Status bits exist for both transmit and receive FIFO buffers in the MODEM_STATUS, FIFO_STATUS and FIFO_H2U_RD registers. These include full, empty, and level flags. Buffer level flags are used to trigger IRQs for HART communication; see also Section 7.3.5.8. The status fields in the FIFO_H2U_RD register represent the state of FIFO_H2U before the read is performed and the data byte is dequeued. This implementation means that if the EMPTY_ FLAG is set, the data byte received in that frame is invalid. Similarly, the LEVEL field represents the 4 MSBs for the FIFO_H2U level before dequeuing. The LSB is not reported, and there are only five internal bits to represent 32 levels; therefore, the LEVEL = 0 is reported when the actual level is 0, 1, or 32. Use FULL_FLAG and EMPTY_FLAG when LEVEL = 0 to differentiate between these three cases.

The FIFO_H2U and FIFO_U2H buffers have 32 levels; however, the level setting for generating IRQ events only uses four bits. For the receive FIFO_H2U buffer, the LSB in the FIFO level threshold comparison is always 1 (FIFO_CFG.H2U_LEVEL_SET[3:0], 1). This configuration is designed to alert the user when FIFO_H2U is getting nearly full so as to enable a timely data dequeue, and prevent the loss of incoming HART data due to FIFO overload. For this reason, the FIFO_H2U_LEVEL_FLAG is also a greater-than (>) comparison to the FIFO_CFG.H2U_LEVEL_SET. For example, if FIFO_CFG.H2U_LEVEL_SET = 4’b1000, then when the level of the FIFO_H2U > 5’b10001, the FIFO_H2U_LEVEL_FLAG is set. Setting FIFO_CFG.H2U_LEVEL_SET = 4’b1111 (default) effectively disables this flag. Use FIFO_H2U_FULL_ FLAG to detect the FIFO_H2U full event. When the FIFO_H2U is full, the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data.

Similarly, for the transmit FIFO_U2H buffer, the LSB in the FIFO level threshold comparison is always 0 (FIFO_CFG.U2H_LEVEL_SET[3:0], 0). This configuration is designed to alert the user when FIFO_U2H is getting nearly empty so as to enable a timely data enqueue, and prevent FIFO_U2H from becoming empty prematurely and causing a gap error on the HART bus. For this reason, the FIFO_U2H_LEVEL_FLAG is also a less-than (<) comparison with the FIFO_CFG.U2H_LEVEL_SET. For example, if FIFO_CFG.U2H_LEVEL_SET = 4’b1000, then when the level of the FIFO_U2H < 5’b10000, the FIFO_U2H_LEVEL_FLAG is set. Setting FIFO_CFG.U2H_LEVEL_SET = 4’b0000 (default) effectively disables this flag. Use FIFO_U2H_EMPTY_ FLAG to detect the FIFO_U2H empty event.

To avoid buffer overflow, monitor the level of FIFO_U2H by watching for a buffer-full or buffer-threshold event. If the FIFO_U2H_LEVEL_FLAG bit in the MODEM_STATUS_MASK register is set to 0, the IRQ pin toggles when the threshold is exceeded. Similarly, an alarm can be triggered based on the FIFO_U2H_FULL_FLAG bit in the MODEM_STATUS register. When the FIFO_U2H is full the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data.