AFEx8201 feature multiple GPIO pins, each independently configurable in either input only or output only or input-ouput mode through GPIO_CFG and GPIO registers. Select either push-pull or pseudo open drain sub modes supported when the GPIO is in output mode. No dedicated GPIO pins are present since the same pins are also configurable for communication interfaces. Based on the selection of the interface protocol and how many pins are used for communication purposes, the AFEx8201 have up to four available GPIOs. Refer to Section 6.5.1 for detailed diagrams of available GPIOs in each communication mode. If a GPIO pin is unused or undriven, the pin must be tied resistively to either IOVDD or GND according to the connection diagrams in Section 6.5.1. Unconnected floating input pins lead to unknown states for the communication interfaces and varying supply currents for the AFEx8201. When functioning as an output, each GPIO pin is capable of sourcing and sinking current and when functioning as an input the register address 0x1C reflects the digital state of the GPIO pins (for details of source and sink capabilities and input thresholds, see Section 5.5). The minimum pulse width for transition detection is t_{PULSE_GPIO}. When a state transition occurs on a GPIO input, the new state must be held for a minimum of t_{PULSE_GPIO} for detection by the AFEx8201.