JAJSNU4A May   2023  – June 2024 AFE78201 , AFE88201

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2  Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3  Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4  IRQ
      5. 6.3.5  Internal Reference
      6. 6.3.6  Integrated Precision Oscillator
      7. 6.3.7  Precision Oscillator Diagnostics
      8. 6.3.8  One-Time Programmable (OTP) Memory
      9. 6.3.9  GPIO
      10. 6.3.10 Timer
      11. 6.3.11 Unique Chip Identifier (ID)
      12. 6.3.12 Scratch Pad Register
    4. 6.4 Device Functional Modes
      1. 6.4.1 Register Built-In Self-Test (RBIST)
      2. 6.4.2 DAC Power-Down Mode
      3. 6.4.3 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
      2. 6.5.2 GPIO Programming
      3. 6.5.3 Serial Peripheral Interface (SPI)
        1. 6.5.3.1 SPI Frame Definition
        2. 6.5.3.2 SPI Read and Write
        3. 6.5.3.3 Frame Error Checking
        4. 6.5.3.4 Synchronization
      4. 6.5.4 UART Interface
        1. 6.5.4.1 UART Break Mode (UBM)
      5. 6.5.5 Status Bits
      6. 6.5.6 Watchdog Timer
  8. 7 Register Maps
    1. 7.1 AFEx8201 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Analog Output Module
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 XTR305
            1. 8.2.1.2.1.1 Current-Output Mode
            2. 8.2.1.2.1.2 Voltage Output Mode
            3. 8.2.1.2.1.3 Diagnostic Features
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

6.5.5 Status Bits

In SPI mode and UBM, every response from the AFEx8201 includes a set of status bits. For SPI mode bit order, see Section 6.5.3.1. For UBM bit order, Section 6.5.4.1.

Table 6-10 Status Bits
STATUS BIT DESCRIPTION NOTES / REFERENCE
ALARM_IRQ 1h = ALARM_IRQ asserted
0h = Normal operation		 From the GEN_STATUS(1) register (Table 7-29).
See also Section 6.3.4.
CRC_ERR
(CRC enabled SPI only) 		1h = CRC error detect in input frame
0h = No CRC error detected 		Generated by the SPI on a frame by frame basis.
See Section 6.5.3.3.
GEN_IRQ 1h = GEN_IRQ asserted
0h = Normal Operation		 From the ALARM_STATUS(1) register (Table 7-28).
See also Section 6.3.4.
OSC_DIV_1024 (UBM mode)

1h = Sampled signal is high

0h = Sampled signal is low

 Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. See also Section 6.3.7.
OSC_DIV_2 (SPI mode) 1h = Sampled signal is high
0h = Sampled signal is low		 Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. See also Section 6.3.7.
R/IRQn (UBM only) 1h = Read request
0h = IRQ event		 Generated by the UART interface on a frame by frame basis.
See Section 6.5.4.1 for details.
RBIST 1h = RBIST busy (registers not readable)
0h = RBIST done (registers readable)		 RBIST running status.
See Section 6.4.1 for details.
RESET 1h = First readback after RESET
0h = All other readbacks		 From the GEN_STATUS register (Table 7-29).
See also Section 6.4.3.
(1) ALARM_STATUS, and GEN_STATUS registers contain cross-readable IRQ flags for the other register. The ALARM_STATUS register has the GEN_IRQ bit. GEN_STATUS has the ALARM_IRQ bit. This functionality enables the system microcontroller to always get full status information by reading only one register, and thus save power.