JAJSNU4A
May 2023 – June 2024
AFE78201
,
AFE88201
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
5.7
Timing Diagrams
5.8
Typical Characteristics: VOUT DAC
5.9
Typical Characteristics: ADC
5.10
Typical Characteristics: Reference
5.11
Typical Characteristics: Power Supply
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Digital-to-Analog Converter (DAC) Overview
6.3.1.1
DAC Resistor String
6.3.1.2
DAC Buffer Amplifier
6.3.1.3
DAC Transfer Function
6.3.1.4
DAC Gain and Offset Calibration
6.3.1.5
Programmable Slew Rate
6.3.1.6
DAC Register Structure and CLEAR State
6.3.2
Analog-to-Digital Converter (ADC) Overview
6.3.2.1
ADC Operation
6.3.2.2
ADC Custom Channel Sequencer
6.3.2.3
ADC Synchronization
6.3.2.4
ADC Offset Calibration
6.3.2.5
External Monitoring Inputs
6.3.2.6
Temperature Sensor
6.3.2.7
Self-Diagnostic Multiplexer
6.3.2.8
ADC Bypass
6.3.3
Programmable Out-of-Range Alarms
6.3.3.1
Alarm-Based Interrupts
6.3.3.2
Alarm Action Configuration Register
6.3.3.3
Alarm Voltage Generator
6.3.3.4
Temperature Sensor Alarm Function
6.3.3.5
Internal Reference Alarm Function
6.3.3.6
ADC Alarm Function
6.3.3.7
Fault Detection
6.3.4
IRQ
6.3.5
Internal Reference
6.3.6
Integrated Precision Oscillator
6.3.7
Precision Oscillator Diagnostics
6.3.8
One-Time Programmable (OTP) Memory
6.3.9
GPIO
6.3.10
Timer
6.3.11
Unique Chip Identifier (ID)
6.3.12
Scratch Pad Register
6.4
Device Functional Modes
6.4.1
Register Built-In Self-Test (RBIST)
6.4.2
DAC Power-Down Mode
6.4.3
Reset
6.5
Programming
6.5.1
Communication Setup
6.5.1.1
SPI Mode
6.5.1.2
UART Mode
6.5.2
GPIO Programming
6.5.3
Serial Peripheral Interface (SPI)
6.5.3.1
SPI Frame Definition
6.5.3.2
SPI Read and Write
6.5.3.3
Frame Error Checking
6.5.3.4
Synchronization
6.5.4
UART Interface
6.5.4.1
UART Break Mode (UBM)
6.5.5
Status Bits
6.5.6
Watchdog Timer
7
Register Maps
7.1
AFEx8201 Registers
8
Application and Implementation
8.1
Application Information
8.1.1
Multichannel Configuration
8.2
Typical Application
8.2.1
Analog Output Module
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
XTR305
8.2.1.2.1.1
Current-Output Mode
8.2.1.2.1.2
Voltage Output Mode
8.2.1.2.1.3
Diagnostic Features
8.2.1.3
Application Curves
8.3
Initialization Setup
8.4
Power Supply Recommendations
8.5
Layout
8.5.1
Layout Guidelines
8.5.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
ドキュメントの更新通知を受け取る方法
9.3
サポート・リソース
9.4
Trademarks
9.5
静電気放電に関する注意事項
9.6
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
RRU|24
サーマルパッド・メカニカル・データ
8.2.1.3
Application Curves
Figure 8-6
DAC Code to XTR Output Current
Figure 8-7
DAC Code to XTR Output Voltage