JAJSNU4A May   2023  – June 2024 AFE78201 , AFE88201

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2  Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3  Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4  IRQ
      5. 6.3.5  Internal Reference
      6. 6.3.6  Integrated Precision Oscillator
      7. 6.3.7  Precision Oscillator Diagnostics
      8. 6.3.8  One-Time Programmable (OTP) Memory
      9. 6.3.9  GPIO
      10. 6.3.10 Timer
      11. 6.3.11 Unique Chip Identifier (ID)
      12. 6.3.12 Scratch Pad Register
    4. 6.4 Device Functional Modes
      1. 6.4.1 Register Built-In Self-Test (RBIST)
      2. 6.4.2 DAC Power-Down Mode
      3. 6.4.3 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
      2. 6.5.2 GPIO Programming
      3. 6.5.3 Serial Peripheral Interface (SPI)
        1. 6.5.3.1 SPI Frame Definition
        2. 6.5.3.2 SPI Read and Write
        3. 6.5.3.3 Frame Error Checking
        4. 6.5.3.4 Synchronization
      4. 6.5.4 UART Interface
        1. 6.5.4.1 UART Break Mode (UBM)
      5. 6.5.5 Status Bits
      6. 6.5.6 Watchdog Timer
  8. 7 Register Maps
    1. 7.1 AFEx8201 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Analog Output Module
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 XTR305
            1. 8.2.1.2.1.1 Current-Output Mode
            2. 8.2.1.2.1.2 Voltage Output Mode
            3. 8.2.1.2.1.3 Diagnostic Features
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RRU|24
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 RRU Package, 24-pin UQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AIN0 15 AI ADC input voltage. The input range is 0 V to 2 × VREF.
ALARM 24 DO Alarm notification pin, open drain, active low. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z).
GND 14 P Digital and analog ground. Ground reference point for all circuitry on the device.
GND 21 P Digital and analog ground.
GND 22 P Digital and analog ground.
GPIO0/ CLK_OUT 11 DO/DI General-purpose input/output (GPIO) pin. Can be configured as a clock output for the 1.2288-MHz internal clock or as a timer. In Hi-Z if not driven. An external pullup or pulldown resistor is required.
GPIO1 3 DO/DI General-purpose input/output (GPIO) pin. In Hi-Z if not driven. An external pullup or pulldown resistor is required.
GPIO2/ UARTOUT 2 DO/DI General-purpose input/output (GPIO) pin. Configured as UART data output at power up. This pin can be configured to function as IRQ pin in SPI only mode. In Hi-Z if not driven. An external pullup or pulldown resistor is required.
GPIO3/ UARTIN 1 DI/DO General-purpose input/output (GPIO) pin. Configured as UART data input at power up. Connect to IOVDD or logic high if not used. An external pullup or pulldown resistor is required.
GPIO4/ SDO 9 DO/DI General-purpose input/output (GPIO) pin. Can be configured as an SPI data output in SPI mode. Data are output on the rising edge of SCLK when CS is low. Interrupt request (IRQ) pin in the UART break mode (UBM). The output is in Hi-Z at power up and must be enabled in the CONFIG register. An external pullup or pulldown resistor is required.
GPIO5/ SDI 8 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI data input at power up. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. SDI is a Schmitt-trigger logic input. An external pullup or pulldown resistor is required.
GPIO6/ CS 10 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI chip-select input at power up. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in Hi-Z and data on SDI are ignored. An external pullup or pulldown resistor is required.
IOVDD 12 P Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces.
NC 23 — Must be left unconnected.
POL_SEL/ AIN1 16 DI/AI ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to 2 × VREF. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage.
PVDD 17 P Power supply for the internal low-dropout regulator (LDO), ADC input and VOUT DAC output.
REF_EN 5 DI Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin.
REF_GND 20 P GND reference for VREFIO pin.
RESET 6 DI Reset pin, active low. Logic low on this pin turns off the internal oscillator and resets the device. Logic high returns the device to normal operation. Do not leave any digital pins floating.
SCLK 7 DI SPI clock. Data are transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input. Connect to GND or logic low if not used. Do not leave any digital pins floating.
SCLR 4 DI DAC clear input pin in SPI mode. A logic high on this pin forces the DAC output into a CLEAR state. Connect to GND in UBM. Do not leave any digital input pins floating.
VDD 13 P/AO Internal low voltage LDO output. When 2.7 V to 5.5 V on PVDD pin is provided, the internal LDO is enabled. Connect a 1-μF to 10-μF capacitor on this pin.
VOUT 18 AO DAC output voltage.
VREFIO 19 AI/AO When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this case, a load capacitance of 70 nF to 130 nF is required for stability. When disabled, this pin is the external 1.25‑V reference input.
(1) AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power.