JAJSNU4A May   2023  – June 2024 AFE78201 , AFE88201

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2  Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3  Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4  IRQ
      5. 6.3.5  Internal Reference
      6. 6.3.6  Integrated Precision Oscillator
      7. 6.3.7  Precision Oscillator Diagnostics
      8. 6.3.8  One-Time Programmable (OTP) Memory
      9. 6.3.9  GPIO
      10. 6.3.10 Timer
      11. 6.3.11 Unique Chip Identifier (ID)
      12. 6.3.12 Scratch Pad Register
    4. 6.4 Device Functional Modes
      1. 6.4.1 Register Built-In Self-Test (RBIST)
      2. 6.4.2 DAC Power-Down Mode
      3. 6.4.3 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
      2. 6.5.2 GPIO Programming
      3. 6.5.3 Serial Peripheral Interface (SPI)
        1. 6.5.3.1 SPI Frame Definition
        2. 6.5.3.2 SPI Read and Write
        3. 6.5.3.3 Frame Error Checking
        4. 6.5.3.4 Synchronization
      4. 6.5.4 UART Interface
        1. 6.5.4.1 UART Break Mode (UBM)
      5. 6.5.5 Status Bits
      6. 6.5.6 Watchdog Timer
  8. 7 Register Maps
    1. 7.1 AFEx8201 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Analog Output Module
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 XTR305
            1. 8.2.1.2.1.1 Current-Output Mode
            2. 8.2.1.2.1.2 Voltage Output Mode
            3. 8.2.1.2.1.3 Diagnostic Features
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

5.5 Electrical Characteristics

all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT DAC STATIC PERFORMANCE
Resolution AFE88201 16 Bits
AFE78201 14
INL Integral nonlinearity(1) AFE88201, TA = –40°C to +125°C –12 12 LSB
AFE88201, TA = –40°C to +85°C –4 4
AFE78201 –3 3
DNL Differential nonlinearity(1) –1 1 LSB
TUE Total unadjusted error(1) TA = –40°C to +125°C –0.1 0.1 %FSR
TA = –40°C to +85°C –0.08 0.08
TA = 25°C –0.05 0.05
Zero code error, no load TA = –40°C to +125°C 1 mV
TA = –40°C to +85°C 1
TA = 25°C 0.5
Zero code error temperature coefficient ±3 ppm/°C
Offset error(1) TA = –40°C to +125°C –0.07 0.07 %FSR
TA = –40°C to +85°C –0.05 0.05
TA = 25°C –0.03 0.03
Offset error temperature coefficient (1) ±3 ppm/°C
Gain error(1) TA = –40°C to +125°C –0.1 0.1 %FSR
TA = –40°C to +85°C –0.08 0.08
TA = 25°C –0.05 0.05
Gain error temperature coefficient(1) ±3 ppm FSR/°C
Full-scale error TA = –40°C to +125°C –0.1 0.1 %FSR
TA = –40°C to +85°C –0.08 0.08
TA = 25°C –0.05 0.05
Full-scale error temperature coefficient ±3 ppm FSR/°C
VOUT DAC DYNAMIC PERFORMANCE
ts Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB 65 µs
10-mV step settling to ±2 LSB 30
Slew rate Full-scale transition measured from 10% to 90% 30 mV/µs
Vn Output noise 0.1 Hz to 10 Hz, DAC at midscale 0.25 LSBpp
100-kHz bandwidth, DAC at midscale 32 µVrms
Vn Output noise density Measured at 1 kHz, DAC at midscale, PVDD = 3 V 180 nV/√Hz
Measured at 1 kHz, DAC at midscale, PVDD = 5 V 260
Power supply rejection ratio (ac) 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. 85 dB
Code change glitch impulse Midcode ±1 LSB (including feedthrough) 4.5 nV-s
Code change glitch magnitude Midcode ±1 LSB (including feedthrough), 
PVDD = 5 V		 1.5 mV
Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 1 nV-s
VOUT DAC OUTPUT CHARACTERISTICS
Output voltage 0 2.5 V
VOUT alarm output high 2.35 2.5 2.65 V
VOUT alarm output low 0.285 0.3 0.315 V
RLOAD Resistive load(2) 10 kΩ
CLOAD Capacitive load(2) 100 pF
Load regulation DAC at midscale, –1 mA ≤ IOUT ≤ +1 mA 10 µV/mA
Short-circuit current Full-scale output shorted to GND 5 mA
Zero output shorted to VDD 5
Output voltage headroom to PVDD DAC at full code, IOUT = 1 mA (sourcing) 200 mV
ZO Large signal dc output impedance To GND, DAC at code 0 60 Ω
DAC at midscale 10 mΩ
DAC at code 65535 10
Output Hi-Z 500 kΩ
Power supply rejection ratio (dc) DAC at midscale 0.1 mV/V
Output voltage drift vs time, ideal VREF TA = 35°C, VOUT = midscale, 1000 hours ±5 ppmFSR
DIAGNOSTIC ADC
Input voltage 0 2.5 V
Resolution 12 Bits
DNL Differential nonlinearity Specified 12-bit monotonic –1 ±0.2 1 LSB
INL Integral nonlinearity –4 ±1 4 LSB
Offset error After calibration –10 ±1.6 10 LSB
Gain error –0.8 ±0.13 0.8 %FSR
Noise ±4 LSB
Input capacitance 6 pF
Input bias current ADC not converting –50 50 nA
Acquisition time 52 µs
Conversion time 210 µs
Conversion rate 3.84 kSPS
Temperature sensor accuracy 5 °C
INTERNAL OSCILLATOR
Frequency TA = –40°C to +125°C 1.2165 1.2288 1.2411 MHz
VOLTAGE REFERENCE INPUT
ZVREFIO Reference input impedance (VREFIO) 125 kΩ
CVREFIO Reference input capacitance (VREFIO) 100 pF
VOLTAGE REFERENCE OUTPUT
Output (initial accuracy)(3) TA = 25°C 1.248 1.25 1.252 V
Output drift(3) TA = –40°C to +125°C 10 ppm/℃
Output impedance(3) 0.1 Ω
Output noise(3) 0.1 Hz to 10 Hz 7.5 µVPP
Output noise density(3) Measured at 10 kHz, reference load = 100 nF 200 nV/√Hz
Load current(3) Sourcing, 0.1% VREF change from nominal 2.5 mA
Sinking, 0.1% VREF change from nominal 0.3
Load regulation(3) Sourcing, 0 mA to 2.5 mA 4 µV/mA
COUT Stable output capacitance TA = –40°C to +125°C, 
ESR from 10 mΩ to 400 mΩ		 70 100 130 nF
Line regulation(3) 100 µV/V
Output voltage drift vs time(3) TA = 35°C, 1000 hours ±100 ppm
Thermal hysteresis(3) 1st cycle 500 µV
Additional cycles 25 µV
VDD VOLTAGE REGULATOR OUTPUT
Output voltage 1.71 1.8 1.89 V
Output impedance(3) Sourcing, 0.5 mA to 2.5 mA 3 Ω
Load current(3) Sourcing, 1% VDD change from nominal 4 mA
THERMAL ALARM
Alarm trip point 130 °C
Warning trip point 85 °C
Hysteresis 12 °C
Trip point absolute accuracy 5 °C
Trip point relative accuracy 2 °C
DIGITAL INPUT CHARACTERISTICS
VIH High-level input voltage 0.7 V/IOVDD
VIL Low-level input voltage 0.3 V/IOVDD
Hysteresis voltage 0.05 V/IOVDD
Input current –1.56 1.56 µA
Pin capacitance Per pin 10 pF
DIGITAL OUTPUT CHARACTERISTICS
VOH High-level output voltage ISOURCE = 1 mA 0.8 V/IOVDD
VOL Low-level output voltage ISINK = 1 mA 0.2 V/IOVDD
VOL Open-drain low-level output voltage ISINK = 2 mA 0.3 V
Output pin capacitance 10 pF
POWER REQUIREMENTS
IPVDD Current flowing into PVDD DAC at zero-scale, SPI static 170 210 µA
IREFIO Internal reference current consumption 52 70 µA
IADC ADC current consumption ADC converting at 3.84 kSPS 10 µA
CVDD Recommended VDD decoupling capacitance 1 10 µF
IIOVDD Current flowing into IOVDD SPI static 10 25 µA
IVREFIO Current flowing into VREFIO DAC at midscale code 10 µA
(1) End point fit between code 512 to code 65,535 for 16-bit, code 128 to code 16,383 for 14-bit, DAC output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization.
(2) Not production tested. Design target.
(3) Not production tested. Derived from the characterization data.