First-in, first-out (FIFO) buffers are used to transmit and receive HART data using both the SPI and UART. Both the transmit FIFO (FIFO_U2H) and receive FIFO (FIFO_H2U) buffers are 32 rows and 9-bits wide. The 9-bit width allows the storage of the parity bit with the data byte. Bit[8] is the parity bit as received by either the UART or HART demodulator, depending on the direction of the data flow. The device does not calculate the parity bit in this case, and transmits the data with the wrong parity bit if the wrong parity bit was received. Bits[7:0] are the data.

The AFEx82H1 HART implementation is shown in Figure 6-17.

Figure 6-17 HART Architecture

HART data bytes are enqueued into a transmit FIFO_U2H buffer using the SPI or UART. The input data bits are translated into the mark (1200 Hz) and space (2200 Hz) FSK analog signals (see Figure 6-23) used in HART communication by the internal HART transmit modulator. The receive demodulator enqueues HART data into the receive FIFO_H2U buffer. An arbiter is implemented with signals to CD and from the RTS pins to manage the HART physical connections on MOD_OUT, and either the RX_IN or RX_INF pin. To enable efficient and error-free communication, the arbiter in conjunction with the two FIFO buffers can be used to produce an IRQ for the system controller.

An incorrect stop bit in the HART receive character causes a HART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the HART data are not enqueued into FIFO_H2U. If the frame error check is not masked, an IRQ event is also triggered.

Similarly, an incorrect stop bit in the UARTIN character causes a UART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the UART data are not enqueued into FIFO_U2H. If the frame error check is not masked, an IRQ event is also triggered.