JAJSNU3 December   2023 AFE782H1 , AFE882H1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: HART Modem
    12. 5.12 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2  Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3  Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4  IRQ
      5. 6.3.5  HART Interface
        1. 6.3.5.1  FIFO Buffers
          1. 6.3.5.1.1 FIFO Buffer Access
          2. 6.3.5.1.2 FIFO Buffer Flags
        2. 6.3.5.2  HART Modulator
        3. 6.3.5.3  HART Demodulator
        4. 6.3.5.4  HART Modem Modes
          1. 6.3.5.4.1 Half-Duplex Mode
          2. 6.3.5.4.2 Full-Duplex Mode
        5. 6.3.5.5  HART Modulation and Demodulation Arbitration
          1. 6.3.5.5.1 HART Receive Mode
          2. 6.3.5.5.2 HART Transmit Mode
        6. 6.3.5.6  HART Modulator Timing and Preamble Requirements
        7. 6.3.5.7  HART Demodulator Timing and Preamble Requirements
        8. 6.3.5.8  IRQ Configuration for HART Communication
        9. 6.3.5.9  HART Communication Using the SPI
        10. 6.3.5.10 HART Communication Using UART
        11. 6.3.5.11 Memory Built-In Self-Test (MBIST)
      6. 6.3.6  Internal Reference
      7. 6.3.7  Integrated Precision Oscillator
      8. 6.3.8  Precision Oscillator Diagnostics
      9. 6.3.9  One-Time Programmable (OTP) Memory
      10. 6.3.10 GPIO
      11. 6.3.11 Timer
      12. 6.3.12 Unique Chip Identifier (ID)
      13. 6.3.13 Scratch Pad Register
    4. 6.4 Device Functional Modes
      1. 6.4.1 DAC Power-Down Mode
      2. 6.4.2 Register Built-In Self-Test (RBIST)
      3. 6.4.3 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
        3. 6.5.1.3 SPI Plus UART Mode
        4. 6.5.1.4 HART Functionality Setup Options
      2. 6.5.2 GPIO Programming
      3. 6.5.3 Serial Peripheral Interface (SPI)
        1. 6.5.3.1 SPI Frame Definition
        2. 6.5.3.2 SPI Read and Write
        3. 6.5.3.3 Frame Error Checking
        4. 6.5.3.4 Synchronization
      4. 6.5.4 UART Interface
        1. 6.5.4.1 UART Break Mode (UBM)
          1. 6.5.4.1.1 Interface With FIFO Buffers and Register Map
      5. 6.5.5 Status Bits
      6. 6.5.6 Watchdog Timer
  8. 7 Register Maps
    1. 7.1 AFEx82H1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Current Loop Control
          2. 8.2.1.2.2 HART Connections
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4.2 Register Built-In Self-Test (RBIST)

The AFEx82H1 feature a register built-in self-test (RBIST) that runs on all the registers listed in Table 7-14 through a CRC calculation in the order the registers are listed in Table 7-14. If a register is reserved, the reset value is used in the calculation of the RBIST. If the final CRC value is zero, then no error is present in the configuration of the registers. If a non-zero value is present at the end of the calculation, then there is a configuration error. The polynomial used has a Hamming distance (HD) of 4 for data packets up to 2048 bits. With HD = 4, the CRC detects any combination of 4-bit errors within the stored data. Independently calculate the expected CRC polynomial and store the output in the RBIST_CRC register at 3Fh.

The final value of the CRC is read in the CRC_RD register at address 3Eh. This value is updated while either an RBIST or shadow load is running. Both the RBIST and OTP memory use the same CRC calculation engine and polynomial. The value in the CRC_RD register remains constant until another RBIST or SHADOWLOAD in TRIGGER register (0Ah) is triggered.

Set TRIGGER.RBIST to 1 to initiate an RBIST. The TRIGGER.RBIST bit stays high as long as the RBIST is running and clears when the self-test is complete. While the RBIST is running, the registers cannot be written to or read. Send NOP commands and monitor the RBIST SDO status bit to determine if the RBIST has completed.

In UBM, the RBIST does not interfere with register communication. UBM communication is slow enough that the RBIST completes before any following read or write command.

The GEN_STATUS.BIST_DONE and GEN_STATUS.BIST_FAIL bits have the same functionality for both MBIST and RBIST. GEN_STATUS.BIST_MODE is used to select between two tests (1 = RBIST and 0 = MBIST). This bit is sticky until the GEN_STATUS register is read.

The FIFO_CFG.FIFO_H2U_FLUSH and FIFO_CFG.FIFO_U2H_FLUSH bits are write-self-clear (WSC) and considered 0 by the CRC module.

The 16-bit CRC used to generate the RBIST is compliant to the openSAFETY (0x755B) standard with the following polynomial:

x16 + x14 + x13 + x12 + x10 + x8 + x6 + x4 + x3 + x1 + 1.

The list of registers covered by the RBIST is listed in Table 7-14. Not all registers feature the RBIST.

Table 6-9 List of Registers Covered by RBIST
ADDR (HEX) REGISTER RESET (HEX)
01h DAC_DATA 0000h
02h CONFIG 0036h
03h DAC_CFG 0B00h
04h DAC_GAIN 8000h
05h DAC_OFFSET 0000h
06h DAC_CLR_CODE 0000h
08h ADC_CFG 8810h
09h ADC_INDEX_CFG 0080h
0Bh SPECIAL_CFG 0000h
0Dh RESERVED 0100h
0Eh MODEM_CFG 0040h
0Fh FIFO_CFG 00F0h
10h ALARM_ACT 8020h
11h WDT 0018h
12h AIN0_THRESHOLD FF00h
13h AIN1_THRESHOLD FF00h
14h TEMP_THRESHOLD FF00h
1Bh GPIO_CFG 00FFh
1Dh ALARM_STATUS_MASK EFDFh
1Eh GEN_STATUS_MASK FFFFh
1Fh MODEM_STATUS_MASK FFFFh
3Fh RBIST_CRC 0000h