SPRS657F February   2010  – January 2017 AM1705

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 Memory Map Summary
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  External Memory Interface A (ASYNC)
      4. 3.6.4  External Memory Interface B (SDRAM only)
      5. 3.6.5  Serial Peripheral Interface Modules (SPI0, SPI1)
      6. 3.6.6  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      7. 3.6.7  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      8. 3.6.8  Enhanced Quadrature Encoder Pulse Module (eQEP)
      9. 3.6.9  Boot
      10. 3.6.10 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      11. 3.6.11 Inter-Integrated Circuit Modules(I2C0, I2C1)
      12. 3.6.12 Timers
      13. 3.6.13 Multichannel Audio Serial Ports (McASP0, McASP1)
      14. 3.6.14 Universal Serial Bus Modules (USB0)
      15. 3.6.15 Ethernet Media Access Controller (EMAC)
      16. 3.6.16 Multimedia Card/Secure Digital (MMC/SD)
      17. 3.6.17 Reserved and No Connect
      18. 3.6.18 Supply and Ground
      19. 3.6.19 Unused USB0 (USB2.0) Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-on Sequence
      2. 6.3.2 Power-off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 PLL Controller 0 Registers
    7. 6.7  Interrupts
      1. 6.7.1 ARM CPU Interrupts
        1. 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 6.7.1.2 AINTC Hardware Vector Generation
        3. 6.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 6.7.1.4 AINTC System Interrupt Assignments on the device
        5. 6.7.1.5 AINTC Memory Map
    8. 6.8  General-Purpose Input/Output (GPIO)
      1. 6.8.1 GPIO Register Description(s)
      2. 6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    9. 6.9  EDMA
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Connection Examples
      3. 6.10.3 External Memory Interface A (EMIFA) Registers
      4. 6.10.4 EMIFA Electrical Data/Timing
    11. 6.11 External Memory Interface B (EMIFB)
      1. 6.11.1 EMIFB SDRAM Loading Limitations
      2. 6.11.2 Interfacing to SDRAM
      3. 6.11.3 EMIFB Registers
      4. 6.11.4 EMIFB Electrical Data/Timing
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Peripheral Register Description(s)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Registers
      2. 6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    16. 6.16 Multichannel Audio Serial Ports (McASP0, McASP1)
      1. 6.16.1 McASP Peripheral Registers Description(s)
      2. 6.16.2 McASP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
        2. 6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
    18. 6.18 Enhanced Capture (eCAP) Peripheral
    19. 6.19 Enhanced Quadrature Encoder (eQEP) Peripheral
    20. 6.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 Timers
      1. 6.21.1 Timer Electrical Data/Timing
    22. 6.22 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 6.22.1 I2C Device-Specific Information
      2. 6.22.2 I2C Peripheral Registers Description(s)
      3. 6.22.3 I2C Electrical Data/Timing
        1. 6.22.3.1 Inter-Integrated Circuit (I2C) Timing
    23. 6.23 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.23.1 UART Peripheral Registers Description(s)
      2. 6.23.2 UART Electrical Data/Timing
    24. 6.24 USB0 OTG (USB2.0 OTG)
      1. 6.24.1 USB2.0 (USB0) Electrical Data/Timing
      2. 6.24.2 USB0 Unused Signal Configuration
    25. 6.25 Power and Sleep Controller (PSC)
      1. 6.25.1 Power Domain and Module Topology
        1. 6.25.1.1 Power Domain States
        2. 6.25.1.2 Module States
    26. 6.26 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.26.1 PRUSS Register Descriptions
    27. 6.27 Emulation Logic
      1. 6.27.1 JTAG Port Description
      2. 6.27.2 Scan Chain Configuration Parameters
      3. 6.27.3 Initial Scan Chain Configuration
        1. 6.27.3.1 Adding TAPS to the Scan Chain
      4. 6.27.4 JTAG 1149.1 Boundary Scan Considerations
    28. 6.28 IEEE 1149.1 JTAG
      1. 6.28.1 JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
      2. 6.28.2 JTAG Test-Port Electrical Data/Timing
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for PTP
    2. 8.2 Supplementary Information About the 176-pin PTP PowerPAD™ Package
      1. 8.2.1 Standoff Height
      2. 8.2.2 PowerPAD™ PCB Footprint
    3. 8.3 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PTP|176
サーマルパッド・メカニカル・データ
発注情報

8 Mechanical Packaging and Orderable Information

This section describes the device orderable part numbers, packaging options, materials, thermal and mechanical parameters.

8.1 Thermal Data for PTP

The following table(s) show the thermal resistance characteristics for the PowerPADTM PTP mechanical package.

Table 8-1 Thermal Resistance Characteristics (PowerPADTM Package) [PTP]"

No. °C/W(1) °C/W(2) °C/W(3) °C/W(4) AIR FLOW (m/s)(5)
1 RΘJC Junction-to-case 7.8 9.4 8.6 10.1 N/A
2 RΘJB Junction-to-board 6.2 9.9 7.1 10.6 N/A
3 RΘJA Junction-to-free air 21.3 27.9 23.2 30.6 0.00
4 RΘJMA Junction-to-moving air 14.3 20.2 22.6 0.50
5 13.1 18.6 21.0 1.00
6 12.1 17.4 19.6 2.00
7 11.2 16.2 18.2 4.00
8 PsiJT Junction-to-package top 0.5 0.7 0.8 0.00
9 0.6 0.9 1.0 0.50
10 0.7 1.0 1.1 1.00
11 0.8 1.1 1.3 2.00
12 1.0 1.3 1.5 4.00
13 PsiJB Junction-to-board 6.3 9.5 10.8 0.00
14 5.9 8.8 9.9 0.50
15 5.9 8.7 9.8 1.00
16 5.8 8.6 9.7 2.00
17 5.8 8.5 9.6 4.00
(1) Simulation data, using a model of a JEDEC defined 2S2P system with a 12mmx12mm copper pad on the top and bottom copper layers connected with an 8x8 thermal via array and soldered to the package thermal pad. Power dissipation of 1W assumed, 70C Ambient temp assumed. Signal layer copper coverage 20%, inner layer copper coverage 90%. Actual performance will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness. Power dissipation of 1W and ambient temp of 70C assumed.
(3) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper thickness 2oz (70um) top and bottom.
(4) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper thickness 1oz (35um) top and bottom.
(5) m/s = meters per second

8.2 Supplementary Information About the 176-pin PTP PowerPAD™ Package

This section highlights a few important details about the 176-pin PTP PowerPAD™ package. Texas Instruments' PowerPAD Thermally Enhanced Package Technical Brief (SLMA002) should be consulted when creating a PCB footprint for this device.

8.2.1 Standoff Height

As illustrated in Figure 8-1, the standoff height specification for this device (between 0.050 mm and 0.150 mm) is measured from the seating plane established by the three lowest package pins to the lowest point on the package body. Due to warpage, the lowest point on the package body is located in the center of the package at the exposed thermal pad.

Using this definition of standoff height provides the correct result for determining the correct solder paste thickness. According to TI's PowerPAD Thermally Enhanced Package Technical Brief (SLMA002), the recommended range of solder paste thickness for this package is between 0.152 mm and 0.178 mm.

AM1705 dg_standoff_prs297.gif Figure 8-1 Standoff Height Measurement on 176-pin PTP Package

8.2.2 PowerPAD™ PCB Footprint

In general, for proper thermal performance, the thermal pad under the package body should be as large as possible. However, the soldermask opening for the PowerPAD™ should be sized to match the pad size on the 176-pin PTP package; as illustrated in Figure 8-2.

AM1705 dg_solder_am1705.gif Figure 8-2 Soldermask Opening Should Match Size of Package Thermal Pad

8.3 Packaging Information

The following packaging information and addendum reflect the most current data available for the designated device(s). This data is subject to change without notice and without revision of this document.