JAJSVM4 データシート

JAJSVM4A September 2024 – November 2024 AM2612

ADVANCE INFORMATION

1
1 特長
2 アプリケーション
3 概要
1. 3.1 機能ブロック図
4 Package Comparison
1. 4.1 Related Products
5 Terminal Configuration and Functions
1. 5.1 Pin Diagram
2. 5.2 Pin Attributes
  1. 15
  2. 16
3. 5.3 Signal Descriptions
  1. 18
  2. 5.3.1 ADC
    1. 20
    2. 21
    3. 22
  3. 5.3.2 ADC_CAL
    1. 24
  4. 5.3.3 ADC VREF
    1. 26
  5. 5.3.4 CPSW
    1. 28
    2. 29
    3. 30
    4. 31
    5. 32
    6. 33
    7. 34
  6. 5.3.5 CPTS
    1. 36
  7. 5.3.6 DAC
    1. 38
  8. 5.3.7 EPWM
    1. 40
    2. 41
    3. 42
    4. 43
    5. 44
    6. 45
    7. 46
    8. 47
    9. 48
    10. 49
  9. 5.3.8 EQEP
    1. 51
    2. 52
  10. 5.3.9 FSI
    1. 54
    2. 55
  11. 5.3.10 GPIO
    1. 57
  12. 5.3.11 GPMC0
    1. 59
  13. 5.3.12 I2C
    1. 61
    2. 62
    3. 63
  14. 5.3.13 LIN
    1. 65
    2. 66
    3. 67
  15. 5.3.14 MCAN
    1. 69
    2. 70
  16. 5.3.15 SPI (MCSPI)
    1. 72
    2. 73
    3. 74
    4. 75
  17. 5.3.16 MMC
    1. 77
  18. 5.3.17 Power Supply
    1. 79
  19. 5.3.18 PRU-ICSS
    1. 81
    2. 82
    3. 83
    4. 84
    5. 85
  20. 5.3.19 OSPI
    1. 87
    2. 88
  21. 5.3.20 SDFM
    1. 90
    2. 91
  22. 5.3.21 System and Miscellaneous
    1. 5.3.21.1 Boot Mode Configuration
      1. 94
    2. 5.3.21.2 Clocking
      1. 96
      2. 97
      3. 98
    3. 5.3.21.3 Emulation and Debug
      1. 100
      2. 101
    4. 5.3.21.4 SYSTEM
      1. 103
    5. 5.3.21.5 USB0
      1. 105
    6. 5.3.21.6 VMON
      1. 107
    7. 108
      1. 109
  23. 5.3.22 UART
    1. 111
    2. 112
    3. 113
    4. 114
    5. 115
    6. 116
  24. 5.3.23 XBAR
    1. 118
    2. 119
6 Specifications
7 Detailed Description
1. 7.1 Overview
2. 7.2 Processor Subsystems
  1. 7.2.1 Arm Cortex-R5F Subsystem
8 Applications, Implementation, and Layout
1. 8.1 Device Connection and Layout Fundamentals
9 Device and Documentation Support
10Revision History
11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

ZFG|304

サーマルパッド・メカニカル・データ

発注情報

jajsvm4a_oa

6.3.1 Digital and Analog IO Electrical Characteristics

over recommended operating conditions (unless otherwise noted). The below are for IOs powered at 3.3V

PARAMETER		MIN	TYP	MAX	UNIT
PORz IO
V_IH	High-Level Input Voltage	1.35			V
V_IL	Low-Level Input Voltage			0.5	V
V_HYS	Hysteresis Voltage at an Input	0.070			V
I_L	Input Leakage Current	–2		2	μA
Warm Reset IO
V_IH	High-Level Input Voltage	2			V
V_IL	Low-Level Input Voltage			0.8	V
V_HYS	Hysteresis Voltage at an Input	0.347			V
V_OL	Low Level Output Voltage, Driver Enabled : I_OL = 6 mA			0.45	V
I_L	Input Leakage Current, Receiver Disabled, Pull Disabled	–57			μA
TCK IO
V_IH	High-Level Input Voltage	2.15			V
V_IL	Low-Level Input Voltage			0.55	V
V_HYS	Hysteresis Voltage at an Input	0.4			V
I_L	Input Leakage Current, Receiver Disabled, Pull Disabled	–3.9	8.9	17.2	μA
	Input Leakage Current, Receiver Disabled, Pullup Enabled		106.9	128.2	μA
	Input Leakage Current, Receiver Disabled, Pulldown Enabled		100.3	130.3	μA
I2C OD IOs
V_IH	High-Level Input Voltage	2			V
V_IL	Low-Level Input Voltage			0.8	V
V_HYS	Hysteresis Voltage at an Input	0.165			V
I_L	Input Leakage Current, Receiver Disabled, Pull Disabled	–18		18	μA
V_OL	Low Level Output Voltage, Driver Enabled : I_OL = 3 mA			0.45	V
All Other LVCMOS
V_IH	High- Level Input Voltage	2			V
V_IL	Low-Level Input Voltage			0.8	V
V_HYS	Hysteresis Voltage at an Input	0.265			V
V_OL	Low Level Output Voltage, Driver Enabled : I_OL = 6 mA			0.45	V
V_OH	High Level Output Voltage, Driver Enabled : I_OH = 6 mA	VDDS33⁽¹⁾ – 0.45			V
I_L	Input Leakage Current, Receiver Disabled, Pull Disabled	–18		18	μA
	Input Leakage Current, Receiver Disabled, Pullup Enabled	–243	–100	–19	μA
	Input Leakage Current, Receiver Disabled, Pulldown Enabled	51	100	210	μA

(1) VDDS33 is the voltage on the corresponding power-supply pins(VDDS33, VDDS1833_FLASH0, VDDS1833_FLASH1) on the IC.