SPRSPA7A September   2024  – November 2024 AM2612

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Package Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM261x ZCZ Pin Diagram
      2. 5.1.2 AM261x ZFG Pin Diagram
      3. 5.1.3 AM261x ZEJ Pin Diagram
      4. 5.1.4 AM261x ZNC Pin Diagram
    2. 5.2 Pin Attributes
      1.      15
      2.      16
    3. 5.3 Signal Descriptions
      1.      18
      2. 5.3.1  ADC
        1.       20
        2.       21
        3.       22
      3. 5.3.2  ADC_CAL
        1.       24
      4. 5.3.3  ADC VREF
        1.       26
      5. 5.3.4  CPSW
        1.       28
        2.       29
        3.       30
        4.       31
        5.       32
        6.       33
        7.       34
      6. 5.3.5  CPTS
        1.       36
      7. 5.3.6  DAC
        1.       38
      8. 5.3.7  EPWM
        1.       40
        2.       41
        3.       42
        4.       43
        5.       44
        6.       45
        7.       46
        8.       47
        9.       48
        10.       49
      9. 5.3.8  EQEP
        1.       51
        2.       52
      10. 5.3.9  FSI
        1.       54
        2.       55
      11. 5.3.10 GPIO
        1.       57
      12. 5.3.11 GPMC0
        1.       59
      13. 5.3.12 I2C
        1.       61
        2.       62
        3.       63
      14. 5.3.13 LIN
        1.       65
        2.       66
        3.       67
      15. 5.3.14 MCAN
        1.       69
        2.       70
      16. 5.3.15 SPI (MCSPI)
        1.       72
        2.       73
        3.       74
        4.       75
      17. 5.3.16 MMC
        1.       77
      18. 5.3.17 Power Supply
        1.       79
      19. 5.3.18 PRU-ICSS
        1.       81
        2.       82
        3.       83
        4.       84
        5.       85
      20. 5.3.19 OSPI
        1.       87
        2.       88
      21. 5.3.20 SDFM
        1.       90
        2.       91
      22. 5.3.21 System and Miscellaneous
        1. 5.3.21.1 Boot Mode Configuration
          1.        94
        2. 5.3.21.2 Clocking
          1.        96
          2.        97
          3.        98
        3. 5.3.21.3 Emulation and Debug
          1.        100
          2.        101
        4. 5.3.21.4 SYSTEM
          1.        103
        5. 5.3.21.5 USB0
          1.        105
        6. 5.3.21.6 VMON
          1.        107
        7.       108
          1.        109
      23. 5.3.22 UART
        1.       111
        2.       112
        3.       113
        4.       114
        5.       115
        6.       116
      24. 5.3.23 XBAR
        1.       118
        2.       119
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Electrical Characteristics
      1. 6.3.1 Digital and Analog IO Electrical Characteristics
    4. 6.4 Thermal Resistance Characteristics
      1. 6.4.1 Package Thermal Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 External Oscillator
      2. 8.1.2 JTAG, EMU, and TRACE
      3. 8.1.3 Hardware Reference Design and Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • ZFG|304
サーマルパッド・メカニカル・データ
発注情報

The following list describes the contents of each column in the Pin Attributes table:
  1. Ball Number: Ball numbers assigned to each terminal of the Ball Grid Array package.
  2. Ball Name: Ball name assigned to each terminal of the Ball Grid Array package (this name is typically taken from the primary MUXMODE 0 signal function).
  3. Signal Name: Signal name of all dedicated and pin multiplexed signal functions associated with a ball.
    Note:

    The Pin Attributes table, defines the SoC pin multiplexed signal function implemented at the pin and does not define secondary multiplexing of signal functions implemented in device subsystems. Secondary multiplexing of signal functions are not described in this table. For more information on secondary multiplexed signal functions, see the respective peripheral chapter of the device TRM.

  4. Mux Mode: The MUXMODE value associated with each pin multiplexed signal function:
    • MUXMODE 7 is the primary pin multiplexed signal function. However, the primary pin multiplexed signal function is not necessarily the default pin multiplexed signal function.
    • MUXMODE values 1 through 15 are possible for pin multiplexed signal functions. However, not all MUXMODE values have been implemented. The only valid MUXMODE values are those defined as pin multiplexed signal functions within the Pin Attributes table. Only defined valid values of MUXMODE can be used.
    • Bootstrap defines SOC configuration pins, where the logic state applied to each pin is latched on the rising edge of PORz. These input signal functions are fixed to their respective pins and are not programmable via MUXMODE.
    • An empty box or "-" means Not Applicable.
    Note:
    • The value found in the MUX MODE AFTER RESET column defines the default pin multiplexed signal function selected when PORz is deasserted.
    • Configuring two pins to the same pin multiplexed signal function can yield unexpected results and is not supported. This can be prevented with proper software configuration.

    • Configuring a pad to an undefined multiplexing mode results in undefined behavior and must be avoided.

  5. Type: Signal type and direction:

    • I = Input

    • O = Output

    • ID = Input, with open-drain output function

    • OD = Output, with open-drain output function

    • IO = Input, Output, or simultaneously Input and Output

    • IOD = Input, Output, or simultaneously Input and Output, with open-drain output function

    • IOZ = Input, Output, or simultaneously Input and Output, with three-state output function

    • OZ = Output with three-state output function

    • A = Analog

    • CAP = LDO capacitor

    • PWR = Power

    • GND = Ground

  6. Ball State During Reset (RX/TX/PULL): State of the terminal while PORz is asserted, where RX defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state of internal pull resistors:
    • RX (Input buffer)
      • Off: The input buffer is disabled.
      • On: The input buffer is enabled.
    • TX (Output buffer)
      • Off: The output buffer is disabled.
      • Low: The output buffer is enabled and drives VOL.
    • PULL (Internal pull resistors)
      • Off: Internal pull resistors are turned off.
      • Up: Internal pull-up resistor is turned on.
      • Down: Internal pull-down resistor is turned on.
      • NA: No internal pull resistor.
    • An empty box, or "-" means Not Applicable.
  7. Ball State After Reset (RX/TX/PULL): State of the terminal after PORz is deasserted, where RX defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state of internal pull resistors:
    • RX (Input buffer)
      • Off: The input buffer is disabled.
      • On: The input buffer is enabled.
    • TX (Output buffer)
      • Off: The output buffer is disabled.
      • SS: The subsystem selected with MUXMODE determines the output buffer state.
    • PULL (Internal pull resistors)
      • Off: Internal pull resistors are turned off.
      • Up: Internal pull-up resistor is turned on.
      • Down: Internal pull-down resistor is turned on.
      • NA: No internal pull resistor.
    • An empty box, NA, or "-" means Not Applicable.
  8. Mux Mode After Reset: The value found in this column defines the default pin multiplexed signal function after PORz is deasserted.
    • An empty box, NA, or "-" means Not Applicable.
  9. I/O Voltage: This column describes I/O operating voltage options of the respective power supply, when applicable.
    • An empty box, NA, or "-" means Not Applicable.

    For more information, see valid operating voltage range defined for each power supply in Recommended Operating Conditions.

  10. Power: The power supply of the associated I/O, when applicable.
    • An empty box, NA, or "-" means Not Applicable.
  11. Hys: Indicates if the input buffer associated with this I/O has hysteresis:
    • Yes: Hysteresis Support
    • No: No Hysteresis Support
    • An empty box, NA, or "-" means Not Applicable.

    For more information, see the hysteresis values in Electrical Characteristics.

  12. Pull Type: Indicates the presence of an internal pull-up or pull-down resistor. Internal resistors can be enabled or disabled via software.
    • PU: Internal pull-up Only
    • PD: Internal pull-down Only
    • PU/PD: Internal pull-up and pull-down
    • An empty box, NA, or "-" means No internal pull.
    Note:

    Configuring two pins to the same pin multiplexed signal function is not supported as this yields unexpected results. Issues can be easily prevented with the proper software configuration.

    When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This must be avoided.

  13. Buffer Type: This column defines the buffer type associated with a terminal. This information can be used to determine the applicable Electrical Characteristics table.
    • An empty box, NA, or "-" means Not Applicable.

    For electrical characteristics, refer to the appropriate buffer type table in Electrical Characteristics.

  14. Pad Configuration Register Name: This is the name of the device pad/pin configuration register.
  15. Pad Configuration Register Address: This is the memory address of the device pad/pin configuration register.
  16. Pad Configuration Register Default Value: This is the default value of the register device pad/pin configuration register after PORz is deasserted.