JAJSOB0D october   2022  – july 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
      1. 6.1.1 ZCZ Pin Diagram
    2. 6.2 Pin Attributes
      1.      13
      2.      14
    3. 6.3 Signal Descriptions
      1.      16
      2. 6.3.1  ADC
        1.       18
        2.       19
        3.       20
        4.       21
        5.       22
        6. 6.3.1.1 ADC-CMPSS Signal Connections
      3. 6.3.2  ADC_CAL
        1.       25
      4. 6.3.3  ADC VREF
        1.       27
      5. 6.3.4  CPSW
        1.       29
        2.       30
        3.       31
        4.       32
        5.       33
        6.       34
        7.       35
      6. 6.3.5  CPTS
        1.       37
      7. 6.3.6  DAC
        1.       39
      8. 6.3.7  Emulation and Debug
        1.       41
        2.       42
      9. 6.3.8  EPWM
        1.       44
        2.       45
        3.       46
        4.       47
        5.       48
        6.       49
        7.       50
        8.       51
        9.       52
        10.       53
        11.       54
        12.       55
        13.       56
        14.       57
        15.       58
        16.       59
        17.       60
        18.       61
        19.       62
        20.       63
        21.       64
        22.       65
        23.       66
        24.       67
        25.       68
        26.       69
        27.       70
        28.       71
        29.       72
        30.       73
        31.       74
        32.       75
      10. 6.3.9  EQEP
        1.       77
        2.       78
        3.       79
      11. 6.3.10 FSI
        1.       81
        2.       82
        3.       83
        4.       84
        5.       85
        6.       86
        7.       87
        8.       88
      12. 6.3.11 GPIO
        1.       90
      13. 6.3.12 GPMC
        1.       92
      14. 6.3.13 I2C
        1.       94
        2.       95
        3.       96
        4.       97
        5.       98
      15. 6.3.14 LIN
        1.       100
        2.       101
        3.       102
        4.       103
        5.       104
      16. 6.3.15 MCAN
        1.       106
        2.       107
        3.       108
        4.       109
      17. 6.3.16 SPI (MCSPI)
        1.       111
        2.       112
        3.       113
        4.       114
        5.       115
      18. 6.3.17 MMC
        1.       117
      19. 6.3.18 Power Supply
        1.       119
      20. 6.3.19 PRU-ICSS
        1.       121
        2.       122
        3.       123
        4.       124
        5.       125
      21. 6.3.20 QSPI
        1.       127
      22. 6.3.21 Reserved
        1.       129
      23. 6.3.22 SDFM
        1.       131
        2.       132
      24. 6.3.23 System and Miscellaneous
        1. 6.3.23.1 Boot Mode Configuration
          1.        135
        2. 6.3.23.2 Clocking
          1.        137
          2.        138
          3.        139
        3. 6.3.23.3 SYSTEM
          1.        141
        4. 6.3.23.4 VMON
          1.        143
      25. 6.3.24 UART
        1.       145
        2.       146
        3.       147
        4.       148
        5.       149
        6.       150
      26. 6.3.25 XBAR
        1.       152
    4. 6.4 Pin Connectivity Requirements
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Electrostatic Discharge (ESD) Extended Automotive Ratings
    3. 7.3  Electrostatic Discharge (ESD) Industrial Ratings
    4. 7.4  Power-On Hours (POH) Summary
      1. 7.4.1 Automotive Temperature Profile
    5. 7.5  Recommended Operating Conditions
    6. 7.6  Operating Performance Points
    7. 7.7  Power Consumption Summary
      1. 7.7.1 Power Consumption - Maximum
      2. 7.7.2 Power Consumption - Typical
      3. 7.7.3 Power Consumption - Traction Inverter
    8. 7.8  Electrical Characteristics
      1. 7.8.1 Digital and Analog IO Electrical Characteristics
      2. 7.8.2 Analog-to-Digital Converter (ADC)
      3. 7.8.3 Comparator Subsystem A (CMPSSA)
      4. 7.8.4 Comparator Subsystem B (CMPSSB)
      5. 7.8.5 Digital-to-Analog Converter (DAC)
      6. 7.8.6 Power Management Unit (PMU)
      7. 7.8.7 Safety Comparators
    9. 7.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.9.1 VPP Specifications
      2. 7.9.2 Hardware Requirements
      3. 7.9.3 Programming Sequence
      4. 7.9.4 Impact to Your Hardware Warranty
    10. 7.10 Thermal Resistance Characteristics
      1. 7.10.1 Package Thermal Characteristics
    11. 7.11 Timing and Switching Characteristics
      1. 7.11.1 Timing Parameters and Information
      2. 7.11.2 Power Supply Sequencing
        1. 7.11.2.1 Power-On and Reset Sequencing
          1. 7.11.2.1.1 Power Reset Sequence Description
        2. 7.11.2.2 Power-Down Sequencing
      3. 7.11.3 System Timing
        1. 7.11.3.1 System Timing Conditions
        2. 7.11.3.2 Reset Timing
          1. 7.11.3.2.1 PORz Timing Requirements
          2.        191
          3. 7.11.3.2.2 WARMRSTn Switching Characteristics
          4.        193
          5. 7.11.3.2.3 WARMRSTn Timing Requirements
          6.        195
        3. 7.11.3.3 Safety Signal Timing
          1. 7.11.3.3.1 SAFETY_ERRORn Switching Characteristics
          2.        198
      4. 7.11.4 Clock Specifications
        1. 7.11.4.1 Input Clocks / Oscillators
          1. 7.11.4.1.1 Crystal Oscillator (XTAL) Parameters
          2. 7.11.4.1.2 External Clock Characteristics
        2. 7.11.4.2 Clock Timing
          1. 7.11.4.2.1 Clock Timing Requirements
          2.        205
          3. 7.11.4.2.2 Clock Switching Characteristics
          4.        207
      5. 7.11.5 Peripherals
        1. 7.11.5.1  2-port Gigabit Ethernet MAC (CPSW)
          1. 7.11.5.1.1 CPSW MDIO Timing
            1. 7.11.5.1.1.1 CPSW MDIO Timing Conditions
            2. 7.11.5.1.1.2 CPSW MDIO Timing Requirements
            3. 7.11.5.1.1.3 CPSW MDIO Switching Characteristics
            4.         214
          2. 7.11.5.1.2 CPSW RMII Timing
            1. 7.11.5.1.2.1 CPSW RMII Timing Conditions
            2. 7.11.5.1.2.2 CPSW RMII[x]_REFCLK Timing Requirements - RMII Mode
            3.         218
            4. 7.11.5.1.2.3 CPSW RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode
            5.         220
            6. 7.11.5.1.2.4 CPSW RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode
            7.         222
          3. 7.11.5.1.3 CPSW RGMII Timing
            1. 7.11.5.1.3.1 CPSW RGMII Timing Conditions
            2. 7.11.5.1.3.2 CPSW RGMII[x]_RCLK Timing Requirements - RGMII Mode
            3. 7.11.5.1.3.3 CPSW RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements
            4.         227
            5. 7.11.5.1.3.4 CPSW RGMII[x]_TCLK Switching Characteristics - RGMII Mode
            6. 7.11.5.1.3.5 CPSW RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode
            7.         230
        2. 7.11.5.2  Enhanced Capture (eCAP)
          1. 7.11.5.2.1 ECAP Timing Conditions
          2. 7.11.5.2.2 ECAP Timing Requirements
          3.        234
          4. 7.11.5.2.3 ECAP Switching Characteristics
          5.        236
        3. 7.11.5.3  Enhanced Pulse Width Modulation (ePWM)
          1. 7.11.5.3.1 EPWM Timing Conditions
          2. 7.11.5.3.2 EPWM Timing Requirements
          3.        240
          4. 7.11.5.3.3 EPWM Switching Characteristics
          5.        242
          6.        EPWM Characteristics
        4. 7.11.5.4  Enhanced Quadrature Encoder Pulse (eQEP)
          1. 7.11.5.4.1 EQEP Timing Conditions
          2. 7.11.5.4.2 EQEP Timing Requirements
          3.        247
          4. 7.11.5.4.3 EQEP Switching Characteristics
        5. 7.11.5.5  Fast Serial Interface (FSI)
          1. 7.11.5.5.1 FSI Timing Conditions
          2. 7.11.5.5.2 FSIRX Timing Requirements
          3.        252
          4. 7.11.5.5.3 FSIRX Switching Characteristics
          5. 7.11.5.5.4 FSITX Switching Characteristics
          6.        255
          7. 7.11.5.5.5 FSITX SPI Signaling Mode Switching Characteristics
          8.        257
        6. 7.11.5.6  General Purpose Input/Output (GPIO)
          1. 7.11.5.6.1 GPIO Timing Conditions
          2. 7.11.5.6.2 GPIO Timing Requirements
          3. 7.11.5.6.3 GPIO Switching Characteristics
        7. 7.11.5.7  General Purpose Memory Controller (GPMC)
          1. 7.11.5.7.1 GPMC Timing Conditions
          2. 7.11.5.7.2 GPMC/NOR Flash Timing Requirements - Synchronous Mode 100MHz
          3. 7.11.5.7.3 GPMC/NOR Flash Switching Characteristics - Synchronous Mode 100MHz
          4.        266
          5. 7.11.5.7.4 GPMC/NOR Flash Timing Requirements - Asynchronous Mode 100MHz
          6. 7.11.5.7.5 GPMC/NOR Flash Switching Characteristics - Asynchronous Mode 100MHz
          7.        269
          8. 7.11.5.7.6 GPMC/NAND Flash Timing Requirements - Asynchronous Mode 100MHz
          9. 7.11.5.7.7 GPMC/NAND Flash Switching Characteristics - Asynchronous Mode 100MHz
          10.        272
        8. 7.11.5.8  Inter-Integrated Circuit (I2C)
          1. 7.11.5.8.1 I2C
        9. 7.11.5.9  Local Interconnect Network (LIN)
          1. 7.11.5.9.1 LIN Timing Conditions
          2. 7.11.5.9.2 LIN Timing Requirements
          3. 7.11.5.9.3 LIN Switching Characteristics
        10. 7.11.5.10 Modular Controller Area Network (MCAN)
          1. 7.11.5.10.1 MCAN Timing Conditions
          2. 7.11.5.10.2 MCAN Switching Characteristics
        11. 7.11.5.11 Serial Peripheral Interface (SPI)
          1. 7.11.5.11.1 SPI Timing Conditions
          2. 7.11.5.11.2 SPI Controller Mode Timing Requirements
          3.        285
          4. 7.11.5.11.3 SPI Controller Mode Switching Characteristics (Clock Phase = 0)
          5.        287
          6. 7.11.5.11.4 SPI Peripheral Mode Timing Requirements
          7.        289
          8. 7.11.5.11.5 SPI Peripheral Mode Switching Characteristics
          9.        291
        12. 7.11.5.12 Multi-Media Card/Secure Digital (MMCSD)
          1. 7.11.5.12.1 MMC Timing Conditions
          2. 7.11.5.12.2 MMC Timing Requirements - SD Card Default Speed Mode
          3.        295
          4. 7.11.5.12.3 MMC Switching Characteristics - SD Card Default Speed Mode
          5.        297
          6. 7.11.5.12.4 MMC Timing Requirements - SD Card High Speed Mode
          7.        299
          8. 7.11.5.12.5 MMC Switching Characteristics - SD Card High Speed Mode
          9.        301
        13. 7.11.5.13 Quad Serial Peripheral Interface (QSPI)
          1. 7.11.5.13.1 QSPI Timing Conditions
          2. 7.11.5.13.2 QSPI Timing Requirements
          3.        305
          4. 7.11.5.13.3 QSPI Switching Characteristics
          5.        307
        14. 7.11.5.14 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
          1. 7.11.5.14.1 PRU-ICSS Programmable Real-Time Unit (PRU)
            1. 7.11.5.14.1.1 PRU-ICSS PRU Timing Conditions
            2. 7.11.5.14.1.2 PRU-ICSS PRU Switching Characteristics - Direct Output Mode
            3.         312
            4. 7.11.5.14.1.3 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            5.         314
            6. 7.11.5.14.1.4 PRU-ICSS PRU Timing Requirements - Shift In Mode
            7.         316
            8. 7.11.5.14.1.5 PRU-ICSS PRU Switching Characteristics - Shift Out Mode
            9.         318
          2. 7.11.5.14.2 PRU-ICSS PRU Sigma Delta and Peripheral Interface
            1. 7.11.5.14.2.1 PRU-ICSS PRU Sigma Delta and Peripheral Interface Timing Conditions
            2. 7.11.5.14.2.2 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
            3.         322
            4. 7.11.5.14.2.3 PRU-ICSS PRU Timing Requirements - Peripheral Interface Mode
            5.         324
            6. 7.11.5.14.2.4 PRU-ICSS PRU Switching Characteristics - Peripheral Interface Mode
            7.         326
          3. 7.11.5.14.3 PRU-ICSS Pulse Width Modulation (PWM)
            1. 7.11.5.14.3.1 PRU-ICSS PWM Timing Conditions
            2. 7.11.5.14.3.2 PRU-ICSS PWM Switching Characteristics
            3.         330
          4. 7.11.5.14.4 PRU-ICSS Industrial Ethernet Peripheral (IEP)
            1. 7.11.5.14.4.1 PRU-ICSS IEP Timing Conditions
            2. 7.11.5.14.4.2 PRU-ICSS IEP Timing Requirements - Input Validated with SYNCx
            3.         334
            4. 7.11.5.14.4.3 PRU-ICSS IEP Timing Requirements - Digital IOs
            5.         336
            6. 7.11.5.14.4.4 PRU-ICSS IEP Timing Requirements - LATCHx_IN
            7.         338
          5. 7.11.5.14.5 PRU-ICSS Universal Asynchronous Receiver Transmitter (UART)
            1. 7.11.5.14.5.1 PRU-ICSS UART Timing Conditions
            2. 7.11.5.14.5.2 PRU-ICSS UART Timing Requirements
            3. 7.11.5.14.5.3 PRU-ICSS UART Switching Characteristics
            4.         343
          6. 7.11.5.14.6 PRU-ICSS Enhanced Capture Peripheral (ECAP)
            1. 7.11.5.14.6.1 PRU-ICSS ECAP Timing Conditions
            2. 7.11.5.14.6.2 PRU-ICSS ECAP Timing Requirements
            3.         347
            4. 7.11.5.14.6.3 PRU-ICSS ECAP Switching Characteristics
            5.         349
          7. 7.11.5.14.7 PRU-ICSS MDIO and MII
            1. 7.11.5.14.7.1 PRU-ICSS MDIO Timing
              1. 7.11.5.14.7.1.1 PRU-ICSS MDIO Timing Conditions
              2. 7.11.5.14.7.1.2 PRU-ICSS MDIO Timing Requirements
              3. 7.11.5.14.7.1.3 PRU-ICSS MDIO Switching Characteristics
              4.          355
            2. 7.11.5.14.7.2 PRU-ICSS MII Timing
              1. 7.11.5.14.7.2.1 PRU-ICSS MII Timing Conditions
              2. 7.11.5.14.7.2.2 PRU-ICSS MII Timing Requirements - MII[x]_RX_CLK
              3.          359
              4. 7.11.5.14.7.2.3 PRU-ICSS MII Timing Requirements - MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER
              5.          361
              6. 7.11.5.14.7.2.4 PRU-ICSS MII Switching Characteristics - MII[x]_TX_CLK
              7.          363
              8. 7.11.5.14.7.2.5 PRU-ICSS MII Switching Characteristics - MII[x]_TXD[3:0] and MII[x]_TXEN
              9.          365
        15. 7.11.5.15 Sigma Delta Filter Module (SDFM)
          1. 7.11.5.15.1 SDFM Timing Conditions
          2. 7.11.5.15.2 SDFM Switching Characteristics
        16. 7.11.5.16 Universal Asynchronous Receiver/Transmitter (UART)
          1. 7.11.5.16.1 UART Timing Conditions
          2. 7.11.5.16.2 UART Timing Requirements
          3. 7.11.5.16.3 UART Switching Characteristics
          4.        373
      6. 7.11.6 Emulation and Debug
        1. 7.11.6.1 JTAG
          1. 7.11.6.1.1 JTAG Timing Conditions
          2. 7.11.6.1.2 JTAG Timing Requirements
          3. 7.11.6.1.3 JTAG Switching Characteristics
          4.        379
        2. 7.11.6.2 Trace
          1. 7.11.6.2.1 Debug Trace Timing Conditions
          2. 7.11.6.2.2 Debug Trace Switching Characteristics
          3.        383
    12. 7.12 Decoupling Capacitor Requirements
      1. 7.12.1 Decoupling Capacitor Requirements
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-R5F Subsystem
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Device Connection and Layout Fundamentals
      1. 9.1.1 External Oscillator
      2. 9.1.2 JTAG, EMU, and TRACE
      3. 9.1.3 Hardware Design Guide
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

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発注情報

6.4 Pin Connectivity Requirements

This section describes connectivity requirements for package balls that have specific connectivity requirements and package balls that may be unused.

Note:

All power balls must be supplied with the voltages specified in the Recommended Operating Conditions section, unless otherwise specified in Signal Descriptions.

For additional clarification, "leave unconnected" or "no connect" (NC) mean no signal traces should be connected to these device ball numbers.

Table 6-107 Pin Connectivity Requirements
BALL NUMBER BALL NAME PIN CONNECTIVITY REQUIREMENTS
D4 SAFETY_ERRORn Each of these balls must be connected to ground (VSS) through separate external pull resistors to ensure they are held to a valid logic low level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-down may be used to hold a valid logic low level if no PCB signal trace is connected to the ball.
B3
C5
D5		 TCK
TDI
TMS		 Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure these balls are held to a valid logic high level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-up may be used to hold a valid logic high level if no PCB signal trace is connected to the ball.
A13
B13		 I2C0_SCL
I2C0_SDA		 Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure these balls are held to a valid logic high level.
N1
N4
A11
C10		 QSPI0_D0 (SOP0)
QSPI0_D1
SPI0_CLK (SOP2)
SPI0_D0 (SOP3)		 Each of these balls must be connected to the corresponding power supply(1) or ground (VSS) through separate external pull resistors to ensure these balls are held to a valid logic high or low level as appropriate to select the desired device boot mode.
ADC ZCZ PIN ADC[0:4]_AIN[0:5] Any unused ADCx_AINy input ball for any ADC instance (ADC[0:4]_AIN[0:5]) must be connected (shorted) directly to ground (VSS).
U16
T15		 ADC_CAL0
ADC_CAL1		 If all ADCx_AINy inputs for all ADC instances (ADC[0:4]_AIN[0:5]) are not used, the ADC_CAL[0:1] analog ball must be connected (shorted) directly to ground (VSS).
U2 VSYS_MON If VSYS_MON is not used, this ball may be connected (shorted) directly to ground (VSS).
LVCMOS ZCZ PIN Any LVCMOS Voltage Buffer Pin If a pin has an associated IOMUX Pad Configuration Registration then the ball may remain unconnected. After PORz, the LVCMOS voltage buffer is configured to a default state compatible with an unconnected ball.
(1) To determine which power supply is associated with any IO, see POWER column of the Pin Attributes table.

Note: Internal pull resistors are weak and may not source enough current to maintain a valid logic level for some operating conditions. This may be the case when connected to components with leakage to the opposite logic level, or when external noise sources couple to signal traces attached to balls which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be required to hold a valid logic level on balls with external connections.

If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state which could damage the IO cell.