JAJSRU7C October   2023  – May 2024 AM263P4 , AM263P4-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Device Comparison
    1. 4.1 Device Identification
    2. 4.2 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 ZCZ_C Pin Diagram
      2. 5.1.2 ZCZ_S Pin Diagram
      3. 5.1.3 ZCZ_F Pin Diagram
    2. 5.2 Pin Attributes
      1.      15
      2.      16
    3. 5.3 Signal Descriptions
      1.      18
      2. 5.3.1  ADC
        1.       20
        2.       21
        3.       22
        4.       23
        5.       24
        6. 5.3.1.1 ADC-CMPSS Signal Connections
      3. 5.3.2  ADC Resolver
        1.       27
        2.       28
        3.       29
      4. 5.3.3  ADC_CAL
        1.       31
      5. 5.3.4  ADC VREF
        1.       33
      6. 5.3.5  CPSW
        1.       35
        2.       36
        3.       37
        4.       38
        5.       39
        6.       40
        7.       41
      7. 5.3.6  CPTS
        1.       43
      8. 5.3.7  DAC
        1.       45
      9. 5.3.8  EPWM
        1.       47
        2.       48
        3.       49
        4.       50
        5.       51
        6.       52
        7.       53
        8.       54
        9.       55
        10.       56
        11.       57
        12.       58
        13.       59
        14.       60
        15.       61
        16.       62
        17.       63
        18.       64
        19.       65
        20.       66
        21.       67
        22.       68
        23.       69
        24.       70
        25.       71
        26.       72
        27.       73
        28.       74
        29.       75
        30.       76
        31.       77
        32.       78
      10. 5.3.9  EQEP
        1.       80
        2.       81
        3.       82
      11. 5.3.10 FSI
        1.       84
        2.       85
        3.       86
        4.       87
        5.       88
        6.       89
        7.       90
        8.       91
      12. 5.3.11 GPIO
        1.       93
      13. 5.3.12 I2C
        1.       95
        2.       96
        3.       97
        4.       98
        5.       99
      14. 5.3.13 LIN
        1.       101
        2.       102
        3.       103
        4.       104
        5.       105
      15. 5.3.14 MCAN
        1.       107
        2.       108
        3.       109
        4.       110
        5.       111
        6.       112
        7.       113
        8.       114
      16. 5.3.15 SPI (MCSPI)
        1.       116
        2.       117
        3.       118
        4.       119
        5.       120
        6.       121
        7.       122
        8.       123
      17. 5.3.16 MMC
        1.       125
      18. 5.3.17 OSPI (Shared)
        1.       127
      19. 5.3.18 Power Supply
        1.       129
      20. 5.3.19 PRU-ICSS
        1.       131
        2.       132
        3.       133
        4.       134
        5.       135
      21. 5.3.20 SDFM
        1.       137
        2.       138
      22. 5.3.21 System and Miscellaneous
        1. 5.3.21.1 Boot Mode Configuration
          1.        141
        2. 5.3.21.2 Clocking
          1.        143
          2.        144
          3.        145
        3. 5.3.21.3 Emulation and Debug
          1.        147
          2.        148
        4. 5.3.21.4 SYSTEM
          1.        150
        5. 5.3.21.5 VMON
          1.        152
        6. 5.3.21.6 Reserved
          1.        154
      23. 5.3.22 UART
        1.       156
        2.       157
        3.       158
        4.       159
        5.       160
        6.       161
      24. 5.3.23 XBAR
        1.       163
        2.       164
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Electrostatic Discharge (ESD) Extended Automotive Ratings
    3. 6.3  Electrostatic Discharge (ESD) Industrial Ratings
    4. 6.4  Power-On Hours (POH) Summary
      1. 6.4.1 Automotive Temperature Profile
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
    7. 6.7  Power Consumption Summary
      1. 6.7.1 Power Consumption - Maximum
      2. 6.7.2 Power Consumption - Typical
      3. 6.7.3 Power Consumption - Traction Inverter
    8. 6.8  Electrical Characteristics
      1. 6.8.1 Digital and Analog IO Electrical Characteristics
      2. 6.8.2 Analog to Digital Converter Characteristics
        1. 6.8.2.1 Analog-to-Digital Converter (ADC)
        2. 6.8.2.2 Resolver Analog-to-Digital Converter (ADC_R)
        3. 6.8.2.3 ADC Input Model
      3. 6.8.3 Comparator Subsystem A (CMPSSA)
      4. 6.8.4 Comparator Subsystem B (CMPSSB)
      5. 6.8.5 Digital-to-Analog Converter (DAC)
      6. 6.8.6 Power Management Unit (PMU)
      7. 6.8.7 Safety Comparators
      8. 6.8.8 Safety System
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 VPP Specifications
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 Package Thermal Characteristics
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Sequencing
        1. 6.11.2.1 Power-On and Reset Sequencing
          1. 6.11.2.1.1 Power Reset Sequence Description
        2. 6.11.2.2 Power-Down Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 System Timing Conditions
        2. 6.11.3.2 Reset Timing
          1. 6.11.3.2.1 PORz Timing Requirements
          2.        207
          3. 6.11.3.2.2 WARMRSTn Switching Characteristics
          4.        209
          5. 6.11.3.2.3 WARMRSTn Timing Requirements
          6.        211
        3. 6.11.3.3 Safety Signal Timing
          1. 6.11.3.3.1 SAFETY_ERRORn Switching Characteristics
          2.        214
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 Crystal Oscillator (XTAL) Parameters
          2. 6.11.4.1.2 External Clock Characteristics
      5. 6.11.5 Peripherals
        1. 6.11.5.1  2-port Gigabit Ethernet MAC (CPSW)
          1. 6.11.5.1.1 CPSW MDIO Timing
            1. 6.11.5.1.1.1 CPSW MDIO Timing Conditions
            2. 6.11.5.1.1.2 CPSW MDIO Timing Requirements
            3. 6.11.5.1.1.3 CPSW MDIO Switching Characteristics
            4.         225
          2. 6.11.5.1.2 CPSW RGMII Timing
            1. 6.11.5.1.2.1 CPSW RGMII Timing Conditions
            2. 6.11.5.1.2.2 CPSW RGMII[x]_RCLK Timing Requirements - RGMII Mode
            3. 6.11.5.1.2.3 CPSW RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements
            4.         230
            5. 6.11.5.1.2.4 CPSW RGMII[x]_TCLK Switching Characteristics - RGMII Mode
            6. 6.11.5.1.2.5 CPSW RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode
            7.         233
          3. 6.11.5.1.3 CPSW RMII Timing
            1. 6.11.5.1.3.1 CPSW RMII Timing Conditions
            2. 6.11.5.1.3.2 CPSW RMII[x]_REFCLK Timing Requirements - RMII Mode
            3.         237
            4. 6.11.5.1.3.3 CPSW RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode
            5.         239
            6. 6.11.5.1.3.4 CPSW RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode
            7.         241
        2. 6.11.5.2  Enhanced Capture (eCAP)
          1. 6.11.5.2.1 ECAP Timing Conditions
          2. 6.11.5.2.2 ECAP Timing Requirements
          3.        245
          4. 6.11.5.2.3 ECAP Switching Characteristics
          5.        247
        3. 6.11.5.3  Enhanced Pulse Width Modulation (ePWM)
          1. 6.11.5.3.1 EPWM Timing Conditions
          2. 6.11.5.3.2 EPWM Timing Requirements
          3.        251
          4. 6.11.5.3.3 EPWM Switching Characteristics
          5.        253
          6. 6.11.5.3.4 EPWM Characteristics
        4. 6.11.5.4  Enhanced Quadrature Encoder Pulse (eQEP)
          1. 6.11.5.4.1 EQEP Timing Conditions
          2. 6.11.5.4.2 EQEP Timing Requirements
          3.        258
          4. 6.11.5.4.3 EQEP Switching Characteristics
        5. 6.11.5.5  Fast Serial Interface (FSI)
          1. 6.11.5.5.1 FSI Timing Conditions
          2. 6.11.5.5.2 FSIRX Timing Requirements
          3.        263
          4. 6.11.5.5.3 FSIRX Switching Characteristics
          5. 6.11.5.5.4 FSITX Switching Characteristics
          6.        266
          7. 6.11.5.5.5 FSITX SPI Signaling Mode Switching Characteristics
          8.        268
        6. 6.11.5.6  General Purpose Input/Output (GPIO)
          1. 6.11.5.6.1 GPIO Timing Conditions
          2. 6.11.5.6.2 GPIO Timing Requirements
          3. 6.11.5.6.3 GPIO Switching Characteristics
        7. 6.11.5.7  Inter-Integrated Circuit (I2C)
          1. 6.11.5.7.1 I2C
        8. 6.11.5.8  Local Interconnect Network (LIN)
          1. 6.11.5.8.1 LIN Timing Conditions
          2. 6.11.5.8.2 LIN Timing Requirements
          3. 6.11.5.8.3 LIN Switching Characteristics
        9. 6.11.5.9  Modular Controller Area Network (MCAN)
          1. 6.11.5.9.1 MCAN Timing Conditions
          2. 6.11.5.9.2 MCAN Switching Characteristics
        10. 6.11.5.10 Serial Peripheral Interface (SPI)
          1. 6.11.5.10.1 SPI Timing Conditions
          2. 6.11.5.10.2 SPI Controller Mode Timing Requirements
          3.        285
          4. 6.11.5.10.3 SPI Controller Mode Switching Characteristics (Clock Phase = 0)
          5.        287
          6. 6.11.5.10.4 SPI Peripheral Mode Timing Requirements
          7.        289
          8. 6.11.5.10.5 SPI Peripheral Mode Switching Characteristics
          9.        291
        11. 6.11.5.11 Multi-Media Card/Secure Digital (MMCSD)
          1. 6.11.5.11.1 MMC Timing Conditions
          2. 6.11.5.11.2 MMC Timing Requirements - SD Card Default Speed Mode
          3.        295
          4. 6.11.5.11.3 MMC Switching Characteristics - SD Card Default Speed Mode
          5.        297
          6. 6.11.5.11.4 MMC Timing Requirements - SD Card High Speed Mode
          7.        299
          8. 6.11.5.11.5 MMC Switching Characteristics - SD Card High Speed Mode
          9.        301
        12. 6.11.5.12 Octal Serial Peripheral Interface (OSPI)
          1. 6.11.5.12.1 OSPI Timing Conditions
          2. 6.11.5.12.2 OSPI PHY Mode
            1. 6.11.5.12.2.1 OSPI0 With PHY Data Training
              1. 6.11.5.12.2.1.1 OSPI DLL Delay Mapping for PHY Data Training
              2. 6.11.5.12.2.1.2 OSPI Timing Requirements - PHY Data Training
              3.          308
              4. 6.11.5.12.2.1.3 OSPI Switching Characteristics - PHY Data Training
              5.          310
            2. 6.11.5.12.2.2 OSPI0 Without Data Training
              1. 6.11.5.12.2.2.1 OSPI0 PHY SDR Timing
                1. 6.11.5.12.2.2.1.1 OSPI DLL Delay Mapping for PHY SDR Timing Modes
                2. 6.11.5.12.2.2.1.2 OSPI Timing Requirements - PHY SDR Mode
                3.           315
                4. 6.11.5.12.2.2.1.3 OSPI Switching Characteristics - PHY SDR Mode
                5.           317
              2. 6.11.5.12.2.2.2 OSPI0 PHY DDR Timing
                1. 6.11.5.12.2.2.2.1 OSPI DLL Delay Mapping for PHY DDR Timing Modes
                2. 6.11.5.12.2.2.2.2 OSPI Timing Requirements - PHY DDR Mode
                3.           321
                4. 6.11.5.12.2.2.2.3 OSPI Switching Characteristics - PHY DDR Mode
                5.           323
          3. 6.11.5.12.3 OSPI Tap Mode
            1. 6.11.5.12.3.1 OSPI0 Tap SDR Timing
              1. 6.11.5.12.3.1.1 OSPI Timing Requirements - Tap SDR Mode
              2.          327
              3. 6.11.5.12.3.1.2 OSPI Switching Characteristics - Tap SDR Mode
              4.          329
            2. 6.11.5.12.3.2 OSPI0 Tap DDR Timing
              1. 6.11.5.12.3.2.1 OSPI Timing Requirements - Tap DDR Mode
              2.          332
              3. 6.11.5.12.3.2.2 OSPI Switching Characteristics - Tap DDR Mode
              4.          334
        13. 6.11.5.13 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
          1. 6.11.5.13.1 PRU-ICSS Programmable Real-Time Unit (PRU)
            1. 6.11.5.13.1.1 PRU-ICSS PRU Timing Conditions
            2. 6.11.5.13.1.2 PRU-ICSS PRU Switching Characteristics - Direct Output Mode
            3.         339
            4. 6.11.5.13.1.3 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            5.         341
            6. 6.11.5.13.1.4 PRU-ICSS PRU Timing Requirements - Shift In Mode
            7.         343
            8. 6.11.5.13.1.5 PRU-ICSS PRU Switching Characteristics - Shift Out Mode
            9.         345
          2. 6.11.5.13.2 PRU-ICSS PRU Sigma Delta and Peripheral Interface
            1. 6.11.5.13.2.1 PRU-ICSS PRU Sigma Delta and Peripheral Interface Timing Conditions
            2. 6.11.5.13.2.2 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
            3.         349
            4. 6.11.5.13.2.3 PRU-ICSS PRU Timing Requirements - Peripheral Interface Mode
            5.         351
            6. 6.11.5.13.2.4 PRU-ICSS PRU Switching Characteristics - Peripheral Interface Mode
            7.         353
          3. 6.11.5.13.3 PRU-ICSS Pulse Width Modulation (PWM)
            1. 6.11.5.13.3.1 PRU-ICSS PWM Timing Conditions
            2. 6.11.5.13.3.2 PRU-ICSS PWM Switching Characteristics
            3.         357
          4. 6.11.5.13.4 PRU-ICSS Industrial Ethernet Peripheral (IEP)
            1. 6.11.5.13.4.1 PRU-ICSS IEP Timing Conditions
            2. 6.11.5.13.4.2 PRU-ICSS IEP Timing Requirements - Input Validated with SYNCx
            3.         361
            4. 6.11.5.13.4.3 PRU-ICSS IEP Timing Requirements - Digital IOs
            5.         363
            6. 6.11.5.13.4.4 PRU-ICSS IEP Timing Requirements - LATCHx_IN
            7.         365
          5. 6.11.5.13.5 PRU-ICSS Universal Asynchronous Receiver Transmitter (UART)
            1. 6.11.5.13.5.1 PRU-ICSS UART Timing Conditions
            2. 6.11.5.13.5.2 PRU-ICSS UART Timing Requirements
            3. 6.11.5.13.5.3 PRU-ICSS UART Switching Characteristics
            4.         370
          6. 6.11.5.13.6 PRU-ICSS Enhanced Capture Peripheral (ECAP)
            1. 6.11.5.13.6.1 PRU-ICSS ECAP Timing Conditions
            2. 6.11.5.13.6.2 PRU-ICSS ECAP Timing Requirements
            3.         374
            4. 6.11.5.13.6.3 PRU-ICSS ECAP Switching Characteristics
            5.         376
          7. 6.11.5.13.7 PRU-ICSS MDIO and MII
            1. 6.11.5.13.7.1 PRU-ICSS MDIO Timing
              1. 6.11.5.13.7.1.1 PRU-ICSS MDIO Timing Conditions
              2. 6.11.5.13.7.1.2 PRU-ICSS MDIO Timing Requirements
              3. 6.11.5.13.7.1.3 PRU-ICSS MDIO Switching Characteristics
              4.          382
            2. 6.11.5.13.7.2 PRU-ICSS MII Timing
              1. 6.11.5.13.7.2.1 PRU-ICSS MII Timing Conditions
              2. 6.11.5.13.7.2.2 PRU-ICSS MII Timing Requirements - MII[x]_RX_CLK
              3.          386
              4. 6.11.5.13.7.2.3 PRU-ICSS MII Timing Requirements - MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER
              5.          388
              6. 6.11.5.13.7.2.4 PRU-ICSS MII Switching Characteristics - MII[x]_TX_CLK
              7.          390
              8. 6.11.5.13.7.2.5 PRU-ICSS MII Switching Characteristics - MII[x]_TXD[3:0] and MII[x]_TXEN
              9.          392
        14. 6.11.5.14 Sigma Delta Filter Module (SDFM)
          1. 6.11.5.14.1 SDFM Timing Conditions
          2. 6.11.5.14.2 SDFM Switching Characteristics
        15. 6.11.5.15 Universal Asynchronous Receiver/Transmitter (UART)
          1. 6.11.5.15.1 UART Timing Conditions
          2. 6.11.5.15.2 UART Timing Requirements
          3. 6.11.5.15.3 UART Switching Characteristics
          4.        400
      6. 6.11.6 Emulation and Debug
        1. 6.11.6.1 JTAG
          1. 6.11.6.1.1 JTAG Timing Conditions
          2. 6.11.6.1.2 JTAG Timing Requirements
          3. 6.11.6.1.3 JTAG Switching Characteristics
          4.        406
        2. 6.11.6.2 Trace
          1. 6.11.6.2.1 Debug Trace Timing Conditions
          2. 6.11.6.2.2 Debug Trace Switching Characteristics
          3.        410
    12. 6.12 Decoupling Capacitor Requirements
      1. 6.12.1 Decoupling Capacitor Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 External Oscillator
      2. 8.1.2 JTAG, EMU, and TRACE
      3. 8.1.3 OSPI Connections for Flash-in-Package (ZCZ_F)
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.11.5.12 Octal Serial Peripheral Interface (OSPI)

OSPI0 offers two data capture modes, PHY mode and Tap mode.

PHY mode uses an internal reference clock to transmit and receive data via a DLL based PHY, where each reference clock cycle produces a single cycle of OSPI0_CLK for Single Data Rate (SDR) transfers or a half cycle of OSPI0_CLK for Double Data Rate (DDR) transfers. PHY mode supports four clocking topologies for the receive data capture clock. Internal PHY Loopback - uses the internal reference clock as the PHY receive data capture clock. Internal Pad Loopback - uses OSPI0_LBCLKO looped back into the PHY from the OSPI0_LBCLKO pin as the PHY receive data capture clock. External Board Loopback - uses OSPI0_LBCLKO looped back into the PHY from the OSPI0_DQS pin as the PHY receive data capture clock. DQS - uses the DQS output from the attached device as the PHY receive data capture clock. SDR transfers are not supported when using the Internal Pad Loopback and DQS clocking topologies. DDR transfers are not supported when using the Internal PHY Loopback or Internal Pad Loopback clocking topologies.

Tap mode uses an internal reference clock with selectable taps to adjusted data transmit and receive capture delays relative to OSPI0_CLK, which is a divide by 4 of the internal reference clock for SDR transfers or a divide by 8 of the internal reference clock for DDR transfers. Tap mode only supports one clocking topology for the receive data capture clock. No Loopback - uses the internal reference clock as the Tap receive data capture clock. This clocking topology supports a maximum internal reference clock rate of 200MHz, which produces an OSPI0_CLK rate up to 50MHz for SDR mode or 25MHz for DDR mode.

For more details about features and additional description information on the device Octal Serial Peripheral Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

OSPI PHY Mode defines timing requirements and switching characteristics associated with PHY mode and OSPI Tap Mode defines timing requirements and switching characteristics associated with Tap mode.

OSPI Timing Conditions presents timing conditions for OSPI0.

For more information, see Octal Serial Peripheral Interface (OSPI) section in the device TRM.