SPRSPB0
December 2024
AM2754-Q1
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
3.1
Functional Block Diagram
4
Device Comparison
4.1
Related Products
5
Terminal Configuration and Functions
5.1
Pin Diagram
5.1.1
ANJ Pin Diagram
5.2
Pin Attributes
12
13
5.3
Signal Descriptions
15
5.3.1
ADC
17
5.3.2
Audio Clock References
19
5.3.3
CPSW
21
22
23
24
25
5.3.4
CPTS
27
5.3.5
ECAP
29
30
31
32
33
34
5.3.6
Emulation and Debug
36
37
5.3.7
EPWM
39
40
41
42
5.3.8
GPIO
44
45
46
5.3.9
HYPERBUS
48
5.3.10
I2C
50
51
52
53
54
55
56
57
5.3.11
MCAN
59
60
61
62
63
5.3.12
MCASP
65
66
67
68
69
5.3.13
MLB
71
5.3.14
MMC
73
5.3.15
OSPI
75
76
5.3.16
Power Supply
78
5.3.17
Reserved
80
5.3.18
System and Miscellaneous
82
83
84
85
5.3.19
SPI
87
88
89
90
91
5.3.20
TIMER
93
94
5.3.21
UART
96
97
98
99
100
101
102
103
5.3.22
USB
105
Pin Connectivity Requirements
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Electrostatic Discharge (ESD) for AEC - Q100 devices
6.3
Electrostatic Discharge (ESD) for non AEC - Q100 devices
6.4
Power-On Hours (POH) Summary
6.5
Automotive Temperature Profile
6.6
Recommended Operating Conditions
6.7
Operating Performance Points
6.8
Electrical Characteristics
6.8.1
I2C Open-Drain and Fail-Safe (I2C OD FS) Electrical Characteristics
6.8.2
Fail-Safe Reset (FS RESET) Electrical Characteristics
6.8.3
High-Frequency Oscillators (MCU_OSC0 and OSC1) Electrical Characteristics
6.8.4
Low-Frequency Oscillator (WKUP_LFOSC0) Electrical Characteristics
6.8.5
SDIO Electrical Characteristics
6.8.6
Analog-to-Digital Converter (ADC)
6.8.7
LVCMOS Electrical Characteristics
6.8.8
USB2PHY Electrical Characteristics
6.9
VPP Specifications for One-Time Programmable (OTP) eFuses
6.9.1
VPP Specifications
6.9.2
Hardware Requirements
6.9.3
Programming Sequence
6.9.4
Impact to Your Hardware Warranty
6.10
Thermal Resistance Characteristics
6.10.1
Package Thermal Characteristics
6.11
Timing and Switching Characteristics
6.11.1
Timing Parameters and Information
6.11.2
Power Supply Requirements
6.11.2.1
Power Supply Slew Rate Requirement
6.11.2.2
Power Supply Sequencing
6.11.2.2.1
Power-Up Sequencing without IO Retention
6.11.2.2.2
Power-Up Sequencing with IO Retention
6.11.2.2.3
Power-Up Sequencing - IO Retention Wakeup
6.11.2.2.4
Power-Down Sequencing
6.11.3
System Timing
6.11.3.1
Reset Timing
Reset Timing Conditions
MCU_PORz Timing Requirements
144
RESETSTATz Switching Characteristics
MCU_RESETz Timing Requirements
RESETSTATz Switching Characteristics
EMUx Timing Requirements
149
BOOTMODE Timing Requirements
6.11.3.2
Error Signal Timing
Error Signal Timing Conditions
MCU_ERRORn Switching Characteristics
6.11.3.2.1
154
6.11.3.3
Clock Timing
Clock Timing Conditions
Clock Timing Requirements
6.11.3.3.1
158
Clock Switching Characteristics
6.11.3.3.2
160
6.11.4
Clock Specifications
6.11.4.1
Input Clocks / Oscillators
6.11.4.1.1
MCU_OSC0 and OSC1 Internal Oscillator Clock Source
6.11.4.1.1.1
HFOSC (MCU_OSC0 and OSC1) Crystal Circuit Requirements
6.11.4.1.1.2
HFOSC (MCU_OSC0 and OSC1) Switching Characteristics - Crystal Mode
6.11.4.1.1.3
Load Capacitance
6.11.4.1.1.4
Shunt Capacitance
6.11.4.1.2
MCU_OSC0 and OSC1 LVCMOS Digital Clock Source
6.11.4.1.3
WKUP_LFOSC0 Internal Oscillator Clock Source
6.11.4.1.3.1
LFOSC (WKUP_LFOSC0) Crystal Circuit Requirements
6.11.4.1.3.2
LFOSC (WKUP_LFOSC0) Switching Characteristics - Crystal Mode
6.11.4.1.4
WKUP_LFOSC0 LVCMOS Digital Clock Source
6.11.4.1.5
WKUP_LFOSC0 Not Used
6.11.4.2
Recommended System Precautions for Clock and Control Signal Transitions
6.11.5
Peripherals
6.11.5.1
ATL
ATL Timing Conditions
ATL_AWS[x] Timing Requirements
ATL_BWS[x] Timing Requirements
ATL_PCLK Timing Requirements
ATCLK[x] Switching Characteristics
6.11.5.2
CPSW3G
6.11.5.2.1
CPSW3G MDIO Timing
CPSW3G MDIO Timing Conditions
CPSW3G MDIO Timing Requirements
CPSW3G MDIO Switching Characteristics
187
6.11.5.2.2
CPSW3G RMII Timing
CPSW3G RMII Timing Conditions
CPSW3G RMII[x]_REFCLK Timing Requirements - RMII Mode
191
CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode
193
CPSW3G RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode
195
6.11.5.2.3
CPSW3G RGMII Timing
CPSW3G RGMII Timing Conditions
CPSW3G RGMII[x]_RCLK Timing Requirements - RGMII Mode
CPSW3G RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements - RGMII Mode
200
CPSW3G RGMII[x]_TCLK Switching Characteristics - RGMII Mode
CPSW3G RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode
203
6.11.5.3
ECAP
ECAP Timing Conditions
ECAP Timing Requirements
207
ECAP Switching Characteristics
209
6.11.5.4
Emulation and Debug
6.11.5.4.1
Trace
Trace Timing Conditions
Trace Switching Characteristics
214
6.11.5.4.2
JTAG
JTAG Timing Conditions
JTAG Timing Requirements
JTAG Switching Characteristics
219
6.11.5.5
EPWM
EPWM Timing Conditions
EPWM Timing Requirements
223
EPWM Switching Characteristics
225
6.11.5.6
GPIO
GPIO Timing Conditions
GPIO Timing Requirements
GPIO Switching Characteristics
6.11.5.7
HyperBus
HyperBus Timing Conditions
HyperBus Timing Requirements
HyperBus 166MHz Switching Characteristics
HyperBus 100MHz Switching Characteristics
6.11.5.8
I2C
6.11.5.9
MCAN
MCAN Timing Conditions
MCAN Switching Characteristics
6.11.5.10
MCASP
MCASP Timing Conditions
MCASP Timing Requirements
242
MCASP Switching Characteristics
244
6.11.5.11
MCSPI
MCSPI Timing Conditions
MCSPI Timing Requirements - Controller Mode
248
MCSPI Switching Characteristics - Controller Mode
250
MCSPI Timing Requirements - Peripheral Mode
252
MCSPI Switching Characteristics - Peripheral Mode
254
6.11.5.12
MLB
MLB Timing Conditions
MLB Timing Requirements for MLBCLK - 3-pin
MLB Timing Requirements for Receive Data - 3-pin
MLB Switching Characteristics - 3-Pin
MLB Timing Requirements for MLBCLK - 6-pin
MLB Timing Requirements for Receive Data - 6-pin
MLB Switching Characteristics - 6-Pin
6.11.5.13
MMCSD
6.11.5.13.1
MMC0 - eMMC/SDIO Interface
MMC Timing Conditions
MMC Timing Requirements - 3.3V Legacy SDR Mode
267
MMC Switching Characteristics - 3.3V Legacy SDR Mode
269
MMC Timing Requirements - 3.3V High Speed SDR Mode
271
MMC Switching Characteristics - 3.3V High Speed SDR Mode
273
MMC Timing Requirements - 1.8V Legacy SDR, UHS-I SDR12 Mode
275
MMC Switching Characteristics - 1.8V Legacy SDR, UHS-I SDR12 Mode
277
MMC Timing Requirements - 1.8V High Speed SDR, UHS-I SDR25 Mode
279
MMC Switching Characteristics - 1.8V High Speed SDR, UHS-I SDR25 Mode
281
MMC Switching Characteristics - UHS-I SDR50 Mode
283
MMC Switching Characteristics - UHS-I DDR50 Mode
285
MMC Switching Characteristics - HS200 Mode
287
6.11.5.14
OSPI
OSPI Timing Conditions
6.11.5.14.1
OSPI0 PHY Mode
6.11.5.14.1.1
OSPI0 With PHY Data Training
OSPI DLL Delay Mapping for PHY Data Training
OSPI Timing Requirements - PHY Data Training
294
OSPI Switching Characteristics - PHY Data Training
296
6.11.5.14.1.2
OSPI0 Without Data Training
6.11.5.14.1.2.1
OSPI0 PHY SDR Timing
OSPI DLL Delay Mapping for PHY SDR Timing Modes
OSPI Timing Requirements - PHY SDR Mode
301
OSPI Switching Characteristics - PHY SDR Mode
303
6.11.5.14.1.2.2
OSPI0 PHY DDR Timing
OSPI DLL Delay Mapping for PHY DDR Timing Modes
OSPI Timing Requirements - PHY DDR Mode
307
OSPI Switching Characteristics - PHY DDR Mode
309
6.11.5.14.2
OSPI0 Tap Mode
6.11.5.14.2.1
OSPI0 Tap SDR Timing
OSPI Timing Requirements - Tap SDR Mode
313
OSPI Switching Characteristics - Tap SDR Mode
315
6.11.5.14.2.2
OSPI0 Tap DDR Timing
OSPI Timing Requirements - Tap DDR Mode
318
OSPI Switching Characteristics - Tap DDR Mode
320
6.11.5.15
Timers
Timer Timing Conditions
Timer Timing Requirements
Timer Switching Characteristics
325
6.11.5.16
UART
UART Timing Conditions
UART Timing Requirements
UART Switching Characteristics
330
6.11.5.17
USB
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Processor Subsystems
7.3.1
Arm Cortex-R5F Subsystem
7.3.2
Device/Power Manager
8
Applications, Implementation, and Layout
8.1
Device Connection and Layout Fundamentals
8.1.1
Power Supply
8.1.2
External Oscillator
8.1.3
JTAG, EMU, and TRACE
8.1.4
Unused Pins
8.2
Peripheral- and Interface-Specific Design Information
8.2.1
OSPI/QSPI/SPI Board Design and Layout Guidelines
8.2.1.1
No Loopback, Internal PHY Loopback, and Internal Pad Loopback
8.2.1.2
External Board Loopback
8.2.1.3
DQS (only available in Octal SPI devices)
8.2.2
High Speed Differential Signal Routing Guidance
8.2.3
Thermal Solution Guidance
8.3
Clock Routing Guidelines
8.3.1
Oscillator Routing
9
Device and Documentation Support
9.1
Device Nomenclature
9.1.1
Standard Package Symbolization
9.1.2
Device Naming Convention
9.2
Tools and Software
9.3
Documentation Support
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
11.1
Packaging Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
ANJ|361
サーマルパッド・メカニカル・データ
発注情報
sprspb0_oa
Table 5-27 I2C1 Signal Descriptions
SIGNAL NAME [
1
]
PIN TYPE [
2
]
DESCRIPTION [
3
]
ANJ PIN [
4
]
I2C1_SCL
IOD
I2C Clock
N2
I2C1_SDA
IOD
I2C Data
M2