SPRSPB0 Data sheet

SPRSPB0 December 2024 AM2754-Q1

ADVANCE INFORMATION

1
1 Features
2 Applications
3 Description
1. 3.1 Functional Block Diagram
4 Device Comparison
1. 4.1 Related Products
5 Terminal Configuration and Functions
1. 5.1 Pin Diagram
  1. 5.1.1 ANJ Pin Diagram
2. 5.2 Pin Attributes
  1. 12
  2. 13
3. 5.3 Signal Descriptions
  1. 15
  2. 5.3.1 ADC
    1. 17
  3. 5.3.2 Audio Clock References
    1. 19
  4. 5.3.3 CPSW
    1. 21
    2. 22
    3. 23
    4. 24
    5. 25
  5. 5.3.4 CPTS
    1. 27
  6. 5.3.5 ECAP
    1. 29
    2. 30
    3. 31
    4. 32
    5. 33
    6. 34
  7. 5.3.6 Emulation and Debug
    1. 36
    2. 37
  8. 5.3.7 EPWM
    1. 39
    2. 40
    3. 41
    4. 42
  9. 5.3.8 GPIO
    1. 44
    2. 45
    3. 46
  10. 5.3.9 HYPERBUS
    1. 48
  11. 5.3.10 I2C
    1. 50
    2. 51
    3. 52
    4. 53
    5. 54
    6. 55
    7. 56
    8. 57
  12. 5.3.11 MCAN
    1. 59
    2. 60
    3. 61
    4. 62
    5. 63
  13. 5.3.12 MCASP
    1. 65
    2. 66
    3. 67
    4. 68
    5. 69
  14. 5.3.13 MLB
    1. 71
  15. 5.3.14 MMC
    1. 73
  16. 5.3.15 OSPI
    1. 75
    2. 76
  17. 5.3.16 Power Supply
    1. 78
  18. 5.3.17 Reserved
    1. 80
  19. 5.3.18 System and Miscellaneous
    1. 82
    2. 83
    3. 84
    4. 85
  20. 5.3.19 SPI
    1. 87
    2. 88
    3. 89
    4. 90
    5. 91
  21. 5.3.20 TIMER
    1. 93
    2. 94
  22. 5.3.21 UART
    1. 96
    2. 97
    3. 98
    4. 99
    5. 100
    6. 101
    7. 102
    8. 103
  23. 5.3.22 USB
    1. 105
4. Pin Connectivity Requirements
6 Specifications
1. 6.1 Absolute Maximum Ratings
2. 6.2 Electrostatic Discharge (ESD) for AEC - Q100 devices
3. 6.3 Electrostatic Discharge (ESD) for non AEC - Q100 devices
4. 6.4 Power-On Hours (POH) Summary
5. 6.5 Automotive Temperature Profile
6. 6.6 Recommended Operating Conditions
7. 6.7 Operating Performance Points
8. 6.8 Electrical Characteristics
9. 6.9 VPP Specifications for One-Time Programmable (OTP) eFuses
10. 6.10 Thermal Resistance Characteristics
  1. 6.10.1 Package Thermal Characteristics
11. 6.11 Timing and Switching Characteristics
  1. 6.11.1 Timing Parameters and Information
  2. 6.11.2 Power Supply Requirements
    1. 6.11.2.1 Power Supply Slew Rate Requirement
    2. 6.11.2.2 Power Supply Sequencing
  3. 6.11.3 System Timing
    1. 6.11.3.1 Reset Timing
      1. Reset Timing Conditions
      2. MCU_PORz Timing Requirements
      3. 144
      4. RESETSTATz Switching Characteristics
      5. MCU_RESETz Timing Requirements
      6. RESETSTATz Switching Characteristics
      7. EMUx Timing Requirements
      8. 149
      9. BOOTMODE Timing Requirements
    2. 6.11.3.2 Error Signal Timing
    3. 6.11.3.3 Clock Timing
      1. Clock Timing Conditions
      2. Clock Timing Requirements
      3. 6.11.3.3.1 158
      4. Clock Switching Characteristics
      5. 6.11.3.3.2 160
  4. 6.11.4 Clock Specifications
    1. 6.11.4.1 Input Clocks / Oscillators
    2. 6.11.4.2 Recommended System Precautions for Clock and Control Signal Transitions
  5. 6.11.5 Peripherals
    1. 6.11.5.1 ATL
      1. ATL Timing Conditions
      2. ATL_AWS[x] Timing Requirements
      3. ATL_BWS[x] Timing Requirements
      4. ATL_PCLK Timing Requirements
      5. ATCLK[x] Switching Characteristics
    2. 6.11.5.2 CPSW3G
      1. 6.11.5.2.1 CPSW3G MDIO Timing
        
                CPSW3G MDIO Timing Conditions
        
                CPSW3G MDIO Timing Requirements
        
                CPSW3G MDIO Switching Characteristics
        
                187
      2. 6.11.5.2.2 CPSW3G RMII Timing
        
                CPSW3G RMII Timing Conditions
        
                CPSW3G RMII[x]_REFCLK Timing Requirements - RMII Mode
        
                191
        
                CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode
        
                193
        
                CPSW3G RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode
        
                195
      3. 6.11.5.2.3 CPSW3G RGMII Timing
        
                CPSW3G RGMII Timing Conditions
        
                CPSW3G RGMII[x]_RCLK Timing Requirements - RGMII Mode
        
                CPSW3G RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements - RGMII Mode
        
                200
        
                CPSW3G RGMII[x]_TCLK Switching Characteristics - RGMII Mode
        
                CPSW3G RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode
        
                203
    3. 6.11.5.3 ECAP
      1. ECAP Timing Conditions
      2. ECAP Timing Requirements
      3. 207
      4. ECAP Switching Characteristics
      5. 209
    4. 6.11.5.4 Emulation and Debug
      1. 6.11.5.4.1 Trace
        
                Trace Timing Conditions
        
                Trace Switching Characteristics
        
                214
      2. 6.11.5.4.2 JTAG
        
                JTAG Timing Conditions
        
                JTAG Timing Requirements
        
                JTAG Switching Characteristics
        
                219
    5. 6.11.5.5 EPWM
      1. EPWM Timing Conditions
      2. EPWM Timing Requirements
      3. 223
      4. EPWM Switching Characteristics
      5. 225
    6. 6.11.5.6 GPIO
      1. GPIO Timing Conditions
      2. GPIO Timing Requirements
      3. GPIO Switching Characteristics
    7. 6.11.5.7 HyperBus
      1. HyperBus Timing Conditions
      2. HyperBus Timing Requirements
      3. HyperBus 166MHz Switching Characteristics
      4. HyperBus 100MHz Switching Characteristics
    8. 6.11.5.8 I2C
    9. 6.11.5.9 MCAN
      1. MCAN Timing Conditions
      2. MCAN Switching Characteristics
    10. 6.11.5.10 MCASP
      1. MCASP Timing Conditions
      2. MCASP Timing Requirements
      3. 242
      4. MCASP Switching Characteristics
      5. 244
    11. 6.11.5.11 MCSPI
      1. MCSPI Timing Conditions
      2. MCSPI Timing Requirements - Controller Mode
      3. 248
      4. MCSPI Switching Characteristics - Controller Mode
      5. 250
      6. MCSPI Timing Requirements - Peripheral Mode
      7. 252
      8. MCSPI Switching Characteristics - Peripheral Mode
      9. 254
    12. 6.11.5.12 MLB
      1. MLB Timing Conditions
      2. MLB Timing Requirements for MLBCLK - 3-pin
      3. MLB Timing Requirements for Receive Data - 3-pin
      4. MLB Switching Characteristics - 3-Pin
      5. MLB Timing Requirements for MLBCLK - 6-pin
      6. MLB Timing Requirements for Receive Data - 6-pin
      7. MLB Switching Characteristics - 6-Pin
    13. 6.11.5.13 MMCSD
      1. 6.11.5.13.1 MMC0 - eMMC/SDIO Interface
        
                MMC Timing Conditions
        
                MMC Timing Requirements - 3.3V Legacy SDR Mode
        
                267
        
                MMC Switching Characteristics - 3.3V Legacy SDR Mode
        
                269
        
                MMC Timing Requirements - 3.3V High Speed SDR Mode
        
                271
        
                MMC Switching Characteristics - 3.3V High Speed SDR Mode
        
                273
        
                MMC Timing Requirements - 1.8V Legacy SDR, UHS-I SDR12 Mode
        
                275
        
                MMC Switching Characteristics - 1.8V Legacy SDR, UHS-I SDR12 Mode
        
                277
        
                MMC Timing Requirements - 1.8V High Speed SDR, UHS-I SDR25 Mode
        
                279
        
                MMC Switching Characteristics - 1.8V High Speed SDR, UHS-I SDR25 Mode
        
                281
        
                MMC Switching Characteristics - UHS-I SDR50 Mode
        
                283
        
                MMC Switching Characteristics - UHS-I DDR50 Mode
        
                285
        
                MMC Switching Characteristics - HS200 Mode
        
                287
    14. 6.11.5.14 OSPI
      1. OSPI Timing Conditions
      2. 6.11.5.14.1 OSPI0 PHY Mode
        
        6.11.5.14.1.1 OSPI0 With PHY Data Training
        
                 OSPI DLL Delay Mapping for PHY Data Training
        
                 OSPI Timing Requirements - PHY Data Training
        
                 294
        
                 OSPI Switching Characteristics - PHY Data Training
        
                 296
        
        6.11.5.14.1.2 OSPI0 Without Data Training
        
        6.11.5.14.1.2.1 OSPI0 PHY SDR Timing
        
                  OSPI DLL Delay Mapping for PHY SDR Timing Modes
        
                  OSPI Timing Requirements - PHY SDR Mode
        
                  301
        
                  OSPI Switching Characteristics - PHY SDR Mode
        
                  303
        
        6.11.5.14.1.2.2 OSPI0 PHY DDR Timing
        
                  OSPI DLL Delay Mapping for PHY DDR Timing Modes
        
                  OSPI Timing Requirements - PHY DDR Mode
        
                  307
        
                  OSPI Switching Characteristics - PHY DDR Mode
        
                  309
      3. 6.11.5.14.2 OSPI0 Tap Mode
        
        6.11.5.14.2.1 OSPI0 Tap SDR Timing
        
                 OSPI Timing Requirements - Tap SDR Mode
        
                 313
        
                 OSPI Switching Characteristics - Tap SDR Mode
        
                 315
        
        6.11.5.14.2.2 OSPI0 Tap DDR Timing
        
                 OSPI Timing Requirements - Tap DDR Mode
        
                 318
        
                 OSPI Switching Characteristics - Tap DDR Mode
        
                 320
    15. 6.11.5.15 Timers
      1. Timer Timing Conditions
      2. Timer Timing Requirements
      3. Timer Switching Characteristics
      4. 325
    16. 6.11.5.16 UART
      1. UART Timing Conditions
      2. UART Timing Requirements
      3. UART Switching Characteristics
      4. 330
    17. 6.11.5.17 USB
7 Detailed Description
8 Applications, Implementation, and Layout
9 Device and Documentation Support
10Revision History
11Mechanical, Packaging, and Orderable Information
1. 11.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

ANJ|361

サーマルパッド・メカニカル・データ

発注情報

sprspb0_oa

MMC Timing Conditions

PARAMETER		MODE	MIN	MAX	UNIT
INPUT CONDITIONS
SR_I	Input Slew Rate	Legacy SDR 3.3 V, Default Speed High Speed SDR 3.3 V Default Speed andHigh Speed	0.69	2.06	V/ns
		Legacy SDR 1.8V UHS-I SDR12	0.14	1.44	V/ns
		High Speed SDR 1.8V UHS-I SDR25	0.3	1.34	V/ns
		UHS-I DDR50	1	2	V/ns
OUTPUT CONDITIONS
C_L	Output Load Capacitance	HS200, UHS-I SDR104	1	10	pF
C_L	Output Load Capacitance	All other modes	1	12	pF