JAJSDZ0J October   2011  – April 2016 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
      1. 4.1.1 ZCE Package Pin Maps (Top View)
      2. 4.1.2 ZCZ Package Pin Maps (Top View)
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 External Memory Interfaces
      2. 4.3.2 General-Purpose IOs
      3. 4.3.3 Miscellaneous
        1. 4.3.3.1 eCAP
        2. 4.3.3.2 eHRPWM
        3. 4.3.3.3 eQEP
        4. 4.3.3.4 Timer
      4. 4.3.4 PRU-ICSS
        1. 4.3.4.1 PRU0
        2. 4.3.4.2 PRU1
      5. 4.3.5 Removable Media Interfaces
      6. 4.3.6 Serial Communication Interfaces
        1. 4.3.6.1 CAN
        2. 4.3.6.2 GEMAC_CPSW
        3. 4.3.6.3 I2C
        4. 4.3.6.4 McASP
        5. 4.3.6.5 SPI
        6. 4.3.6.6 UART
        7. 4.3.6.7 USB
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points (OPPs)
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  Thermal Resistance Characteristics for ZCE and ZCZ Packages
    9. 5.9  External Capacitors
      1. 5.9.1 Voltage Decoupling Capacitors
        1. 5.9.1.1 Core Voltage Decoupling Capacitors
        2. 5.9.1.2 I/O and Analog Voltage Decoupling Capacitors
      2. 5.9.2 Output Capacitors
    10. 5.10 Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
  6. 6Power and Clocking
    1. 6.1 Power Supplies
      1. 6.1.1 Power Supply Slew Rate Requirement
      2. 6.1.2 Power-Down Sequencing
      3. 6.1.3 VDD_MPU_MON Connections
      4. 6.1.4 Digital Phase-Locked Loop Power Supply Requirements
    2. 6.2 Clock Specifications
      1. 6.2.1 Input Clock Specifications
      2. 6.2.2 Input Clock Requirements
        1. 6.2.2.1 OSC0 Internal Oscillator Clock Source
        2. 6.2.2.2 OSC0 LVCMOS Digital Clock Source
        3. 6.2.2.3 OSC1 Internal Oscillator Clock Source
        4. 6.2.2.4 OSC1 LVCMOS Digital Clock Source
        5. 6.2.2.5 OSC1 Not Used
      3. 6.2.3 Output Clock Specifications
      4. 6.2.4 Output Clock Characteristics
        1. 6.2.4.1 CLKOUT1
        2. 6.2.4.2 CLKOUT2
  7. 7Peripheral Information and Timings
    1. 7.1  Parameter Information
      1. 7.1.1 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  OPP50 Support
    4. 7.4  Controller Area Network (CAN)
      1. 7.4.1 DCAN Electrical Data and Timing
    5. 7.5  DMTimer
      1. 7.5.1 DMTimer Electrical Data and Timing
    6. 7.6  Ethernet Media Access Controller (EMAC) and Switch
      1. 7.6.1 EMAC and Switch Electrical Data and Timing
        1. 7.6.1.1 EMAC/Switch MDIO Electrical Data and Timing
        2. 7.6.1.2 EMAC and Switch MII Electrical Data and Timing
        3. 7.6.1.3 EMAC and Switch RMII Electrical Data and Timing
        4. 7.6.1.4 EMAC and Switch RGMII Electrical Data and Timing
    7. 7.7  External Memory Interfaces
      1. 7.7.1 General-Purpose Memory Controller (GPMC)
        1. 7.7.1.1 GPMC and NOR Flash—Synchronous Mode
        2. 7.7.1.2 GPMC and NOR Flash—Asynchronous Mode
        3. 7.7.1.3 GPMC and NAND Flash—Asynchronous Mode
      2. 7.7.2 mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
        1. 7.7.2.1 mDDR (LPDDR) Routing Guidelines
          1. 7.7.2.1.1 Board Designs
          2. 7.7.2.1.2 LPDDR Interface
            1. 7.7.2.1.2.1 LPDDR Interface Schematic
            2. 7.7.2.1.2.2 Compatible JEDEC LPDDR Devices
            3. 7.7.2.1.2.3 PCB Stackup
            4. 7.7.2.1.2.4 Placement
            5. 7.7.2.1.2.5 LPDDR Keepout Region
            6. 7.7.2.1.2.6 Bulk Bypass Capacitors
            7. 7.7.2.1.2.7 High-Speed Bypass Capacitors
            8. 7.7.2.1.2.8 Net Classes
            9. 7.7.2.1.2.9 LPDDR Signal Termination
          3. 7.7.2.1.3 LPDDR CK and ADDR_CTRL Routing
        2. 7.7.2.2 DDR2 Routing Guidelines
          1. 7.7.2.2.1 Board Designs
          2. 7.7.2.2.2 DDR2 Interface
            1. 7.7.2.2.2.1  DDR2 Interface Schematic
            2. 7.7.2.2.2.2  Compatible JEDEC DDR2 Devices
            3. 7.7.2.2.2.3  PCB Stackup
            4. 7.7.2.2.2.4  Placement
            5. 7.7.2.2.2.5  DDR2 Keepout Region
            6. 7.7.2.2.2.6  Bulk Bypass Capacitors
            7. 7.7.2.2.2.7  High-Speed (HS) Bypass Capacitors
            8. 7.7.2.2.2.8  Net Classes
            9. 7.7.2.2.2.9  DDR2 Signal Termination
            10. 7.7.2.2.2.10 DDR_VREF Routing
          3. 7.7.2.2.3 DDR2 CK and ADDR_CTRL Routing
        3. 7.7.2.3 DDR3 and DDR3L Routing Guidelines
          1. 7.7.2.3.1 Board Designs
            1. 7.7.2.3.1.1 DDR3 versus DDR2
          2. 7.7.2.3.2 DDR3 Device Combinations
          3. 7.7.2.3.3 DDR3 Interface
            1. 7.7.2.3.3.1  DDR3 Interface Schematic
            2. 7.7.2.3.3.2  Compatible JEDEC DDR3 Devices
            3. 7.7.2.3.3.3  PCB Stackup
            4. 7.7.2.3.3.4  Placement
            5. 7.7.2.3.3.5  DDR3 Keepout Region
            6. 7.7.2.3.3.6  Bulk Bypass Capacitors
            7. 7.7.2.3.3.7  High-Speed Bypass Capacitors
              1. 7.7.2.3.3.7.1 Return Current Bypass Capacitors
            8. 7.7.2.3.3.8  Net Classes
            9. 7.7.2.3.3.9  DDR3 Signal Termination
            10. 7.7.2.3.3.10 DDR_VREF Routing
            11. 7.7.2.3.3.11 VTT
          4. 7.7.2.3.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
            1. 7.7.2.3.4.1 Two DDR3 Devices
              1. 7.7.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
              2. 7.7.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
            2. 7.7.2.3.4.2 One DDR3 Device
              1. 7.7.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
              2. 7.7.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device
          5. 7.7.2.3.5 Data Topologies and Routing Definition
            1. 7.7.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
            2. 7.7.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
          6. 7.7.2.3.6 Routing Specification
            1. 7.7.2.3.6.1 CK and ADDR_CTRL Routing Specification
            2. 7.7.2.3.6.2 DQS[x] and DQ[x] Routing Specification
    8. 7.8  I2C
      1. 7.8.1 I2C Electrical Data and Timing
    9. 7.9  JTAG Electrical Data and Timing
    10. 7.10 LCD Controller (LCDC)
      1. 7.10.1 LCD Interface Display Driver (LIDD Mode)
      2. 7.10.2 LCD Raster Mode
    11. 7.11 Multichannel Audio Serial Port (McASP)
      1. 7.11.1 McASP Device-Specific Information
      2. 7.11.2 McASP Electrical Data and Timing
    12. 7.12 Multichannel Serial Port Interface (McSPI)
      1. 7.12.1 McSPI Electrical Data and Timing
        1. 7.12.1.1 McSPI—Slave Mode
        2. 7.12.1.2 McSPI—Master Mode
    13. 7.13 Multimedia Card (MMC) Interface
      1. 7.13.1 MMC Electrical Data and Timing
    14. 7.14 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      1. 7.14.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. 7.14.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
        2. 7.14.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
        3. 7.14.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
      2. 7.14.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. 7.14.2.1 PRU-ICSS ECAT Electrical Data and Timing
      3. 7.14.3 PRU-ICSS MII_RT and Switch
        1. 7.14.3.1 PRU-ICSS MDIO Electrical Data and Timing
        2. 7.14.3.2 PRU-ICSS MII_RT Electrical Data and Timing
      4. 7.14.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. 7.15.1 UART Electrical Data and Timing
      2. 7.15.2 UART IrDA Interface
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Via Channel
    2. 9.2 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZCZ|324
  • ZCE|298
サーマルパッド・メカニカル・データ
発注情報

6 Power and Clocking

6.1 Power Supplies

6.1.1 Power Supply Slew Rate Requirement

To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the maximum slew rate for powering on the supplies to be less than 1.0E +5 V/s. For instance, as shown in Figure 6-1, TI recommends a value greater than 18 µs for the supply ramp slew for a 1.8-V supply.

AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 slew_rate_sprs717.gif Figure 6-1 Power Supply Slew and Slew Rate
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 power_sequence_preferred_dual_3_3.gif
A. RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach a valid level before RTC reset is released.
B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same source if the application only uses operating performance points (OPPs) that define a common power supply voltage for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE domain.
C. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a 3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
D. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V I/O power supplies.
E. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence shown provides the lowest leakage option.
F. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommended sequence.
Figure 6-2 Preferred Power-Supply Sequencing With Dual-Voltage I/Os Configured as 3.3 V
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 power_sequence_alt_dual_3_3.gif
A. RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach a valid level before RTC reset is released.
B. The 3.3-V I/O power supplies may be ramped simultaneously with the 1.8-V I/O power supplies if the voltage sourced by any 3.3-V power supplies does not exceed the voltage sourced by any 1.8-V power supply by more than 2 V. Serious reliability issues may occur if the system power supply design allows any 3.3-V I/O power supplies to exceed any 1.8-V I/O power supplies by more than 2 V.
C. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same source if the application only uses operating performance points (OPPs) that define a common power supply voltage for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE domain.
D. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a 3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
E. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V I/O power supplies.
F. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence shown provides the lowest leakage option.
G. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommended sequence.
Figure 6-3 Alternate Power-Supply Sequencing With Dual-Voltage I/Os Configured as 3.3 V
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 power_sequence_dual_1_8.gif
A. RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach a valid level before RTC reset is released.
B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same source if the application only uses operating performance points (OPPs) that define a common power supply voltage for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE domain.
C. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a 3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
D. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V I/O power supplies.
E. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence shown provides the lowest leakage option.
F. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommended sequence.
Figure 6-4 Power-Supply Sequencing With Dual-Voltage I/Os Configured as 1.8 V
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 power_sequence_rtc_ldo_disabled.gif
A. RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach a valid level before RTC reset is released.
B. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply.
C. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same source if the application only uses operating performance points (OPPs) that define a common power supply voltage for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE domain.
D. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a 3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
E. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V I/O power supplies.
F. VDDS_RTC should be ramped at the same time or before CAP_VDD_RTC, but these power inputs can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence shown provides the lowest leakage option.
G. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommended sequence.
Figure 6-5 Power-Supply Sequencing With Internal RTC LDO Disabled
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 power_sequence_rtc_disabled.gif
A. CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. The PMIC_POWER_EN output cannot be used when the RTC is disabled.
B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same source if the application only uses operating performance points (OPPs) that define a common power supply voltage for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE domain.
C. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a 3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
D. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V I/O power supplies.
E. VDDS_RTC should be ramped at the same time or before CAP_VDD_RTC, but these power inputs can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence shown provides the lowest leakage option.
F. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommended sequence.
Figure 6-6 Power-Supply Sequencing With RTC Feature Disabled

6.1.2 Power-Down Sequencing

PWRONRSTn input terminal should be taken low, which stops all internal clocks before power supplies are turned off. All other external clocks to the device should be shut off.

The preferred way to sequence power down is to have all the power supplies ramped down sequentially in the exact reverse order of the power-up sequencing. In other words, the power supply that has been ramped up first should be the last one that should be ramped down. This ensures there would be no spurious current paths during the power-down sequence. The VDDS power supply must ramp down after all 3.3-V VDDSHVx [1-6] power supplies.

If it is desired to ramp down VDDS and VDDSHVx [1-6] simultaneously, it should always be ensured that the difference between VDDS and VDDSHVx [1-6] during the entire power-down sequence is <2 V. Any violation of this could cause reliability risks for the device. TI recommends maintaining VDDS ≥1.5V as all the other supplies fully ramp down to minimize in-rush currents.

If none of the VDDSHVx [1-6] power supplies are configured as 3.3 V, the VDDS power supply may ramp down along with the VDDSHVx [1-6] supplies or after all the VDDSHVx [1-6] supplies have ramped down. TI recommends maintaining VDDS ≥1.5V as all the other supplies fully ramp down to minimize in-rush currents.

6.1.3 VDD_MPU_MON Connections

Figure 6-7 shows the VDD_MPU_MON connectivity. VDD_MPU_MON connectivity is available only on the ZCZ package.

AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 conncection_VDD_MPU_MON_sprs717.gif Figure 6-7 VDD_MPU_MON Connectivity

6.1.4 Digital Phase-Locked Loop Power Supply Requirements

The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the AM335x device. The AM335x device integrates five different DPLLs—Core DPLL, Per DPLL, LCD DPLL, DDR DPLL, MPU DPLL.

Figure 6-8 shows the power supply connectivity implemented in the AM335x device. Table 6-1 provides the power supply requirements for the DPLL.

AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 dpll_ps_connect_sprs717.gif Figure 6-8 DPLL Power Supply Connectivity

Table 6-1 DPLL Power Supply Requirements

SUPPLY NAME DESCRIPTION MIN NOM MAX UNIT
VDDA1P8V_USB0 Supply voltage range for USBPHY and PER DPLL, Analog, 1.8 V 1.71 1.8 1.89 V
Max peak-to-peak supply noise              50 mV (p-p)
VDDS_PLL_MPU Supply voltage range for DPLL MPU, analog 1.71 1.8 1.89 V
Max peak-to-peak supply noise              50 mV (p-p)
VDDS_PLL_CORE_LCD Supply voltage range for DPLL CORE and LCD, analog 1.71 1.8 1.89 V
Max peak-to-peak supply noise 50 mV (p-p)
VDDS_PLL_DDR Supply voltage range for DPLL DDR, analog 1.71 1.8 1.89 V
Max peak-to-peak supply noise              50 mV (p-p)

6.2 Clock Specifications

6.2.1 Input Clock Specifications

The AM335x device has two clock inputs. Each clock input passes through an internal oscillator which can be connected to an external crystal circuit (oscillator mode) or external LVCMOS square-wave digital clock source (bypass mode). The oscillators automatically operate in bypass mode when their input is connected to an external LVCMOS square-wave digital clock source. The oscillator associated with a specific clock input must be enabled when the clock input is being used in either oscillator mode or bypass mode.

The OSC1 oscillator provides a 32.768-kHz reference clock to the real-time clock (RTC) and is connected to the RTC_XTALIN and RTC_XTALOUT terminals. This clock source is referred to as the 32K oscillator (CLK_32K_RTC) in the AM335x and AMIC110 Sitara Processors Technical Reference Manual. OSC1 is disabled by default after power is applied. This clock input is optional and may not be required if the RTC is configured to receive a clock from the internal 32k RC oscillator (CLK_RC32K) or peripheral PLL (CLK_32KHZ) which receives a reference clock from the OSC0 input.

The OSC0 oscillator provides a 19.2-MHz, 24-MHz, 25-MHz, or 26-MHz reference clock which is used to clock all non-RTC functions and is connected to the XTALIN and XTALOUT terminals. This clock source is referred to as the master oscillator (CLK_M_OSC) in the AM335x and AMIC110 Sitara Processors Technical Reference Manual. OSC0 is enabled by default after power is applied.

For more information related to recommended circuit topologies and crystal oscillator circuit requirements for these clock inputs, see Section 6.2.2.

6.2.2 Input Clock Requirements

6.2.2.1 OSC0 Internal Oscillator Clock Source

Figure 6-9 shows the recommended crystal circuit. TI recommends that preproduction printed-circuit board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on preproduction PCBs.

The XTALIN terminal has a 15- to 40-kΩ internal pulldown resistor which is enabled when OSC0 is disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer.

AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 osc0_crystal_sprs717.gif
A. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package. Parasitic capacitance to the VSS_OSC and respective crystal circuit component grounds should be connected directly to the nearest PCB digital ground (VSS).
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components (excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL = [(C1 × C2) / (C1 + C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer plus any mutual capacitance (Cpkg + CPCB) seen across the AM335x XTALIN and XTALOUT signals. For recommended values of crystal circuit components, see Table 6-2.
Figure 6-9 OSC0 Crystal Circuit Schematic

Table 6-2 OSC0 Crystal Circuit Requirements

PARAMETER MIN TYP MAX UNIT
ƒxtal Crystal parallel resonance frequency Fundamental mode oscillation only 19.2, 24, 25, or 26 MHz
Crystal frequency stability and tolerance(1) –50 50 ppm
CC1 C1 capacitance Cshunt ≤ 5 pF 12 24 pF
Cshunt > 5 pF 18 24
CC2 C2 capacitance Cshunt ≤ 5 pF 12 24 pF
Cshunt > 5 pF 18 24
Cshunt Shunt capacitance 7 pF
ESR Crystal effective series resistance ƒxtal = 19.2 MHz, oscillator has nominal negative resistance of 272 Ω and worst-case negative resistance of 163 Ω 54.4 Ω
ƒxtal = 24 MHz, oscillator has nominal negative resistance of 240 Ω and worst-case negative resistance of 144 Ω 48.0
ƒxtal = 25 MHz, oscillator has nominal negative resistance of 233 Ω and worst-case negative resistance of 140 Ω 46.6
ƒxtal = 26 MHz, oscillator has nominal negative resistance of 227 Ω and worst-case negative resistance of 137 Ω 45.3
(1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.

Table 6-3 OSC0 Crystal Circuit Characteristics

NAME DESCRIPTION MIN TYP MAX UNIT
Cpkg Shunt capacitance of package ZCE package 0.01 pF
ZCZ package 0.01
Pxtal The actual values of the ESR, ƒxtal, and CL should be used to yield a typical crystal power dissipation value. Using the maximum values specified for ESR, ƒxtal, and CL parameters yields a maximum power dissipation value. Pxtal = 0.5 ESR (2 π ƒxtal CL VDDS_OSC)2
tsX Start-up time 1.5 ms
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 osc_startup_osc_sprs717.gif Figure 6-10 OSC0 Start-Up Time

6.2.2.2 OSC0 LVCMOS Digital Clock Source

Figure 6-11 shows the recommended oscillator connections when OSC0 is connected to an LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the XTALIN terminal. The ground for the LVCMOS clock source and VSS_OSC should be connected directly to the nearest PCB digital ground (VSS). In this mode of operation, the XTALOUT terminal should not be used to source any external components. The PCB design should provide a mechanism to disconnect the XTALOUT terminal from any external components or signal traces that may couple noise into OSC0 via the XTALOUT terminal.

The XTALIN terminal has a 15- to 40-kΩ internal pulldown resistor which is enabled when OSC0 is disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer.

AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 osc0_lvcmos_ciruit_sche_sprs717.gif Figure 6-11 OSC0 LVCMOS Circuit Schematic

Table 6-4 OSC0 LVCMOS Reference Clock Requirements

NAME DESCRIPTION MIN TYP MAX UNIT
ƒ(XTALIN) Frequency, LVCMOS reference clock 19.2, 24, 25, or 26 MHz
Frequency, LVCMOS reference clock stability and tolerance(1) –50 50 ppm
tdc(XTALIN) Duty cycle, LVCMOS reference clock period 45% 55%
tjpp(XTALIN) Jitter peak-to-peak, LVCMOS reference clock period –1% 1%
tR(XTALIN) Time, LVCMOS reference clock rise 5 ns
tF(XTALIN) Time, LVCMOS reference clock fall 5 ns
(1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.

6.2.2.3 OSC1 Internal Oscillator Clock Source

Figure 6-12 shows the recommended crystal circuit for OSC1 of the ZCE package and Figure 6-13 shows the recommended crystal circuit for OSC1 of the ZCZ package. TI recommends that preproduction PCB designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on preproduction PCBs.

The RTC_XTALIN terminal has a 10- to 40-kΩ internal pullup resistor which is enabled when OSC1 is disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer.

AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 osc1_crystal_circuit_sche_sprs717.gif
A. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package. Parasitic capacitance to the PCB ground and other signals should be minimized to reduce noise coupled into the oscillator. VSS_RTC and respective crystal circuit component grounds should be connected directly to the nearest PCB digital ground (VSS).
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components (excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL = [(C1 × C2) / (C1 + C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer plus any mutual capacitance (Cpkg + CPCB) seen across the AM335x RTC_XTALIN and RTC_XTALOUT signals. For recommended values of crystal circuit components, see Table 6-5.
Figure 6-12 OSC1 (ZCE Package) Crystal Circuit Schematic
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 osc1_crystal_zcz_sprs717.gif
A. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package. Parasitic capacitance to the PCB ground and other signals should be minimized to reduce noise coupled into the oscillator. VSS_RTC and respective crystal circuit component grounds should be connected directly to the nearest PCB digital ground (VSS).
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components (excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL = [(C1 × C2) / (C1 + C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer plus any mutual capacitance (Cpkg + CPCB) seen across the AM335x RTC_XTALIN and RTC_XTALOUT signals. For recommended values of crystal circuit components, see Table 6-5.
Figure 6-13 OSC1 (ZCZ Package) Crystal Circuit Schematic

Table 6-5 OSC1 Crystal Circuit Requirements

NAME DESCRIPTION MIN TYP MAX UNIT
ƒxtal Crystal parallel resonance frequency Fundamental mode oscillation only 32.768 kHz
Crystal frequency stability and tolerance(1) Maximum RTC error = 10.512 minutes per year –20.0 20.0 ppm
Maximum RTC error = 26.28 minutes per year –50.0 50.0 ppm
CC1 C1 capacitance 12.0 24.0 pF
CC2 C2 capacitance 12.0 24.0 pF
Cshunt Shunt capacitance 1.5 pF
ESR Crystal effective series resistance ƒxtal = 32.768 kHz, oscillator has nominal negative resistance of 725 kΩ and worst-case negative resistance of 250 kΩ 80 kΩ
(1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.

Table 6-6 OSC1 Crystal Circuit Characteristics

NAME DESCRIPTION MIN TYP MAX UNIT
Cpkg Shunt capacitance of package ZCE package 0.17 pF
ZCZ package 0.01 pF
Pxtal The actual values of the ESR, ƒxtal, and CL should be used to yield a typical crystal power dissipation value. Using the maximum values specified for ESR, ƒxtal, and CL parameters yields a maximum power dissipation value. Pxtal = 0.5 ESR (2 π ƒxtal CL VDDS_RTC)2
tsX Start-up time 2 s
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 osc_startup_rtc_sprs717.gif Figure 6-14 OSC1 Start-up Time

6.2.2.4 OSC1 LVCMOS Digital Clock Source

Figure 6-15 shows the recommended oscillator connections when OSC1 of the ZCE package is connected to an LVCMOS square-wave digital clock source and Figure 6-16 shows the recommended oscillator connections when OSC1 of the ZCZ package is connected to an LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the RTC_XTALIN terminal. The ground for the LVCMOS clock source and VSS_RTC of the ZCZ package should be connected directly to the nearest PCB digital ground (VSS). In this mode of operation, the RTC_XTALOUT terminal should not be used to source any external components. The PCB design should provide a mechanism to disconnect the RTC_XTALOUT terminal from any external components or signal traces that may couple noise into OSC1 through the RTC_XTALOUT terminal.

The RTC_XTALIN terminal has a 10- to 40-kΩ internal pullup resistor which is enabled when OSC1 is disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer.

AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 osc1_lvcmoc_circuit_sche_sprs717.gif Figure 6-15 OSC1 (ZCE Package) LVCMOS Circuit Schematic
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 osc1_lvcmos_circuit_zcz_sprs717.gif Figure 6-16 OSC1 (ZCZ Package) LVCMOS Circuit Schematic

Table 6-7 OSC1 LVCMOS Reference Clock Requirements

NAME DESCRIPTION MIN TYP MAX UNIT
ƒ(RTC_XTALIN) Frequency, LVCMOS reference clock 32.768 kHz
Frequency, LVCMOS reference clock stability and tolerance(1) Maximum RTC error = 10.512 minutes/year –20 20 ppm
Maximum RTC error = 26.28 minutes/year –50 50 ppm
tdc(RTC_XTALIN) Duty cycle, LVCMOS reference clock period 45% 55%
tjpp(RTC_XTALIN) Jitter peak-to-peak, LVCMOS reference clock period –1% 1%
tR(RTC_XTALIN) Time, LVCMOS reference clock rise 5 ns
tF(RTC_XTALIN) Time, LVCMOS reference clock fall 5 ns
(1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.

6.2.2.5 OSC1 Not Used

Figure 6-17 shows the recommended oscillator connections when OSC1 of the ZCE package is not used and Figure 6-18 shows the recommended oscillator connections when OSC1 of the ZCZ package is not used. An internal 10-kΩ pullup on the RTC_XTALIN terminal is turned on when OSC1 is disabled to prevent this input from floating to an invalid logic level which may increase leakage current through the oscillator input buffer. OSC1 is disabled by default after power is applied. Therefore, both RTC_XTALIN and RTC_XTALOUT terminals should be a no connect (NC) when OSC1 is not used.

AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 osc1_not_used_sche_sprs717.gif Figure 6-17 OSC1 (ZCE Package) Not Used Schematic
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 osc1_not_used_zcz_sprs717.gif Figure 6-18 OSC1 (ZCZ Package) Not Used Schematic

6.2.3 Output Clock Specifications

The AM335x device has two clock output signals. The CLKOUT1 signal is always a replica of the OSC0 input clock which is referred to as the master oscillator (CLK_M_OSC) in the AM335x and AMIC110 Sitara Processors Technical Reference Manual. The CLKOUT2 signal can be configured to output the OSC1 input clock, which is referred to as the 32K oscillator (CLK_32K_RTC) in the AM335x and AMIC110 Sitara Processors Technical Reference Manual, or four other internal clocks. For more information related to configuring these clock output signals, see the CLKOUT Signals section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.

6.2.4 Output Clock Characteristics

NOTE

The AM335x CLKOUT1 and CLKOUT2 clock outputs should not be used as a synchronous clock for any of the peripheral interfaces because they were not timing closed to any other signals. These clock outputs also were not designed to source any time critical external circuits that require a low jitter reference clock. The jitter performance of these outputs is unpredictable due to complex combinations of many system variables. For example, CLKOUT2 may be sourced from several PLLs with each PLL supporting many configurations that yield different jitter performance. There are also other unpredictable contributors to jitter performance such as application specific noise or crosstalk into the clock circuits. Therefore, there are no plans to specify jitter performance for these outputs.

6.2.4.1 CLKOUT1

The CLKOUT1 signal can be output on the XDMA_EVENT_INTR0 terminal. This terminal connects to one of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR0 multiplexer must be configured for Mode 3 to connect the CLKOUT1 signal to the XDMA_EVENT_INTR0 terminal.

The default reset configuration of the XDMA_EVENT_INTR0 multiplexer is selected by the logic level applied to the LCD_DATA5 terminal on the rising edge of PWRONRSTn. The XDMA_EVENT_INTR0 multiplexer is configured to Mode 7 if the LCD_DATA5 terminal is low on the rising edge of PWRONRSTn or Mode 3 if the LCD_DATA5 terminal is high on the rising edge of PWRONRSTn. This allows the CLKOUT1 signal to be output on the XDMA_EVENT_INTR0 terminal without software intervention. In this mode, the output is held low while PWRONRSTn is active and begins to toggle after PWRONRSTn is released.

6.2.4.2 CLKOUT2

The CLKOUT2 signal can be output on the XDMA_EVENT_INTR1 terminal. This terminal connects to one of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR1 multiplexer must be configured for Mode 3 to connect the CLKOUT2 signal to the XDMA_EVENT_INTR1 terminal.

The default reset configuration of the XDMA_EVENT_INTR1 multiplexer is always Mode 7. Software must configure the XDMA_EVENT_INTR1 multiplexer to Mode 3 for the CLKOUT2 signal to be output on the XDMA_EVENT_INTR1 terminal.