JAJSDZ0J October   2011  – April 2016 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
      1. 4.1.1 ZCE Package Pin Maps (Top View)
      2. 4.1.2 ZCZ Package Pin Maps (Top View)
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 External Memory Interfaces
      2. 4.3.2 General-Purpose IOs
      3. 4.3.3 Miscellaneous
        1. 4.3.3.1 eCAP
        2. 4.3.3.2 eHRPWM
        3. 4.3.3.3 eQEP
        4. 4.3.3.4 Timer
      4. 4.3.4 PRU-ICSS
        1. 4.3.4.1 PRU0
        2. 4.3.4.2 PRU1
      5. 4.3.5 Removable Media Interfaces
      6. 4.3.6 Serial Communication Interfaces
        1. 4.3.6.1 CAN
        2. 4.3.6.2 GEMAC_CPSW
        3. 4.3.6.3 I2C
        4. 4.3.6.4 McASP
        5. 4.3.6.5 SPI
        6. 4.3.6.6 UART
        7. 4.3.6.7 USB
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points (OPPs)
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  Thermal Resistance Characteristics for ZCE and ZCZ Packages
    9. 5.9  External Capacitors
      1. 5.9.1 Voltage Decoupling Capacitors
        1. 5.9.1.1 Core Voltage Decoupling Capacitors
        2. 5.9.1.2 I/O and Analog Voltage Decoupling Capacitors
      2. 5.9.2 Output Capacitors
    10. 5.10 Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
  6. 6Power and Clocking
    1. 6.1 Power Supplies
      1. 6.1.1 Power Supply Slew Rate Requirement
      2. 6.1.2 Power-Down Sequencing
      3. 6.1.3 VDD_MPU_MON Connections
      4. 6.1.4 Digital Phase-Locked Loop Power Supply Requirements
    2. 6.2 Clock Specifications
      1. 6.2.1 Input Clock Specifications
      2. 6.2.2 Input Clock Requirements
        1. 6.2.2.1 OSC0 Internal Oscillator Clock Source
        2. 6.2.2.2 OSC0 LVCMOS Digital Clock Source
        3. 6.2.2.3 OSC1 Internal Oscillator Clock Source
        4. 6.2.2.4 OSC1 LVCMOS Digital Clock Source
        5. 6.2.2.5 OSC1 Not Used
      3. 6.2.3 Output Clock Specifications
      4. 6.2.4 Output Clock Characteristics
        1. 6.2.4.1 CLKOUT1
        2. 6.2.4.2 CLKOUT2
  7. 7Peripheral Information and Timings
    1. 7.1  Parameter Information
      1. 7.1.1 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  OPP50 Support
    4. 7.4  Controller Area Network (CAN)
      1. 7.4.1 DCAN Electrical Data and Timing
    5. 7.5  DMTimer
      1. 7.5.1 DMTimer Electrical Data and Timing
    6. 7.6  Ethernet Media Access Controller (EMAC) and Switch
      1. 7.6.1 EMAC and Switch Electrical Data and Timing
        1. 7.6.1.1 EMAC/Switch MDIO Electrical Data and Timing
        2. 7.6.1.2 EMAC and Switch MII Electrical Data and Timing
        3. 7.6.1.3 EMAC and Switch RMII Electrical Data and Timing
        4. 7.6.1.4 EMAC and Switch RGMII Electrical Data and Timing
    7. 7.7  External Memory Interfaces
      1. 7.7.1 General-Purpose Memory Controller (GPMC)
        1. 7.7.1.1 GPMC and NOR Flash—Synchronous Mode
        2. 7.7.1.2 GPMC and NOR Flash—Asynchronous Mode
        3. 7.7.1.3 GPMC and NAND Flash—Asynchronous Mode
      2. 7.7.2 mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
        1. 7.7.2.1 mDDR (LPDDR) Routing Guidelines
          1. 7.7.2.1.1 Board Designs
          2. 7.7.2.1.2 LPDDR Interface
            1. 7.7.2.1.2.1 LPDDR Interface Schematic
            2. 7.7.2.1.2.2 Compatible JEDEC LPDDR Devices
            3. 7.7.2.1.2.3 PCB Stackup
            4. 7.7.2.1.2.4 Placement
            5. 7.7.2.1.2.5 LPDDR Keepout Region
            6. 7.7.2.1.2.6 Bulk Bypass Capacitors
            7. 7.7.2.1.2.7 High-Speed Bypass Capacitors
            8. 7.7.2.1.2.8 Net Classes
            9. 7.7.2.1.2.9 LPDDR Signal Termination
          3. 7.7.2.1.3 LPDDR CK and ADDR_CTRL Routing
        2. 7.7.2.2 DDR2 Routing Guidelines
          1. 7.7.2.2.1 Board Designs
          2. 7.7.2.2.2 DDR2 Interface
            1. 7.7.2.2.2.1  DDR2 Interface Schematic
            2. 7.7.2.2.2.2  Compatible JEDEC DDR2 Devices
            3. 7.7.2.2.2.3  PCB Stackup
            4. 7.7.2.2.2.4  Placement
            5. 7.7.2.2.2.5  DDR2 Keepout Region
            6. 7.7.2.2.2.6  Bulk Bypass Capacitors
            7. 7.7.2.2.2.7  High-Speed (HS) Bypass Capacitors
            8. 7.7.2.2.2.8  Net Classes
            9. 7.7.2.2.2.9  DDR2 Signal Termination
            10. 7.7.2.2.2.10 DDR_VREF Routing
          3. 7.7.2.2.3 DDR2 CK and ADDR_CTRL Routing
        3. 7.7.2.3 DDR3 and DDR3L Routing Guidelines
          1. 7.7.2.3.1 Board Designs
            1. 7.7.2.3.1.1 DDR3 versus DDR2
          2. 7.7.2.3.2 DDR3 Device Combinations
          3. 7.7.2.3.3 DDR3 Interface
            1. 7.7.2.3.3.1  DDR3 Interface Schematic
            2. 7.7.2.3.3.2  Compatible JEDEC DDR3 Devices
            3. 7.7.2.3.3.3  PCB Stackup
            4. 7.7.2.3.3.4  Placement
            5. 7.7.2.3.3.5  DDR3 Keepout Region
            6. 7.7.2.3.3.6  Bulk Bypass Capacitors
            7. 7.7.2.3.3.7  High-Speed Bypass Capacitors
              1. 7.7.2.3.3.7.1 Return Current Bypass Capacitors
            8. 7.7.2.3.3.8  Net Classes
            9. 7.7.2.3.3.9  DDR3 Signal Termination
            10. 7.7.2.3.3.10 DDR_VREF Routing
            11. 7.7.2.3.3.11 VTT
          4. 7.7.2.3.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
            1. 7.7.2.3.4.1 Two DDR3 Devices
              1. 7.7.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
              2. 7.7.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
            2. 7.7.2.3.4.2 One DDR3 Device
              1. 7.7.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
              2. 7.7.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device
          5. 7.7.2.3.5 Data Topologies and Routing Definition
            1. 7.7.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
            2. 7.7.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
          6. 7.7.2.3.6 Routing Specification
            1. 7.7.2.3.6.1 CK and ADDR_CTRL Routing Specification
            2. 7.7.2.3.6.2 DQS[x] and DQ[x] Routing Specification
    8. 7.8  I2C
      1. 7.8.1 I2C Electrical Data and Timing
    9. 7.9  JTAG Electrical Data and Timing
    10. 7.10 LCD Controller (LCDC)
      1. 7.10.1 LCD Interface Display Driver (LIDD Mode)
      2. 7.10.2 LCD Raster Mode
    11. 7.11 Multichannel Audio Serial Port (McASP)
      1. 7.11.1 McASP Device-Specific Information
      2. 7.11.2 McASP Electrical Data and Timing
    12. 7.12 Multichannel Serial Port Interface (McSPI)
      1. 7.12.1 McSPI Electrical Data and Timing
        1. 7.12.1.1 McSPI—Slave Mode
        2. 7.12.1.2 McSPI—Master Mode
    13. 7.13 Multimedia Card (MMC) Interface
      1. 7.13.1 MMC Electrical Data and Timing
    14. 7.14 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      1. 7.14.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. 7.14.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
        2. 7.14.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
        3. 7.14.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
      2. 7.14.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. 7.14.2.1 PRU-ICSS ECAT Electrical Data and Timing
      3. 7.14.3 PRU-ICSS MII_RT and Switch
        1. 7.14.3.1 PRU-ICSS MDIO Electrical Data and Timing
        2. 7.14.3.2 PRU-ICSS MII_RT Electrical Data and Timing
      4. 7.14.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. 7.15.1 UART Electrical Data and Timing
      2. 7.15.2 UART IrDA Interface
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Via Channel
    2. 9.2 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZCZ|324
  • ZCE|298
サーマルパッド・メカニカル・データ
発注情報

4 Terminal Configuration and Functions

4.1 Pin Diagram

NOTE

The terms 'ball', 'pin', and 'terminal' are used interchangeably throughout the document. An attempt is made to use 'ball' only when referring to the physical package.

4.1.1 ZCE Package Pin Maps (Top View)

The pin maps that follow show the pin assignments on the ZCE package in three sections (left, middle, and right).

Table 4-1 ZCE Pin Map [Section Left - Top View]

A B C D E F
19 VSS I2C0_SCL UART1_TXD UART1_RTSn UART0_RXD UART0_CTSn
18 SPI0_SCLK SPI0_D0 I2C0_SDA UART1_RXD ECAP0_IN_PWM0_OUT UART0_RTSn
17 SPI0_CS0 SPI0_D1 EXTINTn XXXX UART1_CTSn UART0_TXD
16 WARMRSTn SPI0_CS1 XXXX XXXX XXXX VDDS
15 EMU0 XDMA_EVENT_INTR1 XDMA_EVENT_INTR0 XXXX PWRONRSTn XXXX
14 TDO TCK TMS EMU1 XXXX VDDSHV6
13 TRSTn TDI CAP_VBB_MPU CAP_VDD_SRAM_MPU VDDSHV6 VSS
12 AIN7 AIN5 VDDS_SRAM_MPU_BB VDDS VDDSHV6 VSS
11 AIN1 AIN3 XXXX XXXX VDDSHV6 VDD_CORE
10 AIN6 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VSS VSS XXXX
9 VREFP VREFN XXXX XXXX VSS VDD_CORE
8 AIN2 AIN0 AIN4 VSSA_ADC VSS VSS
7 RTC_KALDO_ENn RTC_PWRONRSTn PMIC_POWER_EN VDDA_ADC VSS VSS
6 RTC_XTALIN RESERVED VDDS_RTC CAP_VDD_RTC XXXX VSS
5 RTC_XTALOUT EXT_WAKEUP VDDS_PLL_DDR XXXX DDR_A4 XXXX
4 DDR_WEn DDR_BA2 XXXX XXXX XXXX DDR_A12
3 DDR_BA0 DDR_A3 DDR_A8 XXXX DDR_A15 DDR_A0
2 DDR_A5 DDR_A9 DDR_CK DDR_A7 DDR_A10 DDR_RASn
1 VSS DDR_A6 DDR_CKn DDR_A2 DDR_BA1 DDR_CASn
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_left.gif

ZCE Pin Map [Section Middle - Top View]

G H J K L M
19 MMC0_CLK MMC0_DAT3 MII1_COL MII1_RX_ER MII1_RX_DV MII1_RX_CLK
18 MMC0_DAT0 MMC0_DAT2 MII1_CRS RMII1_REF_CLK MII1_TXD0 MII1_TXD1
17 MMC0_CMD MMC0_DAT1 XXXX MII1_TX_EN XXXX MII1_TXD3
16 USB0_DRVVBUS VDDS_PLL_MPU XXXX VDD_CORE XXXX VDDS
15 VDDSHV4 VDDSHV4 VSS VDD_CORE VSS VDDSHV5
14 XXXX VDDSHV4 VSS XXXX VSS VDDSHV5
13 XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE
12 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE
11 VDD_CORE VSS VSS VSS VSS VSS
10 XXXX VSS XXXX XXXX XXXX VSS
9 VDD_CORE VSS VSS VSS VSS VSS
8 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE
7 XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE
6 XXXX VDDS_DDR VSS XXXX VSS VDDS_DDR
5 VDDS_DDR VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR
4 DDR_A11 DDR_VREF XXXX VDDS_DDR XXXX DDR_D11
3 DDR_CKE DDR_A14 XXXX DDR_DQM1 XXXX DDR_D10
2 DDR_RESETn DDR_CSn0 DDR_A1 DDR_D8 DDR_DQSn1 DDR_D12
1 DDR_ODT DDR_A13 DDR_VTP DDR_D9 DDR_DQS1 DDR_D13
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_middle.gif

ZCE Pin Map [Section Right - Top View]

N P R T U V W
19 MII1_TX_CLK MII1_RXD1 MDC USB0_VBUS USB0_DP USB0_ID VSS
18 MII1_TXD2 MII1_RXD0 VDDA3P3V_USB0 USB0_CE USB0_DM GPMC_BEn1 GPMC_WPn
17 MII1_RXD3 MDIO VDDA1P8V_USB0 XXXX GPMC_CSn3 GPMC_AD15 GPMC_AD14
16 MII1_RXD2 VSSA_USB XXXX XXXX XXXX GPMC_CLK GPMC_AD9
15 VDDSHV5 XXXX GPMC_WAIT0 XXXX GPMC_CSn2 GPMC_AD8 GPMC_AD7
14 XXXX VSS XXXX VDDS GPMC_AD6 GPMC_CSn1 GPMC_AD5
13 XXXX VSS VDDSHV1 GPMC_AD13 GPMC_AD12 GPMC_AD4 GPMC_AD3
12 VSS VSS VDDSHV1 GPMC_AD10 GPMC_AD11 GPMC_AD2 XTALOUT
11 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX VSS_OSC XTALIN
10 XXXX XXXX VSS VSS VDDS_OSC GPMC_ADVn_ALE GPMC_AD0
9 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX GPMC_AD1 GPMC_OEn_REn
8 VSS VSS VDDSHV1 VDDS_PLL_CORE_LCD GPMC_WEn GPMC_BEn0_CLE GPMC_CSn0
7 XXXX VSS VDDSHV6 LCD_HSYNC LCD_VSYNC LCD_DATA15 LCD_AC_BIAS_EN
6 XXXX VDDSHV6 XXXX VDDS LCD_DATA13 LCD_DATA12 LCD_DATA14
5 VDDS_DDR XXXX VPP XXXX LCD_DATA10 LCD_DATA11 LCD_PCLK
4 DDR_D0 DDR_D1 XXXX XXXX XXXX LCD_DATA8 LCD_DATA9
3 DDR_DQM0 DDR_D4 DDR_D7 XXXX LCD_DATA7 LCD_DATA6 LCD_DATA5
2 DDR_D14 DDR_D2 DDR_DQSn0 DDR_D6 LCD_DATA1 LCD_DATA3 LCD_DATA4
1 DDR_D15 DDR_D3 DDR_DQS0 DDR_D5 LCD_DATA0 LCD_DATA2 VSS
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_right.gif

4.1.2 ZCZ Package Pin Maps (Top View)

The pin maps that follow show the pin assignments on the ZCZ package in three sections (left, middle, and right).

ZCZ Pin Map [Section Left - Top View]

A B C D E F
18 VSS EXTINTn ECAP0_IN_PWM0_OUT UART1_CTSn UART0_CTSn MMC0_DAT2
17 SPI0_SCLK SPI0_D0 I2C0_SDA UART1_RTSn UART0_RTSn MMC0_DAT3
16 SPI0_CS0 SPI0_D1 I2C0_SCL UART1_RXD UART0_TXD USB0_DRVVBUS
15 XDMA_EVENT_INTR0 PWRONRSTn SPI0_CS1 UART1_TXD UART0_RXD USB1_DRVVBUS
14 MCASP0_AHCLKX EMU1 EMU0 XDMA_EVENT_INTR1 VDDS VDDSHV6
13 MCASP0_ACLKX MCASP0_FSX MCASP0_FSR MCASP0_AXR1 VDDSHV6 VDD_MPU
12 TCK MCASP0_ACLKR MCASP0_AHCLKR MCASP0_AXR0 VDDSHV6 VDD_MPU
11 TDO TDI TMS CAP_VDD_SRAM_MPU VDDSHV6 VDD_MPU
10 WARMRSTn TRSTn CAP_VBB_MPU VDDS_SRAM_MPU_BB VDDSHV6 VDD_MPU
9 VREFN VREFP AIN7 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VDDS
8 AIN6 AIN5 AIN4 VDDA_ADC VSSA_ADC VSS
7 AIN3 AIN2 AIN1 VDDS_RTC VDDS_PLL_DDR VDD_CORE
6 RTC_XTALIN AIN0 PMIC_POWER_EN CAP_VDD_RTC VDDS VDD_CORE
5 VSS_RTC RTC_PWRONRSTn EXT_WAKEUP DDR_A6 VDDS_DDR VDDS_DDR
4 RTC_XTALOUT RTC_KALDO_ENn DDR_BA0 DDR_A8 DDR_A2 DDR_A10
3 RESERVED DDR_BA2 DDR_A3 DDR_A15 DDR_A12 DDR_A0
2 VDD_MPU_MON DDR_WEn DDR_A4 DDR_CK DDR_A7 DDR_A11
1 VSS DDR_A5 DDR_A9 DDR_CKn DDR_BA1 DDR_CASn
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_left.gif

ZCZ Pin Map [Section Middle - Top View]

G H J K L M
18 MMC0_CMD RMII1_REF_CLK MII1_TXD3 MII1_TX_CLK MII1_RX_CLK MDC
17 MMC0_CLK MII1_CRS MII1_RX_DV MII1_TXD0 MII1_RXD3 MDIO
16 MMC0_DAT0 MII1_COL MII1_TX_EN MII1_TXD1 MII1_RXD2 MII1_RXD0
15 MMC0_DAT1 VDDS_PLL_MPU MII1_RX_ER MII1_TXD2 MII1_RXD1 USB0_CE
14 VDDSHV6 VDDSHV4 VDDSHV4 VDDSHV5 VDDSHV5 VSSA_USB
13 VDD_MPU VDD_MPU VDD_MPU VDDS VSS VDD_CORE
12 VSS VSS VDD_CORE VDD_CORE VSS VSS
11 VSS VDD_CORE VSS VSS VSS VDD_CORE
10 VDD_CORE VSS VSS VSS VSS VSS
9 VSS VSS VSS VSS VDD_CORE VSS
8 VSS VSS VSS VDD_CORE VDD_CORE VSS
7 VDD_CORE VSS VSS VSS VDD_CORE VSS
6 VDD_CORE VSS VSS VDD_CORE VDD_CORE VSS
5 VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VPP
4 DDR_RASn DDR_A14 DDR_VREF DDR_D12 DDR_D14 DDR_D1
3 DDR_CKE DDR_A13 DDR_VTP DDR_D11 DDR_D13 DDR_D0
2 DDR_RESETn DDR_CSn0 DDR_DQM1 DDR_D10 DDR_DQSn1 DDR_DQM0
1 DDR_ODT DDR_A1 DDR_D8 DDR_D9 DDR_DQS1 DDR_D15
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_middle.gif

ZCZ Pin Map [Section Right - Top View]

N P R T U V
18 USB0_DM USB1_CE USB1_DM USB1_VBUS GPMC_BEn1 VSS
17 USB0_DP USB1_ID USB1_DP GPMC_WAIT0 GPMC_WPn GPMC_A11
16 VDDA1P8V_USB0 USB0_ID VDDA1P8V_USB1 GPMC_A10 GPMC_A9 GPMC_A8
15 VDDA3P3V_USB0 USB0_VBUS VDDA3P3V_USB1 GPMC_A7 GPMC_A6 GPMC_A5
14 VSSA_USB VDDS GPMC_A4 GPMC_A3 GPMC_A2 GPMC_A1
13 VDD_CORE VDDSHV3 GPMC_A0 GPMC_CSn3 GPMC_AD15 GPMC_AD14
12 VDD_CORE VDDSHV3 GPMC_AD13 GPMC_AD12 GPMC_AD11 GPMC_CLK
11 VSS VDDSHV2 VDDS_OSC GPMC_AD10 XTALOUT VSS_OSC
10 VSS VDDSHV2 VDDS_PLL_CORE_LCD GPMC_AD9 GPMC_AD8 XTALIN
9 VDD_CORE VDDS GPMC_AD6 GPMC_AD7 GPMC_CSn1 GPMC_CSn2
8 VDD_CORE VDDSHV1 GPMC_AD2 GPMC_AD3 GPMC_AD4 GPMC_AD5
7 VSS VDDSHV1 GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD0 GPMC_AD1
6 VDDS VDDSHV6 LCD_AC_BIAS_EN GPMC_BEn0_CLE GPMC_WEn GPMC_CSn0
5 VDDSHV6 VDDSHV6 LCD_HSYNC LCD_DATA15 LCD_VSYNC LCD_PCLK
4 DDR_D5 DDR_D7 LCD_DATA3 LCD_DATA7 LCD_DATA11 LCD_DATA14
3 DDR_D4 DDR_D6 LCD_DATA2 LCD_DATA6 LCD_DATA10 LCD_DATA13
2 DDR_D3 DDR_DQSn0 LCD_DATA1 LCD_DATA5 LCD_DATA9 LCD_DATA12
1 DDR_D2 DDR_DQS0 LCD_DATA0 LCD_DATA4 LCD_DATA8 VSS
AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 ball_map_right.gif

4.2 Pin Attributes

The AM335x and AMIC110 Sitara Processors Technical Reference Manual and this document may reference internal signal names when discussing peripheral input and output signals because many of the AM335x package terminals can be multiplexed to one of several peripheral signals. The following table has a Pin Name column that lists all device terminal names and a Signal Name column that lists all internal signal names multiplexed to each terminal which provides a cross reference of internal signal names to terminal names. This table also identifies other important terminal characteristics.

  1. BALL NUMBER: Package ball numbers associated with each signals.
  2. PIN NAME: The name of the package pin or terminal.
    Note: The table does not take into account subsystem terminal multiplexing options.
  3. SIGNAL NAME: The signal name for that pin in the mode being used.
  4. MODE: Multiplexing mode number.
    1. Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the terminal corresponds to the name of the terminal. There is always a function mapped on the primary mode. Notice that primary mode is not necessarily the default mode.

      2. Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE column.

    2. Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are effectively used for alternate functions, while some modes are not used and do not correspond to a functional configuration.
  5. TYPE: Signal direction
    • I = Input
    • O = Output
    • I/O = Input and Output
    • D = Open drain
    • DS = Differential
    • A = Analog
    • PWR = Power
    • GND = Ground

      • Note: In the safe_mode, the buffer is configured in high-impedance.

  6. BALL RESET STATE: State of the terminal while the active low PWRONRSTn terminal is low.
    • 0: The buffer drives VOL (pulldown or pullup resistor not activated)
      0(PD): The buffer drives VOL with an active pulldown resistor
    • 1: The buffer drives VOH (pulldown or pullup resistor not activated)
      1(PU): The buffer drives VOH with an active pullup resistor
    • Z: High-impedance
    • L: High-impedance with an active pulldown resistor
    • H : High-impedance with an active pullup resistor
  7. BALL RESET REL. STATE: State of the terminal after the active low PWRONRSTn terminal transitions from low to high.
    • 0: The buffer drives VOL (pulldown or pullup resistor not activated)
      0(PD): The buffer drives VOL with an active pulldown resistor
    • 1: The buffer drives VOH (pulldown or pullup resistor not activated)
      1(PU): The buffer drives VOH with an active pullup resistor
    • Z: High-impedance.
    • L: High-impedance with an active pulldown resistor
    • H : High-impedance with an active pullup resistor
  8. RESET REL. MODE: The mode is automatically configured after the active low PWRONRSTn terminal transitions from low to high.
  9. POWER: The voltage supply that powers the I/O buffers of the terminal.
  10. HYS: Indicates if the input buffer is with hysteresis.
  11. BUFFER STRENGTH: Drive strength of the associated output buffer.
  12. PULLUP OR PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
  13. I/O CELL: I/O cell information.

    14. Note: Configuring two terminals to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration.

Table 4-2 Pin Attributes (ZCE and ZCZ Packages)

ZCE BALL NUMBER [1] ZCZ BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6](25) BALL RESET REL. STATE [7] RESET REL. MODE [8] ZCE POWER /
ZCZ POWER [9]		 HYS [10] BUFFER STRENGTH (mA) [11] PULLUP /DOWN TYPE [12] I/O CELL [13]
B8 B6 AIN0 AIN0 0 A (22) Z Z 0 VDDA_ADC / VDDA_ADC NA 25 NA Analog
A11 C7 AIN1 AIN1 0 A (21) Z Z 0 VDDA_ADC / VDDA_ADC NA 25 NA Analog
A8 B7 AIN2 AIN2 0 A (21) Z Z 0 VDDA_ADC / VDDA_ADC NA 25 NA Analog
B11 A7 AIN3 AIN3 0 A (20) Z Z 0 VDDA_ADC / VDDA_ADC NA 25 NA Analog
C8 C8 AIN4 AIN4 0 A (20) Z Z 0 VDDA_ADC / VDDA_ADC NA 25 NA Analog
B12 B8 AIN5 AIN5 0 A Z Z 0 VDDA_ADC / VDDA_ADC NA NA NA Analog
A10 A8 AIN6 AIN6 0 A Z Z 0 VDDA_ADC / VDDA_ADC NA NA NA Analog
A12 C9 AIN7 AIN7 0 A Z Z 0 VDDA_ADC / VDDA_ADC NA NA NA Analog
C13 C10 CAP_VBB_MPU CAP_VBB_MPU NA A
D6 D6 CAP_VDD_RTC CAP_VDD_RTC NA A
B10 D9 CAP_VDD_SRAM_CORE CAP_VDD_SRAM_CORE NA A
D13 D11 CAP_VDD_SRAM_MPU CAP_VDD_SRAM_MPU NA A
F3 F3 DDR_A0 ddr_a0 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
J2 H1 DDR_A1 ddr_a1 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
D1 E4 DDR_A2 ddr_a2 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
B3 C3 DDR_A3 ddr_a3 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
E5 C2 DDR_A4 ddr_a4 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
A2 B1 DDR_A5 ddr_a5 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
B1 D5 DDR_A6 ddr_a6 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
D2 E2 DDR_A7 ddr_a7 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
C3 D4 DDR_A8 ddr_a8 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
B2 C1 DDR_A9 ddr_a9 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
E2 F4 DDR_A10 ddr_a10 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
G4 F2 DDR_A11 ddr_a11 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
F4 E3 DDR_A12 ddr_a12 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
H1 H3 DDR_A13 ddr_a13 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
H3 H4 DDR_A14 ddr_a14 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
E3 D3 DDR_A15 ddr_a15 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
A3 C4 DDR_BA0 ddr_ba0 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
E1 E1 DDR_BA1 ddr_ba1 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
B4 B3 DDR_BA2 ddr_ba2 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
F1 F1 DDR_CASn ddr_casn 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
C2 D2 DDR_CK ddr_ck 0 O L 0 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
G3 G3 DDR_CKE ddr_cke 0 O L 0 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
C1 D1 DDR_CKn ddr_nck 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
H2 H2 DDR_CSn0 ddr_csn0 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
N4 M3 DDR_D0 ddr_d0 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
P4 M4 DDR_D1 ddr_d1 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
P2 N1 DDR_D2 ddr_d2 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
P1 N2 DDR_D3 ddr_d3 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
P3 N3 DDR_D4 ddr_d4 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
T1 N4 DDR_D5 ddr_d5 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
T2 P3 DDR_D6 ddr_d6 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
R3 P4 DDR_D7 ddr_d7 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
K2 J1 DDR_D8 ddr_d8 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
K1 K1 DDR_D9 ddr_d9 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
M3 K2 DDR_D10 ddr_d10 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
M4 K3 DDR_D11 ddr_d11 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
M2 K4 DDR_D12 ddr_d12 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
M1 L3 DDR_D13 ddr_d13 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
N2 L4 DDR_D14 ddr_d14 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
N1 M1 DDR_D15 ddr_d15 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
N3 M2 DDR_DQM0 ddr_dqm0 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
K3 J2 DDR_DQM1 ddr_dqm1 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
R1 P1 DDR_DQS0 ddr_dqs0 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
L1 L1 DDR_DQS1 ddr_dqs1 0 I/O L Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
R2 P2 DDR_DQSn0 ddr_dqsn0 0 I/O H Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
L2 L2 DDR_DQSn1 ddr_dqsn1 0 I/O H Z 0 VDDS_DDR / VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
G1 G1 DDR_ODT ddr_odt 0 O L 0 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
F2 G4 DDR_RASn ddr_rasn 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
G2 G2 DDR_RESETn ddr_resetn 0 O L 0 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
H4 J4 DDR_VREF ddr_vref 0 A (18) NA NA NA VDDS_DDR / VDDS_DDR NA NA NA Analog
J1 J3 DDR_VTP ddr_vtp 0 I (19) NA NA NA VDDS_DDR / VDDS_DDR NA NA NA Analog
A4 B2 DDR_WEn ddr_wen 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
E18 C18 ECAP0_IN_PWM0_OUT eCAP0_in_PWM0_out 0 I/O Z L 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
uart3_txd 1 O
spi1_cs1 2 I/O
pr1_ecap0_ecap_capin_apwm_o 3 I/O
spi1_sclk 4 I/O
mmc0_sdwp 5 I
xdma_event_intr2 6 I
gpio0_7 7 I/O
A15 C14 EMU0 EMU0 0 I/O H H 0 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpio3_7 7 I/O
D14 B14 EMU1 EMU1 0 I/O H H 0 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpio3_8 7 I/O
C17 B18 EXTINTn nNMI 0 I Z H 0 VDDSHV6 / VDDSHV6 Yes NA PU/PD LVCMOS
B5 C5 EXT_WAKEUP EXT_WAKEUP 0 I L Z 0 VDDS_RTC / VDDS_RTC Yes NA NA LVCMOS
NA R13 GPMC_A0 gpmc_a0 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_txen 1 O
rgmii2_tctl 2 O
rmii2_txen 3 O
gpmc_a16 4 O
pr1_mii_mt1_clk 5 I
ehrpwm1_tripzone_input 6 I
gpio1_16 7 I/O
NA V14 GPMC_A1 gpmc_a1 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_rxdv 1 I
rgmii2_rctl 2 I
mmc2_dat0 3 I/O
gpmc_a17 4 O
pr1_mii1_txd3 5 O
ehrpwm0_synco 6 O
gpio1_17 7 I/O
NA U14 GPMC_A2 gpmc_a2 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_txd3 1 O
rgmii2_td3 2 O
mmc2_dat1 3 I/O
gpmc_a18 4 O
pr1_mii1_txd2 5 O
ehrpwm1A 6 O
gpio1_18 7 I/O
NA T14 GPMC_A3 gpmc_a3 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_txd2 1 O
rgmii2_td2 2 O
mmc2_dat2 3 I/O
gpmc_a19 4 O
pr1_mii1_txd1 5 O
ehrpwm1B 6 O
gpio1_19 7 I/O
NA R14 GPMC_A4 gpmc_a4 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_txd1 1 O
rgmii2_td1 2 O
rmii2_txd1 3 O
gpmc_a20 4 O
pr1_mii1_txd0 5 O
eQEP1A_in 6 I
gpio1_20 7 I/O
NA V15 GPMC_A5 gpmc_a5 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_txd0 1 O
rgmii2_td0 2 O
rmii2_txd0 3 O
gpmc_a21 4 O
pr1_mii1_rxd3 5 I
eQEP1B_in 6 I
gpio1_21 7 I/O
NA U15 GPMC_A6 gpmc_a6 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_txclk 1 I
rgmii2_tclk 2 O
mmc2_dat4 3 I/O
gpmc_a22 4 O
pr1_mii1_rxd2 5 I
eQEP1_index 6 I/O
gpio1_22 7 I/O
NA T15 GPMC_A7 gpmc_a7 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_rxclk 1 I
rgmii2_rclk 2 I
mmc2_dat5 3 I/O
gpmc_a23 4 O
pr1_mii1_rxd1 5 I
eQEP1_strobe 6 I/O
gpio1_23 7 I/O
NA V16 GPMC_A8 gpmc_a8 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_rxd3 1 I
rgmii2_rd3 2 I
mmc2_dat6 3 I/O
gpmc_a24 4 O
pr1_mii1_rxd0 5 I
mcasp0_aclkx 6 I/O
gpio1_24 7 I/O
NA U16 GPMC_A9 (10) gpmc_a9 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_rxd2 1 I
rgmii2_rd2 2 I
mmc2_dat7 / rmii2_crs_dv 3 I/O
gpmc_a25 4 O
pr1_mii_mr1_clk 5 I
mcasp0_fsx 6 I/O
gpio1_25 7 I/O
NA T16 GPMC_A10 gpmc_a10 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_rxd1 1 I
rgmii2_rd1 2 I
rmii2_rxd1 3 I
gpmc_a26 4 O
pr1_mii1_rxdv 5 I
mcasp0_axr0 6 I/O
gpio1_26 7 I/O
NA V17 GPMC_A11 gpmc_a11 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_rxd0 1 I
rgmii2_rd0 2 I
rmii2_rxd0 3 I
gpmc_a27 4 O
pr1_mii1_rxer 5 I
mcasp0_axr1 6 I/O
gpio1_27 7 I/O
W10 U7 GPMC_AD0 gpmc_ad0 0 I/O L L 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat0 1 I/O
gpio1_0 7 I/O
V9 V7 GPMC_AD1 gpmc_ad1 0 I/O L L 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat1 1 I/O
gpio1_1 7 I/O
V12 R8 GPMC_AD2 gpmc_ad2 0 I/O L L 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat2 1 I/O
gpio1_2 7 I/O
W13 T8 GPMC_AD3 gpmc_ad3 0 I/O L L 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat3 1 I/O
gpio1_3 7 I/O
V13 U8 GPMC_AD4 gpmc_ad4 0 I/O L L 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat4 1 I/O
gpio1_4 7 I/O
W14 V8 GPMC_AD5 gpmc_ad5 0 I/O L L 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat5 1 I/O
gpio1_5 7 I/O
U14 R9 GPMC_AD6 gpmc_ad6 0 I/O L L 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat6 1 I/O
gpio1_6 7 I/O
W15 T9 GPMC_AD7 gpmc_ad7 0 I/O L L 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat7 1 I/O
gpio1_7 7 I/O
V15 U10 GPMC_AD8 gpmc_ad8 0 I/O L L 7 VDDSHV1 / VDDSHV2 Yes 6 PU/PD LVCMOS
lcd_data23 1 O
mmc1_dat0 2 I/O
mmc2_dat4 3 I/O
ehrpwm2A 4 O
pr1_mii_mt0_clk 5 I
gpio0_22 7 I/O
W16 T10 GPMC_AD9 gpmc_ad9 0 I/O L L 7 VDDSHV1 / VDDSHV2 Yes 6 PU/PD LVCMOS
lcd_data22 1 O
mmc1_dat1 2 I/O
mmc2_dat5 3 I/O
ehrpwm2B 4 O
pr1_mii0_col 5 I
gpio0_23 7 I/O
T12 T11 GPMC_AD10 gpmc_ad10 0 I/O L L 7 VDDSHV1 / VDDSHV2 Yes 6 PU/PD LVCMOS
lcd_data21 1 O
mmc1_dat2 2 I/O
mmc2_dat6 3 I/O
ehrpwm2_tripzone_input 4 I
pr1_mii0_txen 5 O
gpio0_26 7 I/O
U12 U12 GPMC_AD11 gpmc_ad11 0 I/O L L 7 VDDSHV1 / VDDSHV2 Yes 6 PU/PD LVCMOS
lcd_data20 1 O
mmc1_dat3 2 I/O
mmc2_dat7 3 I/O
ehrpwm0_synco 4 O
pr1_mii0_txd3 5 O
gpio0_27 7 I/O
U13 T12 GPMC_AD12 gpmc_ad12 0 I/O L L 7 VDDSHV1 / VDDSHV2 Yes 6 PU/PD LVCMOS
lcd_data19 1 O
mmc1_dat4 2 I/O
mmc2_dat0 3 I/O
eQEP2A_in 4 I
pr1_mii0_txd2 5 O
pr1_pru0_pru_r30_14 6 O
gpio1_12 7 I/O
T13 R12 GPMC_AD13 gpmc_ad13 0 I/O L L 7 VDDSHV1 / VDDSHV2 Yes 6 PU/PD LVCMOS
lcd_data18 1 O
mmc1_dat5 2 I/O
mmc2_dat1 3 I/O
eQEP2B_in 4 I
pr1_mii0_txd1 5 O
pr1_pru0_pru_r30_15 6 O
gpio1_13 7 I/O
W17 V13 GPMC_AD14 gpmc_ad14 0 I/O L L 7 VDDSHV1 / VDDSHV2 Yes 6 PU/PD LVCMOS
lcd_data17 1 O
mmc1_dat6 2 I/O
mmc2_dat2 3 I/O
eQEP2_index 4 I/O
pr1_mii0_txd0 5 O
pr1_pru0_pru_r31_14 6 I
gpio1_14 7 I/O
V17 U13 GPMC_AD15 gpmc_ad15 0 I/O L L 7 VDDSHV1 / VDDSHV2 Yes 6 PU/PD LVCMOS
lcd_data16 1 O
mmc1_dat7 2 I/O
mmc2_dat3 3 I/O
eQEP2_strobe 4 I/O
pr1_ecap0_ecap_capin_apwm_o 5 I/O
pr1_pru0_pru_r31_15 6 I
gpio1_15 7 I/O
V10 R7 GPMC_ADVn_ALE gpmc_advn_ale 0 O H H 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
timer4 2 I/O
gpio2_2 7 I/O
V8 T6 GPMC_BEn0_CLE gpmc_be0n_cle 0 O H H 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
timer5 2 I/O
gpio2_5 7 I/O
V18 U18 GPMC_BEn1 gpmc_be1n 0 O H H 7 VDDSHV1 / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_col 1 I
gpmc_csn6 2 O
mmc2_dat3 3 I/O
gpmc_dir 4 O
pr1_mii1_rxlink 5 I
mcasp0_aclkr 6 I/O
gpio1_28 7 I/O
V16 V12 GPMC_CLK gpmc_clk 0 I/O L L 7 VDDSHV1 / VDDSHV2 Yes 6 PU/PD LVCMOS
lcd_memory_clk 1 O
gpmc_wait1 2 I
mmc2_clk 3 I/O
pr1_mii1_crs 4 I
pr1_mdio_mdclk 5 O
mcasp0_fsr 6 I/O
gpio2_1 7 I/O
W8 V6 GPMC_CSn0 gpmc_csn0 0 O H H 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
gpio1_29 7 I/O
V14 U9 GPMC_CSn1 gpmc_csn1 0 O H H 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
gpmc_clk 1 I/O
mmc1_clk 2 I/O
pr1_edio_data_in6 3 I
pr1_edio_data_out6 4 O
pr1_pru1_pru_r30_12 5 O
pr1_pru1_pru_r31_12 6 I
gpio1_30 7 I/O
U15 V9 GPMC_CSn2 gpmc_csn2 0 O H H 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
gpmc_be1n 1 O
mmc1_cmd 2 I/O
pr1_edio_data_in7 3 I
pr1_edio_data_out7 4 O
pr1_pru1_pru_r30_13 5 O
pr1_pru1_pru_r31_13 6 I
gpio1_31 7 I/O
U17 T13 GPMC_CSn3 (6) gpmc_csn3 0 O H H 7 VDDSHV1 / VDDSHV2 Yes 6 PU/PD LVCMOS
gpmc_a3 1 O
rmii2_crs_dv 2 I
mmc2_cmd 3 I/O
pr1_mii0_crs 4 I
pr1_mdio_data 5 I/O
EMU4 6 I/O
gpio2_0 7 I/O
W9 T7 GPMC_OEn_REn gpmc_oen_ren 0 O H H 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
timer7 2 I/O
gpio2_3 7 I/O
R15 T17 GPMC_WAIT0 gpmc_wait0 0 I H H 7 VDDSHV1 / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_crs 1 I
gpmc_csn4 2 O
rmii2_crs_dv 3 I
mmc1_sdcd 4 I
pr1_mii1_col 5 I
uart4_rxd 6 I
gpio0_30 7 I/O
U8 U6 GPMC_WEn gpmc_wen 0 O H H 7 VDDSHV1 / VDDSHV1 Yes 6 PU/PD LVCMOS
timer6 2 I/O
gpio2_4 7 I/O
W18 U17 GPMC_WPn gpmc_wpn 0 O H H 7 VDDSHV1 / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_rxerr 1 I
gpmc_csn5 2 O
rmii2_rxerr 3 I
mmc2_sdcd 4 I
pr1_mii1_txen 5 O
uart4_txd 6 O
gpio0_31 7 I/O
C18 C17 I2C0_SDA I2C0_SDA 0 I/OD Z H 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
timer4 1 I/O
uart2_ctsn 2 I
eCAP2_in_PWM2_out 3 I/O
gpio3_5 7 I/O
B19 C16 I2C0_SCL I2C0_SCL 0 I/OD Z H 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
timer7 1 I/O
uart2_rtsn 2 O
eCAP1_in_PWM1_out 3 I/O
gpio3_6 7 I/O
W7 R6 LCD_AC_BIAS_EN lcd_ac_bias_en 0 O Z L 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a11 1 O
pr1_mii1_crs 2 I
pr1_edio_data_in5 3 I
pr1_edio_data_out5 4 O
pr1_pru1_pru_r30_11 5 O
pr1_pru1_pru_r31_11 6 I
gpio2_25 7 I/O
U1 R1 LCD_DATA0 (5) lcd_data0 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a0 1 O
pr1_mii_mt0_clk 2 I
ehrpwm2A 3 O
pr1_pru1_pru_r30_0 5 O
pr1_pru1_pru_r31_0 6 I
gpio2_6 7 I/O
U2 R2 LCD_DATA1 (5) lcd_data1 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a1 1 O
pr1_mii0_txen 2 O
ehrpwm2B 3 O
pr1_pru1_pru_r30_1 5 O
pr1_pru1_pru_r31_1 6 I
gpio2_7 7 I/O
V1 R3 LCD_DATA2 (5) lcd_data2 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a2 1 O
pr1_mii0_txd3 2 O
ehrpwm2_tripzone_input 3 I
pr1_pru1_pru_r30_2 5 O
pr1_pru1_pru_r31_2 6 I
gpio2_8 7 I/O
V2 R4 LCD_DATA3 (5) lcd_data3 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a3 1 O
pr1_mii0_txd2 2 O
ehrpwm0_synco 3 O
pr1_pru1_pru_r30_3 5 O
pr1_pru1_pru_r31_3 6 I
gpio2_9 7 I/O
W2 T1 LCD_DATA4 (5) lcd_data4 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a4 1 O
pr1_mii0_txd1 2 O
eQEP2A_in 3 I
pr1_pru1_pru_r30_4 5 O
pr1_pru1_pru_r31_4 6 I
gpio2_10 7 I/O
W3 T2 LCD_DATA5 (5) lcd_data5 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a5 1 O
pr1_mii0_txd0 2 O
eQEP2B_in 3 I
pr1_pru1_pru_r30_5 5 O
pr1_pru1_pru_r31_5 6 I
gpio2_11 7 I/O
V3 T3 LCD_DATA6 (5) lcd_data6 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a6 1 O
pr1_edio_data_in6 2 I
eQEP2_index 3 I/O
pr1_edio_data_out6 4 O
pr1_pru1_pru_r30_6 5 O
pr1_pru1_pru_r31_6 6 I
gpio2_12 7 I/O
U3 T4 LCD_DATA7 (5) lcd_data7 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a7 1 O
pr1_edio_data_in7 2 I
eQEP2_strobe 3 I/O
pr1_edio_data_out7 4 O
pr1_pru1_pru_r30_7 5 O
pr1_pru1_pru_r31_7 6 I
gpio2_13 7 I/O
V4 U1 LCD_DATA8 (5) lcd_data8 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a12 1 O
ehrpwm1_tripzone_input 2 I
mcasp0_aclkx 3 I/O
uart5_txd 4 O
pr1_mii0_rxd3 5 I
uart2_ctsn 6 I
gpio2_14 7 I/O
W4 U2 LCD_DATA9 (5) lcd_data9 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a13 1 O
ehrpwm0_synco 2 O
mcasp0_fsx 3 I/O
uart5_rxd 4 I
pr1_mii0_rxd2 5 I
uart2_rtsn 6 O
gpio2_15 7 I/O
U5 U3 LCD_DATA10 (5) lcd_data10 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a14 1 O
ehrpwm1A 2 O
mcasp0_axr0 3 I/O
pr1_mii0_rxd1 5 I
uart3_ctsn 6 I
gpio2_16 7 I/O
V5 U4 LCD_DATA11 (5) lcd_data11 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a15 1 O
ehrpwm1B 2 O
mcasp0_ahclkr 3 I/O
mcasp0_axr2 4 I/O
pr1_mii0_rxd0 5 I
uart3_rtsn 6 O
gpio2_17 7 I/O
V6 V2 LCD_DATA12 (5) lcd_data12 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a16 1 O
eQEP1A_in 2 I
mcasp0_aclkr 3 I/O
mcasp0_axr2 4 I/O
pr1_mii0_rxlink 5 I
uart4_ctsn 6 I
gpio0_8 7 I/O
U6 V3 LCD_DATA13 (5) lcd_data13 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a17 1 O
eQEP1B_in 2 I
mcasp0_fsr 3 I/O
mcasp0_axr3 4 I/O
pr1_mii0_rxer 5 I
uart4_rtsn 6 O
gpio0_9 7 I/O
W6 V4 LCD_DATA14 (5) lcd_data14 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a18 1 O
eQEP1_index 2 I/O
mcasp0_axr1 3 I/O
uart5_rxd 4 I
pr1_mii_mr0_clk 5 I
uart5_ctsn 6 I
gpio0_10 7 I/O
V7 T5 LCD_DATA15 (5) lcd_data15 0 I/O Z Z 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a19 1 O
eQEP1_strobe 2 I/O
mcasp0_ahclkx 3 I/O
mcasp0_axr3 4 I/O
pr1_mii0_rxdv 5 I
uart5_rtsn 6 O
gpio0_11 7 I/O
T7 R5 LCD_HSYNC (7) lcd_hsync 0 O Z L 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a9 1 O
gpmc_a2 2 O
pr1_edio_data_in3 3 I
pr1_edio_data_out3 4 O
pr1_pru1_pru_r30_9 5 O
pr1_pru1_pru_r31_9 6 I
gpio2_23 7 I/O
W5 V5 LCD_PCLK lcd_pclk 0 O Z L 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a10 1 O
pr1_mii0_crs 2 I
pr1_edio_data_in4 3 I
pr1_edio_data_out4 4 O
pr1_pru1_pru_r30_10 5 O
pr1_pru1_pru_r31_10 6 I
gpio2_24 7 I/O
U7 U5 LCD_VSYNC (7) lcd_vsync 0 O Z L 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a8 1 O
gpmc_a1 2 O
pr1_edio_data_in2 3 I
pr1_edio_data_out2 4 O
pr1_pru1_pru_r30_8 5 O
pr1_pru1_pru_r31_8 6 I
gpio2_22 7 I/O
NA B13 MCASP0_FSX mcasp0_fsx 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0B 1 O
spi1_d0 3 I/O
mmc1_sdcd 4 I
pr1_pru0_pru_r30_1 5 O
pr1_pru0_pru_r31_1 6 I
gpio3_15 7 I/O
NA B12 MCASP0_ACLKR mcasp0_aclkr 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP0A_in 1 I
mcasp0_axr2 2 I/O
mcasp1_aclkx 3 I/O
mmc0_sdwp 4 I
pr1_pru0_pru_r30_4 5 O
pr1_pru0_pru_r31_4 6 I
gpio3_18 7 I/O
NA C12 MCASP0_AHCLKR mcasp0_ahclkr 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0_synci 1 I
mcasp0_axr2 2 I/O
spi1_cs0 3 I/O
eCAP2_in_PWM2_out 4 I/O
pr1_pru0_pru_r30_3 5 O
pr1_pru0_pru_r31_3 6 I
gpio3_17 7 I/O
NA A14 MCASP0_AHCLKX mcasp0_ahclkx 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP0_strobe 1 I/O
mcasp0_axr3 2 I/O
mcasp1_axr1 3 I/O
EMU4 4 I/O
pr1_pru0_pru_r30_7 5 O
pr1_pru0_pru_r31_7 6 I
gpio3_21 7 I/O
NA A13 MCASP0_ACLKX mcasp0_aclkx 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0A 1 O
spi1_sclk 3 I/O
mmc0_sdcd 4 I
pr1_pru0_pru_r30_0 5 O
pr1_pru0_pru_r31_0 6 I
gpio3_14 7 I/O
NA C13 MCASP0_FSR mcasp0_fsr 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP0B_in 1 I
mcasp0_axr3 2 I/O
mcasp1_fsx 3 I/O
EMU2 4 I/O
pr1_pru0_pru_r30_5 5 O
pr1_pru0_pru_r31_5 6 I
gpio3_19 7 I/O
NA D12 MCASP0_AXR0 mcasp0_axr0 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0_tripzone_input 1 I
spi1_d1 3 I/O
mmc2_sdcd 4 I
pr1_pru0_pru_r30_2 5 O
pr1_pru0_pru_r31_2 6 I
gpio3_16 7 I/O
NA D13 MCASP0_AXR1 mcasp0_axr1 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP0_index 1 I/O
mcasp1_axr0 3 I/O
EMU3 4 I/O
pr1_pru0_pru_r30_6 5 O
pr1_pru0_pru_r31_6 6 I
gpio3_20 7 I/O
R19 M18 MDC mdio_clk 0 O H H 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
timer5 1 I/O
uart5_txd 2 O
uart3_rtsn 3 O
mmc0_sdwp 4 I
mmc1_clk 5 I/O
mmc2_clk 6 I/O
gpio0_1 7 I/O
P17 M17 MDIO mdio_data 0 I/O H H 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
timer6 1 I/O
uart5_rxd 2 I
uart3_ctsn 3 I
mmc0_sdcd 4 I
mmc1_cmd 5 I/O
mmc2_cmd 6 I/O
gpio0_0 7 I/O
L19 J17 MII1_RX_DV gmii1_rxdv 0 I L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
lcd_memory_clk 1 O
rgmii1_rctl 2 I
uart5_txd 3 O
mcasp1_aclkx 4 I/O
mmc2_dat0 5 I/O
mcasp0_aclkr 6 I/O
gpio3_4 7 I/O
K17 J16 MII1_TX_EN gmii1_txen 0 O L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_txen 1 O
rgmii1_tctl 2 O
timer4 3 I/O
mcasp1_axr0 4 I/O
eQEP0_index 5 I/O
mmc2_cmd 6 I/O
gpio3_3 7 I/O
K19 J15 MII1_RX_ER gmii1_rxerr 0 I L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_rxerr 1 I
spi1_d1 2 I/O
I2C1_SCL 3 I/OD
mcasp1_fsx 4 I/O
uart5_rtsn 5 O
uart2_txd 6 O
gpio3_2 7 I/O
M19 L18 MII1_RX_CLK gmii1_rxclk 0 I L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
uart2_txd 1 O
rgmii1_rclk 2 I
mmc0_dat6 3 I/O
mmc1_dat1 4 I/O
uart1_dsrn 5 I
mcasp0_fsx 6 I/O
gpio3_10 7 I/O
N19 K18 MII1_TX_CLK gmii1_txclk 0 I L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
uart2_rxd 1 I
rgmii1_tclk 2 O
mmc0_dat7 3 I/O
mmc1_dat0 4 I/O
uart1_dcdn 5 I
mcasp0_aclkx 6 I/O
gpio3_9 7 I/O
J19 H16 MII1_COL gmii1_col 0 I L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
rmii2_refclk 1 I/O
spi1_sclk 2 I/O
uart5_rxd 3 I
mcasp1_axr2 4 I/O
mmc2_dat3 5 I/O
mcasp0_axr2 6 I/O
gpio3_0 7 I/O
J18 H17 MII1_CRS gmii1_crs 0 I L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_crs_dv 1 I
spi1_d0 2 I/O
I2C1_SDA 3 I/OD
mcasp1_aclkx 4 I/O
uart5_ctsn 5 I
uart2_rxd 6 I
gpio3_1 7 I/O
P18 M16 MII1_RXD0 gmii1_rxd0 0 I L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_rxd0 1 I
rgmii1_rd0 2 I
mcasp1_ahclkx 3 I/O
mcasp1_ahclkr 4 I/O
mcasp1_aclkr 5 I/O
mcasp0_axr3 6 I/O
gpio2_21 7 I/O
P19 L15 MII1_RXD1 gmii1_rxd1 0 I L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_rxd1 1 I
rgmii1_rd1 2 I
mcasp1_axr3 3 I/O
mcasp1_fsr 4 I/O
eQEP0_strobe 5 I/O
mmc2_clk 6 I/O
gpio2_20 7 I/O
N16 L16 MII1_RXD2 gmii1_rxd2 0 I L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
uart3_txd 1 O
rgmii1_rd2 2 I
mmc0_dat4 3 I/O
mmc1_dat3 4 I/O
uart1_rin 5 I
mcasp0_axr1 6 I/O
gpio2_19 7 I/O
N17 L17 MII1_RXD3 gmii1_rxd3 0 I L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
uart3_rxd 1 I
rgmii1_rd3 2 I
mmc0_dat5 3 I/O
mmc1_dat2 4 I/O
uart1_dtrn 5 O
mcasp0_axr0 6 I/O
gpio2_18 7 I/O
L18 K17 MII1_TXD0 gmii1_txd0 0 O L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_txd0 1 O
rgmii1_td0 2 O
mcasp1_axr2 3 I/O
mcasp1_aclkr 4 I/O
eQEP0B_in 5 I
mmc1_clk 6 I/O
gpio0_28 7 I/O
M18 K16 MII1_TXD1 gmii1_txd1 0 O L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_txd1 1 O
rgmii1_td1 2 O
mcasp1_fsr 3 I/O
mcasp1_axr1 4 I/O
eQEP0A_in 5 I
mmc1_cmd 6 I/O
gpio0_21 7 I/O
N18 K15 MII1_TXD2 gmii1_txd2 0 O L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
dcan0_rx 1 I
rgmii1_td2 2 O
uart4_txd 3 O
mcasp1_axr0 4 I/O
mmc2_dat2 5 I/O
mcasp0_ahclkx 6 I/O
gpio0_17 7 I/O
M17 J18 MII1_TXD3 gmii1_txd3 0 O L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
dcan0_tx 1 O
rgmii1_td3 2 O
uart4_rxd 3 I
mcasp1_fsx 4 I/O
mmc2_dat1 5 I/O
mcasp0_fsr 6 I/O
gpio0_16 7 I/O
G17 G18 MMC0_CMD mmc0_cmd 0 I/O H H 7 VDDSHV4 / VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a25 1 O
uart3_rtsn 2 O
uart2_txd 3 O
dcan1_rx 4 I
pr1_pru0_pru_r30_13 5 O
pr1_pru0_pru_r31_13 6 I
gpio2_31 7 I/O
G19 G17 MMC0_CLK mmc0_clk 0 I/O H H 7 VDDSHV4 / VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a24 1 O
uart3_ctsn 2 I
uart2_rxd 3 I
dcan1_tx 4 O
pr1_pru0_pru_r30_12 5 O
pr1_pru0_pru_r31_12 6 I
gpio2_30 7 I/O
G18 G16 MMC0_DAT0 mmc0_dat0 0 I/O H H 7 VDDSHV4 / VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a23 1 O
uart5_rtsn 2 O
uart3_txd 3 O
uart1_rin 4 I
pr1_pru0_pru_r30_11 5 O
pr1_pru0_pru_r31_11 6 I
gpio2_29 7 I/O
H17 G15 MMC0_DAT1 mmc0_dat1 0 I/O H H 7 VDDSHV4 / VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a22 1 O
uart5_ctsn 2 I
uart3_rxd 3 I
uart1_dtrn 4 O
pr1_pru0_pru_r30_10 5 O
pr1_pru0_pru_r31_10 6 I
gpio2_28 7 I/O
H18 F18 MMC0_DAT2 mmc0_dat2 0 I/O H H 7 VDDSHV4 / VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a21 1 O
uart4_rtsn 2 O
timer6 3 I/O
uart1_dsrn 4 I
pr1_pru0_pru_r30_9 5 O
pr1_pru0_pru_r31_9 6 I
gpio2_27 7 I/O
H19 F17 MMC0_DAT3 mmc0_dat3 0 I/O H H 7 VDDSHV4 / VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a20 1 O
uart4_ctsn 2 I
timer5 3 I/O
uart1_dcdn 4 I
pr1_pru0_pru_r30_8 5 O
pr1_pru0_pru_r31_8 6 I
gpio2_26 7 I/O
C7 C6 PMIC_POWER_EN PMIC_POWER_EN 0 O H 1 0 VDDS_RTC / VDDS_RTC NA 6 NA LVCMOS
E15 B15 PWRONRSTn porz 0 I Z Z 0 VDDSHV6 / VDDSHV6 (12) Yes NA NA LVCMOS
B6 A3 RESERVED (3) testout 0 O NA NA NA VDDSHV6 / VDDSHV6 NA NA NA Analog
K18 H18 RMII1_REF_CLK rmii1_refclk 0 I/O L L 7 VDDSHV5 / VDDSHV5 Yes 6 PU/PD LVCMOS
xdma_event_intr2 1 I
spi1_cs0 2 I/O
uart5_txd 3 O
mcasp1_axr3 4 I/O
mmc0_pow 5 O
mcasp1_ahclkx 6 I/O
gpio0_29 7 I/O
A7 B4 RTC_KALDO_ENn ENZ_KALDO_1P8V 0 I Z Z 0 VDDS_RTC / VDDS_RTC NA NA NA Analog
B7 B5 RTC_PWRONRSTn RTC_PORz 0 I Z Z 0 VDDS_RTC / VDDS_RTC Yes NA NA LVCMOS
A6 A6 RTC_XTALIN OSC1_IN 0 I H H 0 VDDS_RTC / VDDS_RTC Yes NA PU (1) LVCMOS
A5 A4 RTC_XTALOUT OSC1_OUT 0 O Z (23) Z (23) 0 VDDS_RTC / VDDS_RTC NA NA (15) NA LVCMOS
A18 A17 SPI0_SCLK spi0_sclk 0 I/O Z H 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
uart2_rxd 1 I
I2C2_SDA 2 I/OD
ehrpwm0A 3 O
pr1_uart0_cts_n 4 I
pr1_edio_sof 5 O
EMU2 6 I/O
gpio0_2 7 I/O
A17 A16 SPI0_CS0 spi0_cs0 0 I/O Z H 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
mmc2_sdwp 1 I
I2C1_SCL 2 I/OD
ehrpwm0_synci 3 I
pr1_uart0_txd 4 O
pr1_edio_data_in1 5 I
pr1_edio_data_out1 6 O
gpio0_5 7 I/O
B16 C15 SPI0_CS1 spi0_cs1 0 I/O Z H 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
uart3_rxd 1 I
eCAP1_in_PWM1_out 2 I/O
mmc0_pow 3 O
xdma_event_intr2 4 I
mmc0_sdcd 5 I
EMU4 6 I/O
gpio0_6 7 I/O
B18 B17 SPI0_D0 spi0_d0 0 I/O Z H 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
uart2_txd 1 O
I2C2_SCL 2 I/OD
ehrpwm0B 3 O
pr1_uart0_rts_n 4 O
pr1_edio_latch_in 5 I
EMU3 6 I/O
gpio0_3 7 I/O
B17 B16 SPI0_D1 spi0_d1 0 I/O Z H 7 VDDSHV6 / VDDSHV6 Yes 6 PU/PD LVCMOS
mmc1_sdwp 1 I
I2C1_SDA 2 I/OD
ehrpwm0_tripzone_input 3 I
pr1_uart0_rxd 4 I
pr1_edio_data_in0 5 I
pr1_edio_data_out0 6 O
gpio0_4 7 I/O
B14 A12 TCK TCK 0 I H H 0 VDDSHV6 / VDDSHV6 Yes NA PU/PD LVCMOS
B13 B11 TDI TDI 0 I H H 0 VDDSHV6 / VDDSHV6 Yes NA PU/PD LVCMOS
A14 A11 TDO TDO 0 O H H 0 VDDSHV6 / VDDSHV6 NA 4 PU/PD LVCMOS
C14 C11 TMS TMS 0 I H H 0 VDDSHV6 / VDDSHV6 Yes NA PU/PD LVCMOS
A13 B10 TRSTn nTRST 0 I L L 0 VDDSHV6 / VDDSHV6 Yes NA PU/PD LVCMOS
F17 E16 UART0_TXD uart0_txd 0 O Z H 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
spi1_cs1 1 I/O
dcan0_rx 2 I
I2C2_SCL 3 I/OD
eCAP1_in_PWM1_out 4 I/O
pr1_pru1_pru_r30_15 5 O
pr1_pru1_pru_r31_15 6 I
gpio1_11 7 I/O
F19 E18 UART0_CTSn uart0_ctsn 0 I Z H 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
uart4_rxd 1 I
dcan1_tx 2 O
I2C1_SDA 3 I/OD
spi1_d0 4 I/O
timer7 5 I/O
pr1_edc_sync0_out 6 O
gpio1_8 7 I/O
E19 E15 UART0_RXD uart0_rxd 0 I Z H 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
spi1_cs0 1 I/O
dcan0_tx 2 O
I2C2_SDA 3 I/OD
eCAP2_in_PWM2_out 4 I/O
pr1_pru1_pru_r30_14 5 O
pr1_pru1_pru_r31_14 6 I
gpio1_10 7 I/O
F18 E17 UART0_RTSn uart0_rtsn 0 O Z H 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
uart4_txd 1 O
dcan1_rx 2 I
I2C1_SCL 3 I/OD
spi1_d1 4 I/O
spi1_cs0 5 I/O
pr1_edc_sync1_out 6 O
gpio1_9 7 I/O
C19 D15 UART1_TXD uart1_txd 0 O Z H 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
mmc2_sdwp 1 I
dcan1_rx 2 I
I2C1_SCL 3 I/OD
pr1_uart0_txd 5 O
pr1_pru0_pru_r31_16 6 I
gpio0_15 7 I/O
D18 D16 UART1_RXD uart1_rxd 0 I Z H 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
mmc1_sdwp 1 I
dcan1_tx 2 O
I2C1_SDA 3 I/OD
pr1_uart0_rxd 5 I
pr1_pru1_pru_r31_16 6 I
gpio0_14 7 I/O
D19 D17 UART1_RTSn uart1_rtsn 0 O Z H 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
timer5 1 I/O
dcan0_rx 2 I
I2C2_SCL 3 I/OD
spi1_cs1 4 I/O
pr1_uart0_rts_n 5 O
pr1_edc_latch1_in 6 I
gpio0_13 7 I/O
E17 D18 UART1_CTSn uart1_ctsn 0 I Z H 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
timer6 1 I/O
dcan0_tx 2 O
I2C2_SDA 3 I/OD
spi1_cs0 4 I/O
pr1_uart0_cts_n 5 I
pr1_edc_latch0_in 6 I
gpio0_12 7 I/O
T18 M15 USB0_CE USB0_CE 0 A Z Z 0 VDDA*_USB0 / VDDA*_USB0 (26) NA NA NA Analog
T19 P15 USB0_VBUS USB0_VBUS 0 A Z Z 0 VDDA*_USB0 / VDDA*_USB0 (26) NA NA NA Analog
U18 N18 USB0_DM USB0_DM 0 A Z Z 0 (13) VDDA*_USB0 / VDDA*_USB0 (26) Yes (16) 8 (16) NA Analog
G16 F16 USB0_DRVVBUS USB0_DRVVBUS 0 O L 0(PD) 0 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
gpio0_18 7 I/O
V19 P16 USB0_ID USB0_ID 0 A Z Z 0 VDDA*_USB0 / VDDA*_USB0 (26) NA NA NA Analog
U19 N17 USB0_DP USB0_DP 0 A Z Z 0 (13) VDDA*_USB0 / VDDA*_USB0 (26) Yes (16) 8 (16) NA Analog
NA P18 USB1_CE USB1_CE 0 A Z Z 0 NA / VDDA*_USB1 (27) NA NA NA Analog
NA P17 USB1_ID USB1_ID 0 A Z Z 0 NA / VDDA*_USB1 (27) NA NA NA Analog
NA T18 USB1_VBUS USB1_VBUS 0 A Z Z 0 NA / VDDA*_USB1 (27) NA NA NA Analog
NA R17 USB1_DP USB1_DP 0 A Z Z 0 (14) NA / VDDA*_USB1 (27) Yes (17) 8 (17) NA Analog
NA F15 USB1_DRVVBUS USB1_DRVVBUS 0 O L 0(PD) 0 NA / VDDSHV6 Yes 4 PU/PD LVCMOS
gpio3_13 7 I/O
NA R18 USB1_DM USB1_DM 0 A Z Z 0 (14) NA / VDDA*_USB1 (27) Yes (17) 8 (17) NA Analog
R17 N16 VDDA1P8V_USB0 VDDA1P8V_USB0 NA PWR
NA R16 VDDA1P8V_USB1 VDDA1P8V_USB1 NA PWR
R18 N15 VDDA3P3V_USB0 VDDA3P3V_USB0 NA PWR
NA R15 VDDA3P3V_USB1 VDDA3P3V_USB1 NA PWR
D7 D8 VDDA_ADC VDDA_ADC NA PWR
D12, F16, M16, T6, T14 E6, E14, F9, K13, N6, P9, P14 VDDS VDDS NA PWR
R8, R9, R11, R12, R13 P7, P8 VDDSHV1 VDDSHV1 NA PWR
NA P10, P11 VDDSHV2 VDDSHV2 NA PWR
NA P12, P13 VDDSHV3 VDDSHV3 NA PWR
G15, H14, H15 H14, J14 VDDSHV4 VDDSHV4 NA PWR
M14, M15, N15 K14, L14 VDDSHV5 VDDSHV5 NA PWR
E11, E12, E13, F14, P6, R7 E10, E11, E12, E13, F14, G14, N5, P5, P6 VDDSHV6 VDDSHV6 NA PWR
G5, H5, H6, K4, K5, M5, M6, N5 E5, F5, G5, H5, J5, K5, L5 VDDS_DDR VDDS_DDR NA PWR
U10 R11 VDDS_OSC VDDS_OSC NA PWR
T8 R10 VDDS_PLL_CORE_LCD VDDS_PLL_CORE_LCD NA PWR
C5 E7 VDDS_PLL_DDR VDDS_PLL_DDR NA PWR
H16 H15 VDDS_PLL_MPU VDDS_PLL_MPU NA PWR
C6 D7 VDDS_RTC VDDS_RTC NA PWR
C10 E9 VDDS_SRAM_CORE_BG VDDS_SRAM_CORE_BG NA PWR
C12 D10 VDDS_SRAM_MPU_BB VDDS_SRAM_MPU_BB NA PWR
F9, F11, G9, G11, H7, H8, H12, H13, J7, J8, J12, J13, K15, K16, L7, L8, L12, L13, M7, M8, M12, M13, N9, N11, P9, P11 F6, F7, G6, G7, G10, H11, J12, K6, K8, K12, L6, L7, L8, L9, M11, M13, N8, N9, N12, N13 VDD_CORE VDD_CORE NA PWR
NA F10, F11, F12, F13, G13, H13, J13 VDD_MPU VDD_MPU (30) NA PWR
NA A2 VDD_MPU_MON VDD_MPU_MON (31) NA A
R5 M5 VPP VPP NA PWR
B9 A9 VREFN VREFN 0 AP Z Z 0 VDDA_ADC / VDDA_ADC NA NA NA Analog
A9 B9 VREFP VREFP 0 AP Z Z 0 VDDA_ADC / VDDA_ADC NA NA NA Analog
A1, A19, D10, E7, E8, E9, E10, F6, F7, F8, F12, F13, G8, G12, H9, H10, H11, J5, J6, J9, J11, J14, J15, K8, K9, K11, K12, L5, L6, L9, L11, L14, L15, M9, M10, M11, N8, N12, P7, P8, P12, P13, P14, R10, T10, W1, W19 A1, A18, F8, G8, G9, G11, G12, H6, H7, H8, H9, H10, H12, J6, J7, J8, J9, J10, J11, K7, K9, K10, K11, L10, L11, L12, L13, M6, M7, M8, M9, M10, M12, N7, N10, N11, V1, V18 VSS VSS NA GND
D8 E8 VSSA_ADC VSSA_ADC NA GND
P16 M14, N14 VSSA_USB VSSA_USB NA GND
V11 V11 VSS_OSC VSS_OSC (28) NA A
NA A5 VSS_RTC VSS_RTC (29) NA A
A16 A10 WARMRSTn nRESETIN_OUT 0 I/OD (8) 0 0(PU) (11) 0 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
C15 A15 XDMA_EVENT_INTR0 xdma_event_intr0 0 I Z (4) (9) VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
timer4 2 I/O
clkout1 3 O
spi1_cs1 4 I/O
pr1_pru1_pru_r31_16 5 I
EMU2 6 I/O
gpio0_19 7 I/O
B15 D14 XDMA_EVENT_INTR1 xdma_event_intr1 0 I Z L 7 VDDSHV6 / VDDSHV6 Yes 4 PU/PD LVCMOS
tclkin 2 I
clkout2 3 O
timer7 4 I/O
pr1_pru0_pru_r31_16 5 I
EMU3 6 I/O
gpio0_20 7 I/O
W11 V10 XTALIN OSC0_IN 0 I Z Z 0 VDDS_OSC / VDDS_OSC Yes NA PD (2) LVCMOS
W12 U11 XTALOUT OSC0_OUT 0 O (24) (24) 0 VDDS_OSC / VDDS_OSC NA NA (15) NA LVCMOS
  1. An internal 10 kohm pullup is turned on when the oscillator is diasabled. The oscillator is disabled by default after power is applied.
  2. An internal 15 kohm pulldown is turned on when the oscillator is disabled. The oscillator is enabled by default after power is applied.
  3. Do not connect anything to this terminal.
  4. If sysboot[5] is low on the rising edge of PWRONRSTn, this terminal has an internal pulldown turned on after reset is released. If sysboot[5] is high on the rising edge or PWRONRSTn, this terminal will initially be driven low after reset is released then it begins to toggle at the same frequency of the XTALIN terminal.
  5. LCD_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs, latched on the rising edge of PWRONRSTn.
  6. Mode1 and Mode2 signal assignments for this terminal are only available with silicon revision 2.0 or newer devices.
  7. Mode2 signal assignment for this terminal is only available with silicon revision 2.0 or newer devices.
  8. Refer to the External Warm Reset section of the AM335x Technical Reference Manual for more information related to the operation of this terminal.
  9. Reset Release Mode = 7 if sysboot[5] is low. Mode = 3 if sysboot[5] is high.
  10. Silicon revision 1.0 devices only provide the MMC2_DAT7 signal when Mode3 is selected. Silicon revision 2.0 and newer devices implement another level of pin multiplexing which provides the original MMC2_DAT7 signal or RMII2_CRS_DV signal when Mode3 is selected. This new level of of pin multiplexing is selected with bit zero of the SMA2 register. For more details refer to Section 1.2 of the AM335x Technical Reference Manual.
  11. The 0(PU) indicates that this terminal is initially low based on the description in the AM335x Technical Reference Manual. However, it is also has a weak internal pullup applied.
  12. The input voltage thresholds for this input are not a function of VDDSHV6. Please refer to the DC Electrical Characteristics section for details related to electrical parameters associated with this input terminal.
  13. The internal USB PHY can be configured to multiplex the UART2_TX or UART2_RX signals to this terminal. For more details refer to USB GPIO Details section of the AM335x Technical Reference Manual.
  14. The internal USB PHY can be configured to multiplex the UART3_TX or UART3_RX signals to this terminal. For more details refer to USB GPIO Details section of the AM335x Technical Reference Manual.
  15. This output should only be used to source the recommended crystal circuit.
  16. This parameter only applies when this USB PHY terminal is operating in UART2 mode.
  17. This parameter only applies when this USB PHY terminal is operating in UART3 mode.
  18. This terminal is a analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2).
  19. This terminal is a analog passive signal that connects to an external 49.9 ohm 1%, 20mW reference resistor which is used to calibrate the DDR input/output buffers.
  20. This terminal is analog input that may also be configured as an open-drain output.
  21. This terminal is analog input that may also be configured as an open-source or open-drain output.
  22. This terminal is analog input that may also be configured as an open-source output.
  23. This terminal is high-Z when the oscillator is disabled. This terminal is driven high if RTC_XTALIN is less than VIL, driven low if RTC_XTALIN is greater than VIH, and driven to a unknown value if RTC_XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is disabled by default after power is applied.
  24. This terminal is high-Z when the oscillator is disabled. This terminal is driven high if XTALIN is less than VIL, driven low if XTALIN is greater than VIH, and driven to a unknown value if XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is enabled by default after power is applied.
  25. For all pins with content in the Ball Reset State column of this table, the terminal is not defined until all the supplies are ramped.
  26. This terminal requires two power supplies, VDDA3p3v_USB0 and VDDA1p8v_USB0. The "*" character in the power supply name is a wild card that represents "3p3v" and "1p8v".
  27. This terminal requires two power supplies, VDDA3p3v_USB1 and VDDA1p8v_USB1. The "*" character in the power supply name is a wild card that represents "3p3v" and "1p8v".
  28. Refer to Section 6.2.2 for additional details about VSS_OSC.
  29. Refer to Section 6.2.2 for additional details about VSS_RTC.
  30. This power rail is connected to VDD_CORE in the ZCE package.
  31. This terminal provides a Kelvin connection to VDD_MPU. It can be connected to the power supply feedback input to provide remote sensing which compensates for voltage drop in the PCB power distribution network and package. When the Kelvin connection is not used it should be connected to the same power source as VDD_MPU.

4.3 Signal Descriptions

The AM335x device contains many peripheral interfaces. In order to reduce package size and lower overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex up to eight signal functions. Although there are many combinations of pin multiplexing that are possible, only a certain number of sets, called I/O Sets, are valid due to timing limitations. These valid I/O Sets were carefully chosen to provide many possible application scenarios for the user.

Texas Instruments has developed a Windows-based application called Pin Mux Utility that helps a system designer select the appropriate pin-multiplexing configuration for their AM335x-based product design. The Pin Mux Utility provides a way to select valid I/O Sets of specific peripheral interfaces to ensure the pin-multiplexing configuration selected for a design only uses valid I/O Sets supported by the AM335x device.

  1. SIGNAL NAME: The signal name
  2. DESCRIPTION: Description of the signal
  3. TYPE: Ball type for this specific function:
    • I = Input
    • O = Output
    • I/O = Input/Output
    • D = Open drain
    • DS = Differential
    • A = Analog
  4. BALL: Package ball location

Table 4-3 ADC Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
AIN0 Analog Input/Output A B8 B6
AIN1 Analog Input/Output A A11 C7
AIN2 Analog Input/Output A A8 B7
AIN3 Analog Input/Output A B11 A7
AIN4 Analog Input/Output A C8 C8
AIN5 Analog Input A B12 B8
AIN6 Analog Input A A10 A8
AIN7 Analog Input A A12 C9
VREFN Analog Negative Reference Input AP B9 A9
VREFP Analog Positive Reference Input AP A9 B9

Table 4-4 Debug Subsystem Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
EMU0 MISC EMULATION PIN I/O A15 C14
EMU1 MISC EMULATION PIN I/O D14 B14
EMU2 MISC EMULATION PIN I/O A18, C15 A15, A17, C13
EMU3 MISC EMULATION PIN I/O B15, B18 B17, D13, D14
EMU4 MISC EMULATION PIN I/O B16, U17 A14, C15, T13
nTRST JTAG TEST RESET (ACTIVE LOW) I A13 B10
TCK JTAG TEST CLOCK I B14 A12
TDI JTAG TEST DATA INPUT I B13 B11
TDO JTAG TEST DATA OUTPUT O A14 A11
TMS JTAG TEST MODE SELECT I C14 C11

Table 4-5 LCD Controller Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
lcd_ac_bias_en LCD AC bias enable chip select O W7 R6
lcd_data0 LCD data bus I/O U1 R1
lcd_data1 LCD data bus I/O U2 R2
lcd_data10 LCD data bus I/O U5 U3
lcd_data11 LCD data bus I/O V5 U4
lcd_data12 LCD data bus I/O V6 V2
lcd_data13 LCD data bus I/O U6 V3
lcd_data14 LCD data bus I/O W6 V4
lcd_data15 LCD data bus I/O V7 T5
lcd_data16 LCD data bus O V17 U13
lcd_data17 LCD data bus O W17 V13
lcd_data18 LCD data bus O T13 R12
lcd_data19 LCD data bus O U13 T12
lcd_data2 LCD data bus I/O V1 R3
lcd_data20 LCD data bus O U12 U12
lcd_data21 LCD data bus O T12 T11
lcd_data22 LCD data bus O W16 T10
lcd_data23 LCD data bus O V15 U10
lcd_data3 LCD data bus I/O V2 R4
lcd_data4 LCD data bus I/O W2 T1
lcd_data5 LCD data bus I/O W3 T2
lcd_data6 LCD data bus I/O V3 T3
lcd_data7 LCD data bus I/O U3 T4
lcd_data8 LCD data bus I/O V4 U1
lcd_data9 LCD data bus I/O W4 U2
lcd_hsync LCD Horizontal Sync O T7 R5
lcd_memory_clk LCD MCLK O L19, V16 J17, V12
lcd_pclk LCD pixel clock O W5 V5
lcd_vsync LCD Vertical Sync O U7 U5

4.3.1 External Memory Interfaces

Table 4-6 External Memory Interfaces/DDR Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
ddr_a0 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O F3 F3
ddr_a1 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O J2 H1
ddr_a10 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O E2 F4
ddr_a11 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O G4 F2
ddr_a12 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O F4 E3
ddr_a13 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O H1 H3
ddr_a14 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O H3 H4
ddr_a15 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O E3 D3
ddr_a2 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O D1 E4
ddr_a3 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O B3 C3
ddr_a4 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O E5 C2
ddr_a5 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O A2 B1
ddr_a6 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O B1 D5
ddr_a7 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O D2 E2
ddr_a8 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O C3 D4
ddr_a9 DDR SDRAM ROW/COLUMN ADDRESS OUTPUT O B2 C1
ddr_ba0 DDR SDRAM BANK ADDRESS OUTPUT O A3 C4
ddr_ba1 DDR SDRAM BANK ADDRESS OUTPUT O E1 E1
ddr_ba2 DDR SDRAM BANK ADDRESS OUTPUT O B4 B3
ddr_casn DDR SDRAM COLUMN ADDRESS STROBE OUTPUT (ACTIVE LOW) O F1 F1
ddr_ck DDR SDRAM CLOCK OUTPUT (Differential+) O C2 D2
ddr_cke DDR SDRAM CLOCK ENABLE OUTPUT O G3 G3
ddr_csn0 DDR SDRAM CHIP SELECT OUTPUT O H2 H2
ddr_d0 DDR SDRAM DATA INPUT/OUTPUT I/O N4 M3
ddr_d1 DDR SDRAM DATA INPUT/OUTPUT I/O P4 M4
ddr_d10 DDR SDRAM DATA INPUT/OUTPUT I/O M3 K2
ddr_d11 DDR SDRAM DATA INPUT/OUTPUT I/O M4 K3
ddr_d12 DDR SDRAM DATA INPUT/OUTPUT I/O M2 K4
ddr_d13 DDR SDRAM DATA INPUT/OUTPUT I/O M1 L3
ddr_d14 DDR SDRAM DATA INPUT/OUTPUT I/O N2 L4
ddr_d15 DDR SDRAM DATA INPUT/OUTPUT I/O N1 M1
ddr_d2 DDR SDRAM DATA INPUT/OUTPUT I/O P2 N1
ddr_d3 DDR SDRAM DATA INPUT/OUTPUT I/O P1 N2
ddr_d4 DDR SDRAM DATA INPUT/OUTPUT I/O P3 N3
ddr_d5 DDR SDRAM DATA INPUT/OUTPUT I/O T1 N4
ddr_d6 DDR SDRAM DATA INPUT/OUTPUT I/O T2 P3
ddr_d7 DDR SDRAM DATA INPUT/OUTPUT I/O R3 P4
ddr_d8 DDR SDRAM DATA INPUT/OUTPUT I/O K2 J1
ddr_d9 DDR SDRAM DATA INPUT/OUTPUT I/O K1 K1
ddr_dqm0 DDR WRITE ENABLE / DATA MASK FOR DATA[7:0] O N3 M2
ddr_dqm1 DDR WRITE ENABLE / DATA MASK FOR DATA[15:8] O K3 J2
ddr_dqs0 DDR DATA STROBE FOR DATA[7:0] (Differential+) I/O R1 P1
ddr_dqs1 DDR DATA STROBE FOR DATA[15:8] (Differential+) I/O L1 L1
ddr_dqsn0 DDR DATA STROBE FOR DATA[7:0] (Differential-) I/O R2 P2
ddr_dqsn1 DDR DATA STROBE FOR DATA[15:8] (Differential-) I/O L2 L2
ddr_nck DDR SDRAM CLOCK OUTPUT (Differential-) O C1 D1
ddr_odt ODT OUTPUT O G1 G1
ddr_rasn DDR SDRAM ROW ADDRESS STROBE OUTPUT (ACTIVE LOW) O F2 G4
ddr_resetn DDR3/DDR3L RESET OUTPUT (ACTIVE LOW) O G2 G2
ddr_vref Voltage Reference Input A H4 J4
ddr_vtp VTP Compensation Resistor I J1 J3
ddr_wen DDR SDRAM WRITE ENABLE OUTPUT (ACTIVE LOW) O A4 B2

Table 4-7 External Memory Interfaces/General-Purpose Memory Controller Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
gpmc_a0 GPMC Address O U1 R1, R13
gpmc_a1 GPMC Address O U2, U7 R2, U5, V14
gpmc_a10 GPMC Address O W5 T16, V5
gpmc_a11 GPMC Address O W7 R6, V17
gpmc_a12 GPMC Address O V4 U1
gpmc_a13 GPMC Address O W4 U2
gpmc_a14 GPMC Address O U5 U3
gpmc_a15 GPMC Address O V5 U4
gpmc_a16 GPMC Address O V6 R13, V2
gpmc_a17 GPMC Address O U6 V14, V3
gpmc_a18 GPMC Address O W6 U14, V4
gpmc_a19 GPMC Address O V7 T14, T5
gpmc_a2 GPMC Address O T7, V1 R3, R5, U14
gpmc_a20 GPMC Address O H19 F17, R14
gpmc_a21 GPMC Address O H18 F18, V15
gpmc_a22 GPMC Address O H17 G15, U15
gpmc_a23 GPMC Address O G18 G16, T15
gpmc_a24 GPMC Address O G19 G17, V16
gpmc_a25 GPMC Address O G17 G18, U16
gpmc_a26 GPMC Address O NA T16
gpmc_a27 GPMC Address O NA V17
gpmc_a3 GPMC Address O U17, V2 R4, T13, T14
gpmc_a4 GPMC Address O W2 R14, T1
gpmc_a5 GPMC Address O W3 T2, V15
gpmc_a6 GPMC Address O V3 T3, U15
gpmc_a7 GPMC Address O U3 T15, T4
gpmc_a8 GPMC Address O U7 U5, V16
gpmc_a9 GPMC Address O T7 R5, U16
gpmc_ad0 GPMC Address and Data I/O W10 U7
gpmc_ad1 GPMC Address and Data I/O V9 V7
gpmc_ad10 GPMC Address and Data I/O T12 T11
gpmc_ad11 GPMC Address and Data I/O U12 U12
gpmc_ad12 GPMC Address and Data I/O U13 T12
gpmc_ad13 GPMC Address and Data I/O T13 R12
gpmc_ad14 GPMC Address and Data I/O W17 V13
gpmc_ad15 GPMC Address and Data I/O V17 U13
gpmc_ad2 GPMC Address and Data I/O V12 R8
gpmc_ad3 GPMC Address and Data I/O W13 T8
gpmc_ad4 GPMC Address and Data I/O V13 U8
gpmc_ad5 GPMC Address and Data I/O W14 V8
gpmc_ad6 GPMC Address and Data I/O U14 R9
gpmc_ad7 GPMC Address and Data I/O W15 T9
gpmc_ad8 GPMC Address and Data I/O V15 U10
gpmc_ad9 GPMC Address and Data I/O W16 T10
gpmc_advn_ale GPMC Address Valid / Address Latch Enable O V10 R7
gpmc_be0n_cle GPMC Byte Enable 0 / Command Latch Enable O V8 T6
gpmc_be1n GPMC Byte Enable 1 O U15, V18 U18, V9
gpmc_clk GPMC Clock I/O V14, V16 U9, V12
gpmc_csn0 GPMC Chip Select O W8 V6
gpmc_csn1 GPMC Chip Select O V14 U9
gpmc_csn2 GPMC Chip Select O U15 V9
gpmc_csn3 GPMC Chip Select O U17 T13
gpmc_csn4 GPMC Chip Select O R15 T17
gpmc_csn5 GPMC Chip Select O W18 U17
gpmc_csn6 GPMC Chip Select O V18 U18
gpmc_dir GPMC Data Direction O V18 U18
gpmc_oen_ren GPMC Output / Read Enable O W9 T7
gpmc_wait0 GPMC Wait 0 I R15 T17
gpmc_wait1 GPMC Wait 1 I V16 V12
gpmc_wen GPMC Write Enable O U8 U6
gpmc_wpn GPMC Write Protect O W18 U17

4.3.2 General-Purpose IOs

Table 4-8 General-Purpose IOs/GPIO0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
gpio0_0 GPIO I/O P17 M17
gpio0_1 GPIO I/O R19 M18
gpio0_10 GPIO I/O W6 V4
gpio0_11 GPIO I/O V7 T5
gpio0_12 GPIO I/O E17 D18
gpio0_13 GPIO I/O D19 D17
gpio0_14 GPIO I/O D18 D16
gpio0_15 GPIO I/O C19 D15
gpio0_16 GPIO I/O M17 J18
gpio0_17 GPIO I/O N18 K15
gpio0_18 GPIO I/O G16 F16
gpio0_19 GPIO I/O C15 A15
gpio0_2 GPIO I/O A18 A17
gpio0_20 GPIO I/O B15 D14
gpio0_21 GPIO I/O M18 K16
gpio0_22 GPIO I/O V15 U10
gpio0_23 GPIO I/O W16 T10
gpio0_26 GPIO I/O T12 T11
gpio0_27 GPIO I/O U12 U12
gpio0_28 GPIO I/O L18 K17
gpio0_29 GPIO I/O K18 H18
gpio0_3 GPIO I/O B18 B17
gpio0_30 GPIO I/O R15 T17
gpio0_31 GPIO I/O W18 U17
gpio0_4 GPIO I/O B17 B16
gpio0_5 GPIO I/O A17 A16
gpio0_6 GPIO I/O B16 C15
gpio0_7 GPIO I/O E18 C18
gpio0_8 GPIO I/O V6 V2
gpio0_9 GPIO I/O U6 V3

Table 4-9 General-Purpose IOs/GPIO1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
gpio1_0 GPIO I/O W10 U7
gpio1_1 GPIO I/O V9 V7
gpio1_10 GPIO I/O E19 E15
gpio1_11 GPIO I/O F17 E16
gpio1_12 GPIO I/O U13 T12
gpio1_13 GPIO I/O T13 R12
gpio1_14 GPIO I/O W17 V13
gpio1_15 GPIO I/O V17 U13
gpio1_16 GPIO I/O NA R13
gpio1_17 GPIO I/O NA V14
gpio1_18 GPIO I/O NA U14
gpio1_19 GPIO I/O NA T14
gpio1_2 GPIO I/O V12 R8
gpio1_20 GPIO I/O NA R14
gpio1_21 GPIO I/O NA V15
gpio1_22 GPIO I/O NA U15
gpio1_23 GPIO I/O NA T15
gpio1_24 GPIO I/O NA V16
gpio1_25 GPIO I/O NA U16
gpio1_26 GPIO I/O NA T16
gpio1_27 GPIO I/O NA V17
gpio1_28 GPIO I/O V18 U18
gpio1_29 GPIO I/O W8 V6
gpio1_3 GPIO I/O W13 T8
gpio1_30 GPIO I/O V14 U9
gpio1_31 GPIO I/O U15 V9
gpio1_4 GPIO I/O V13 U8
gpio1_5 GPIO I/O W14 V8
gpio1_6 GPIO I/O U14 R9
gpio1_7 GPIO I/O W15 T9
gpio1_8 GPIO I/O F19 E18
gpio1_9 GPIO I/O F18 E17

Table 4-10 General-Purpose IOs/GPIO2 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
gpio2_0 GPIO I/O U17 T13
gpio2_1 GPIO I/O V16 V12
gpio2_10 GPIO I/O W2 T1
gpio2_11 GPIO I/O W3 T2
gpio2_12 GPIO I/O V3 T3
gpio2_13 GPIO I/O U3 T4
gpio2_14 GPIO I/O V4 U1
gpio2_15 GPIO I/O W4 U2
gpio2_16 GPIO I/O U5 U3
gpio2_17 GPIO I/O V5 U4
gpio2_18 GPIO I/O N17 L17
gpio2_19 GPIO I/O N16 L16
gpio2_2 GPIO I/O V10 R7
gpio2_20 GPIO I/O P19 L15
gpio2_21 GPIO I/O P18 M16
gpio2_22 GPIO I/O U7 U5
gpio2_23 GPIO I/O T7 R5
gpio2_24 GPIO I/O W5 V5
gpio2_25 GPIO I/O W7 R6
gpio2_26 GPIO I/O H19 F17
gpio2_27 GPIO I/O H18 F18
gpio2_28 GPIO I/O H17 G15
gpio2_29 GPIO I/O G18 G16
gpio2_3 GPIO I/O W9 T7
gpio2_30 GPIO I/O G19 G17
gpio2_31 GPIO I/O G17 G18
gpio2_4 GPIO I/O U8 U6
gpio2_5 GPIO I/O V8 T6
gpio2_6 GPIO I/O U1 R1
gpio2_7 GPIO I/O U2 R2
gpio2_8 GPIO I/O V1 R3
gpio2_9 GPIO I/O V2 R4

Table 4-11 General-Purpose IOs/GPIO3 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
gpio3_0 GPIO I/O J19 H16
gpio3_1 GPIO I/O J18 H17
gpio3_10 GPIO I/O M19 L18
gpio3_13 GPIO I/O NA F15
gpio3_14 GPIO I/O NA A13
gpio3_15 GPIO I/O NA B13
gpio3_16 GPIO I/O NA D12
gpio3_17 GPIO I/O NA C12
gpio3_18 GPIO I/O NA B12
gpio3_19 GPIO I/O NA C13
gpio3_2 GPIO I/O K19 J15
gpio3_20 GPIO I/O NA D13
gpio3_21 GPIO I/O NA A14
gpio3_3 GPIO I/O K17 J16
gpio3_4 GPIO I/O L19 J17
gpio3_5 GPIO I/O C18 C17
gpio3_6 GPIO I/O B19 C16
gpio3_7 GPIO I/O A15 C14
gpio3_8 GPIO I/O D14 B14
gpio3_9 GPIO I/O N19 K18

4.3.3 Miscellaneous

Table 4-12 Miscellaneous/Miscellaneous Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
clkout1 Clock out1 O C15 A15
clkout2 Clock out2 O B15 D14
ENZ_KALDO_1P8V Active low enable input for internal CAP_VDD_RTC voltage regulator I A7 B4
EXT_WAKEUP EXT_WAKEUP input I B5 C5
nNMI External Interrupt to ARM Cortex-A8 core I C17 B18
nRESETIN_OUT Active low Warm Reset I/OD A16 A10
OSC0_IN High frequency oscillator input I W11 V10
OSC0_OUT High frequency oscillator output O W12 U11
OSC1_IN Low frequency (32.768 kHz) Real Time Clock oscillator input I A6 A6
OSC1_OUT Low frequency (32.768 kHz) Real Time Clock oscillator output O A5 A4
PMIC_POWER_EN PMIC_POWER_EN output O C7 C6
porz Active low Power on Reset I E15 B15
RTC_PORz Active low RTC reset input I B7 B5
tclkin Timer Clock In I B15 D14
xdma_event_intr0 External DMA Event or Interrupt 0 I C15 A15
xdma_event_intr1 External DMA Event or Interrupt 1 I B15 D14
xdma_event_intr2 External DMA Event or Interrupt 2 I B16, E18, K18 C15, C18, H18

4.3.3.1 eCAP

Table 4-13 eCAP/eCAP0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
eCAP0_in_PWM0_out Enhanced Capture 0 input or Auxiliary PWM0 output I/O E18 C18

Table 4-14 eCAP/eCAP1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
eCAP1_in_PWM1_out Enhanced Capture 1 input or Auxiliary PWM1 output I/O B16, B19, F17 C15, C16, E16

Table 4-15 eCAP/eCAP2 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
eCAP2_in_PWM2_out Enhanced Capture 2 input or Auxiliary PWM2 output I/O C18, E19 C12, C17, E15

4.3.3.2 eHRPWM

Table 4-16 eHRPWM/eHRPWM0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
ehrpwm0A eHRPWM0 A output. O A18 A13, A17
ehrpwm0B eHRPWM0 B output. O B18 B13, B17
ehrpwm0_synci Sync input to eHRPWM0 module from an external pin I A17 A16, C12
ehrpwm0_synco Sync Output from eHRPWM0 module to an external pin O U12, V2, W4 R4, U12, U2, V14
ehrpwm0_tripzone_input eHRPWM0 trip zone input I B17 B16, D12

Table 4-17 eHRPWM/eHRPWM1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
ehrpwm1A eHRPWM1 A output. O U5 U14, U3
ehrpwm1B eHRPWM1 B output. O V5 T14, U4
ehrpwm1_tripzone_input eHRPWM1 trip zone input I V4 R13, U1

Table 4-18 eHRPWM/eHRPWM2 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
ehrpwm2A eHRPWM2 A output. O U1, V15 R1, U10
ehrpwm2B eHRPWM2 B output. O U2, W16 R2, T10
ehrpwm2_tripzone_input eHRPWM2 trip zone input I T12, V1 R3, T11

4.3.3.3 eQEP

Table 4-19 eQEP/eQEP0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
eQEP0A_in eQEP0A quadrature input I M18 B12, K16
eQEP0B_in eQEP0B quadrature input I L18 C13, K17
eQEP0_index eQEP0 index. I/O K17 D13, J16
eQEP0_strobe eQEP0 strobe. I/O P19 A14, L15

Table 4-20 eQEP/eQEP1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
eQEP1A_in eQEP1A quadrature input I V6 R14, V2
eQEP1B_in eQEP1B quadrature input I U6 V15, V3
eQEP1_index eQEP1 index. I/O W6 U15, V4
eQEP1_strobe eQEP1 strobe. I/O V7 T15, T5

Table 4-21 eQEP/eQEP2 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
eQEP2A_in eQEP2A quadrature input I U13, W2 T1, T12
eQEP2B_in eQEP2B quadrature input I T13, W3 R12, T2
eQEP2_index eQEP2 index. I/O V3, W17 T3, V13
eQEP2_strobe eQEP2 strobe. I/O U3, V17 T4, U13

4.3.3.4 Timer

Table 4-22 Timer/Timer4 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
timer4 Timer trigger event / PWM out I/O C15, C18, K17, V10 A15, C17, J16, R7

Table 4-23 Timer/Timer5 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
timer5 Timer trigger event / PWM out I/O D19, H19, R19, V8 D17, F17, M18, T6

Table 4-24 Timer/Timer6 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
timer6 Timer trigger event / PWM out I/O E17, H18, P17, U8 D18, F18, M17, U6

Table 4-25 Timer/Timer7 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
timer7 Timer trigger event / PWM out I/O B15, B19, F19, W9 C16, D14, E18, T7

4.3.4 PRU-ICSS

Table 4-26 PRU-ICSS/eCAP Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
pr1_ecap0_ecap_capin_apwm_o Enhanced capture input or Auxiliary PWM out I/O E18, V17 C18, U13

Table 4-27 PRU-ICSS/ECAT Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
pr1_edc_latch0_in Data In I E17 D18
pr1_edc_latch1_in Data In I D19 D17
pr1_edc_sync0_out Data Out O F19 E18
pr1_edc_sync1_out Data Out O F18 E17
pr1_edio_data_in0 Data In I B17 B16
pr1_edio_data_in1 Data In I A17 A16
pr1_edio_data_in2 Data In I U7 U5
pr1_edio_data_in3 Data In I T7 R5
pr1_edio_data_in4 Data In I W5 V5
pr1_edio_data_in5 Data In I W7 R6
pr1_edio_data_in6 Data In I V14, V3 T3, U9
pr1_edio_data_in7 Data In I U15, U3 T4, V9
pr1_edio_data_out0 Data Out O B17 B16
pr1_edio_data_out1 Data Out O A17 A16
pr1_edio_data_out2 Data Out O U7 U5
pr1_edio_data_out3 Data Out O T7 R5
pr1_edio_data_out4 Data Out O W5 V5
pr1_edio_data_out5 Data Out O W7 R6
pr1_edio_data_out6 Data Out O V14, V3 T3, U9
pr1_edio_data_out7 Data Out O U15, U3 T4, V9
pr1_edio_latch_in Latch In I B18 B17
pr1_edio_sof Start of Frame O A18 A17

Table 4-28 PRU-ICSS/MDIO Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
pr1_mdio_data MDIO Data I/O U17 T13
pr1_mdio_mdclk MDIO Clk O V16 V12

Table 4-29 PRU-ICSS/MII0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
pr1_mii0_col MII Collision Detect I W16 T10
pr1_mii0_crs MII Carrier Sense I U17, W5 T13, V5
pr1_mii0_rxd0 MII Receive Data bit 0 I V5 U4
pr1_mii0_rxd1 MII Receive Data bit 1 I U5 U3
pr1_mii0_rxd2 MII Receive Data bit 2 I W4 U2
pr1_mii0_rxd3 MII Receive Data bit 3 I V4 U1
pr1_mii0_rxdv MII Receive Data Valid I V7 T5
pr1_mii0_rxer MII Receive Data Error I U6 V3
pr1_mii0_rxlink MII Receive Link I V6 V2
pr1_mii0_txd0 MII Transmit Data bit 0 O W17, W3 T2, V13
pr1_mii0_txd1 MII Transmit Data bit 1 O T13, W2 R12, T1
pr1_mii0_txd2 MII Transmit Data bit 2 O U13, V2 R4, T12
pr1_mii0_txd3 MII Transmit Data bit 3 O U12, V1 R3, U12
pr1_mii0_txen MII Transmit Enable O T12, U2 R2, T11
pr1_mii_mr0_clk MII Receive Clock I W6 V4
pr1_mii_mt0_clk MII Transmit Clock I U1, V15 R1, U10

Table 4-30 PRU-ICSS/MII1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
pr1_mii1_col MII Collision Detect I R15 T17
pr1_mii1_crs MII Carrier Sense I V16, W7 R6, V12
pr1_mii1_rxd0 MII Receive Data bit 0 I NA V16
pr1_mii1_rxd1 MII Receive Data bit 1 I NA T15
pr1_mii1_rxd2 MII Receive Data bit 2 I NA U15
pr1_mii1_rxd3 MII Receive Data bit 3 I NA V15
pr1_mii1_rxdv MII Receive Data Valid I NA T16
pr1_mii1_rxer MII Receive Data Error I NA V17
pr1_mii1_rxlink MII Receive Link I V18 U18
pr1_mii1_txd0 MII Transmit Data bit 0 O NA R14
pr1_mii1_txd1 MII Transmit Data bit 1 O NA T14
pr1_mii1_txd2 MII Transmit Data bit 2 O NA U14
pr1_mii1_txd3 MII Transmit Data bit 3 O NA V14
pr1_mii1_txen MII Transmit Enable O W18 U17
pr1_mii_mr1_clk MII Receive Clock I NA U16
pr1_mii_mt1_clk MII Transmit Clock I NA R13

Table 4-31 PRU-ICSS/UART0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
pr1_uart0_cts_n UART Clear to Send I A18, E17 A17, D18
pr1_uart0_rts_n UART Request to Send O B18, D19 B17, D17
pr1_uart0_rxd UART Receive Data I B17, D18 B16, D16
pr1_uart0_txd UART Transmit Data O A17, C19 A16, D15

4.3.4.1 PRU0

Table 4-32 PRU0/General-Purpose Inputs Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
pr1_pru0_pru_r31_0 PRU0 Data In I NA A13
pr1_pru0_pru_r31_1 PRU0 Data In I NA B13
pr1_pru0_pru_r31_10 PRU0 Data In I H17 G15
pr1_pru0_pru_r31_11 PRU0 Data In I G18 G16
pr1_pru0_pru_r31_12 PRU0 Data In I G19 G17
pr1_pru0_pru_r31_13 PRU0 Data In I G17 G18
pr1_pru0_pru_r31_14 PRU0 Data In I W17 V13
pr1_pru0_pru_r31_15 PRU0 Data In I V17 U13
pr1_pru0_pru_r31_16 PRU0 Data In Capture Enable I B15, C19 D14, D15
pr1_pru0_pru_r31_2 PRU0 Data In I NA D12
pr1_pru0_pru_r31_3 PRU0 Data In I NA C12
pr1_pru0_pru_r31_4 PRU0 Data In I NA B12
pr1_pru0_pru_r31_5 PRU0 Data In I NA C13
pr1_pru0_pru_r31_6 PRU0 Data In I NA D13
pr1_pru0_pru_r31_7 PRU0 Data In I NA A14
pr1_pru0_pru_r31_8 PRU0 Data In I H19 F17
pr1_pru0_pru_r31_9 PRU0 Data In I H18 F18

Table 4-33 PRU0/General-Purpose Outputs Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
pr1_pru0_pru_r30_0 PRU0 Data Out O NA A13
pr1_pru0_pru_r30_1 PRU0 Data Out O NA B13
pr1_pru0_pru_r30_10 PRU0 Data Out O H17 G15
pr1_pru0_pru_r30_11 PRU0 Data Out O G18 G16
pr1_pru0_pru_r30_12 PRU0 Data Out O G19 G17
pr1_pru0_pru_r30_13 PRU0 Data Out O G17 G18
pr1_pru0_pru_r30_14 PRU0 Data Out O U13 T12
pr1_pru0_pru_r30_15 PRU0 Data Out O T13 R12
pr1_pru0_pru_r30_2 PRU0 Data Out O NA D12
pr1_pru0_pru_r30_3 PRU0 Data Out O NA C12
pr1_pru0_pru_r30_4 PRU0 Data Out O NA B12
pr1_pru0_pru_r30_5 PRU0 Data Out O NA C13
pr1_pru0_pru_r30_6 PRU0 Data Out O NA D13
pr1_pru0_pru_r30_7 PRU0 Data Out O NA A14
pr1_pru0_pru_r30_8 PRU0 Data Out O H19 F17
pr1_pru0_pru_r30_9 PRU0 Data Out O H18 F18

4.3.4.2 PRU1

Table 4-34 PRU1/General-Purpose Inputs Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
pr1_pru1_pru_r31_0 PRU1 Data In I U1 R1
pr1_pru1_pru_r31_1 PRU1 Data In I U2 R2
pr1_pru1_pru_r31_10 PRU1 Data In I W5 V5
pr1_pru1_pru_r31_11 PRU1 Data In I W7 R6
pr1_pru1_pru_r31_12 PRU1 Data In I V14 U9
pr1_pru1_pru_r31_13 PRU1 Data In I U15 V9
pr1_pru1_pru_r31_14 PRU1 Data In I E19 E15
pr1_pru1_pru_r31_15 PRU1 Data In I F17 E16
pr1_pru1_pru_r31_16 PRU1 Data In Capture Enable I C15, D18 A15, D16
pr1_pru1_pru_r31_2 PRU1 Data In I V1 R3
pr1_pru1_pru_r31_3 PRU1 Data In I V2 R4
pr1_pru1_pru_r31_4 PRU1 Data In I W2 T1
pr1_pru1_pru_r31_5 PRU1 Data In I W3 T2
pr1_pru1_pru_r31_6 PRU1 Data In I V3 T3
pr1_pru1_pru_r31_7 PRU1 Data In I U3 T4
pr1_pru1_pru_r31_8 PRU1 Data In I U7 U5
pr1_pru1_pru_r31_9 PRU1 Data In I T7 R5

Table 4-35 PRU1/General-Purpose Outputs Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
pr1_pru1_pru_r30_0 PRU1 Data Out O U1 R1
pr1_pru1_pru_r30_1 PRU1 Data Out O U2 R2
pr1_pru1_pru_r30_10 PRU1 Data Out O W5 V5
pr1_pru1_pru_r30_11 PRU1 Data Out O W7 R6
pr1_pru1_pru_r30_12 PRU1 Data Out O V14 U9
pr1_pru1_pru_r30_13 PRU1 Data Out O U15 V9
pr1_pru1_pru_r30_14 PRU1 Data Out O E19 E15
pr1_pru1_pru_r30_15 PRU1 Data Out O F17 E16
pr1_pru1_pru_r30_2 PRU1 Data Out O V1 R3
pr1_pru1_pru_r30_3 PRU1 Data Out O V2 R4
pr1_pru1_pru_r30_4 PRU1 Data Out O W2 T1
pr1_pru1_pru_r30_5 PRU1 Data Out O W3 T2
pr1_pru1_pru_r30_6 PRU1 Data Out O V3 T3
pr1_pru1_pru_r30_7 PRU1 Data Out O U3 T4
pr1_pru1_pru_r30_8 PRU1 Data Out O U7 U5
pr1_pru1_pru_r30_9 PRU1 Data Out O T7 R5

4.3.5 Removable Media Interfaces

Table 4-36 Removable Media Interfaces/MMC0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
mmc0_clk MMC/SD/SDIO Clock I/O G19 G17
mmc0_cmd MMC/SD/SDIO Command I/O G17 G18
mmc0_dat0 MMC/SD/SDIO Data Bus I/O G18 G16
mmc0_dat1 MMC/SD/SDIO Data Bus I/O H17 G15
mmc0_dat2 MMC/SD/SDIO Data Bus I/O H18 F18
mmc0_dat3 MMC/SD/SDIO Data Bus I/O H19 F17
mmc0_dat4 MMC/SD/SDIO Data Bus I/O N16 L16
mmc0_dat5 MMC/SD/SDIO Data Bus I/O N17 L17
mmc0_dat6 MMC/SD/SDIO Data Bus I/O M19 L18
mmc0_dat7 MMC/SD/SDIO Data Bus I/O N19 K18
mmc0_pow MMC/SD Power Switch Control O B16, K18 C15, H18
mmc0_sdcd SD Card Detect I B16, P17 A13, C15, M17
mmc0_sdwp SD Write Protect I E18, R19 B12, C18, M18

Table 4-37 Removable Media Interfaces/MMC1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
mmc1_clk MMC/SD/SDIO Clock I/O L18, R19, V14 K17, M18, U9
mmc1_cmd MMC/SD/SDIO Command I/O M18, P17, U15 K16, M17, V9
mmc1_dat0 MMC/SD/SDIO Data Bus I/O N19, V15, W10 K18, U10, U7
mmc1_dat1 MMC/SD/SDIO Data Bus I/O M19, V9, W16 L18, T10, V7
mmc1_dat2 MMC/SD/SDIO Data Bus I/O N17, T12, V12 L17, R8, T11
mmc1_dat3 MMC/SD/SDIO Data Bus I/O N16, U12, W13 L16, T8, U12
mmc1_dat4 MMC/SD/SDIO Data Bus I/O U13, V13 T12, U8
mmc1_dat5 MMC/SD/SDIO Data Bus I/O T13, W14 R12, V8
mmc1_dat6 MMC/SD/SDIO Data Bus I/O U14, W17 R9, V13
mmc1_dat7 MMC/SD/SDIO Data Bus I/O V17, W15 T9, U13
mmc1_sdcd SD Card Detect I R15 B13, T17
mmc1_sdwp SD Write Protect I B17, D18 B16, D16

Table 4-38 Removable Media Interfaces/MMC2 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
mmc2_clk MMC/SD/SDIO Clock I/O P19, R19, V16 L15, M18, V12
mmc2_cmd MMC/SD/SDIO Command I/O K17, P17, U17 J16, M17, T13
mmc2_dat0 MMC/SD/SDIO Data Bus I/O L19, U13 J17, T12, V14
mmc2_dat1 MMC/SD/SDIO Data Bus I/O M17, T13 J18, R12, U14
mmc2_dat2 MMC/SD/SDIO Data Bus I/O N18, W17 K15, T14, V13
mmc2_dat3 MMC/SD/SDIO Data Bus I/O J19, V17, V18 H16, U13, U18
mmc2_dat4 MMC/SD/SDIO Data Bus I/O V15 U10, U15
mmc2_dat5 MMC/SD/SDIO Data Bus I/O W16 T10, T15
mmc2_dat6 MMC/SD/SDIO Data Bus I/O T12 T11, V16
mmc2_dat7 MMC/SD/SDIO Data Bus I/O U12 U12
mmc2_sdcd SD Card Detect I W18 D12, U17
mmc2_sdwp SD Write Protect I A17, C19 A16, D15

4.3.6 Serial Communication Interfaces

4.3.6.1 CAN

Table 4-39 CAN/DCAN0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
dcan0_rx DCAN0 Receive Data I D19, F17, N18 D17, E16, K15
dcan0_tx DCAN0 Transmit Data O E17, E19, M17 D18, E15, J18

Table 4-40 CAN/DCAN1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
dcan1_rx DCAN1 Receive Data I C19, F18, G17 D15, E17, G18
dcan1_tx DCAN1 Transmit Data O D18, F19, G19 D16, E18, G17

4.3.6.2 GEMAC_CPSW

Table 4-41 GEMAC_CPSW/MDIO Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
mdio_clk MDIO Clk O R19 M18
mdio_data MDIO Data I/O P17 M17

Table 4-42 GEMAC_CPSW/MII1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
gmii1_col MII Colision I J19 H16
gmii1_crs MII Carrier Sense I J18 H17
gmii1_rxclk MII Receive Clock I M19 L18
gmii1_rxd0 MII Receive Data bit 0 I P18 M16
gmii1_rxd1 MII Receive Data bit 1 I P19 L15
gmii1_rxd2 MII Receive Data bit 2 I N16 L16
gmii1_rxd3 MII Receive Data bit 3 I N17 L17
gmii1_rxdv MII Receive Data Valid I L19 J17
gmii1_rxer MII Receive Data Error I K19 J15
gmii1_txclk MII Transmit Clock I N19 K18
gmii1_txd0 MII Transmit Data bit 0 O L18 K17
gmii1_txd1 MII Transmit Data bit 1 O M18 K16
gmii1_txd2 MII Transmit Data bit 2 O N18 K15
gmii1_txd3 MII Transmit Data bit 3 O M17 J18
gmii1_txen MII Transmit Enable O K17 J16

Table 4-43 GEMAC_CPSW/MII2 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
gmii2_col MII Colision I V18 U18
gmii2_crs MII Carrier Sense I R15 T17
gmii2_rxclk MII Receive Clock I NA T15
gmii2_rxd0 MII Receive Data bit 0 I NA V17
gmii2_rxd1 MII Receive Data bit 1 I NA T16
gmii2_rxd2 MII Receive Data bit 2 I NA U16
gmii2_rxd3 MII Receive Data bit 3 I NA V16
gmii2_rxdv MII Receive Data Valid I NA V14
gmii2_rxer MII Receive Data Error I W18 U17
gmii2_txclk MII Transmit Clock I NA U15
gmii2_txd0 MII Transmit Data bit 0 O NA V15
gmii2_txd1 MII Transmit Data bit 1 O NA R14
gmii2_txd2 MII Transmit Data bit 2 O NA T14
gmii2_txd3 MII Transmit Data bit 3 O NA U14
gmii2_txen MII Transmit Enable O NA R13

Table 4-44 GEMAC_CPSW/RGMII1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
rgmii1_rclk RGMII Receive Clock I M19 L18
rgmii1_rctl RGMII Receive Control I L19 J17
rgmii1_rd0 RGMII Receive Data bit 0 I P18 M16
rgmii1_rd1 RGMII Receive Data bit 1 I P19 L15
rgmii1_rd2 RGMII Receive Data bit 2 I N16 L16
rgmii1_rd3 RGMII Receive Data bit 3 I N17 L17
rgmii1_tclk RGMII Transmit Clock O N19 K18
rgmii1_tctl RGMII Transmit Control O K17 J16
rgmii1_td0 RGMII Transmit Data bit 0 O L18 K17
rgmii1_td1 RGMII Transmit Data bit 1 O M18 K16
rgmii1_td2 RGMII Transmit Data bit 2 O N18 K15
rgmii1_td3 RGMII Transmit Data bit 3 O M17 J18

Table 4-45 GEMAC_CPSW/RGMII2 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
rgmii2_rclk RGMII Receive Clock I NA T15
rgmii2_rctl RGMII Receive Control I NA V14
rgmii2_rd0 RGMII Receive Data bit 0 I NA V17
rgmii2_rd1 RGMII Receive Data bit 1 I NA T16
rgmii2_rd2 RGMII Receive Data bit 2 I NA U16
rgmii2_rd3 RGMII Receive Data bit 3 I NA V16
rgmii2_tclk RGMII Transmit Clock O NA U15
rgmii2_tctl RGMII Transmit Control O NA R13
rgmii2_td0 RGMII Transmit Data bit 0 O NA V15
rgmii2_td1 RGMII Transmit Data bit 1 O NA R14
rgmii2_td2 RGMII Transmit Data bit 2 O NA T14
rgmii2_td3 RGMII Transmit Data bit 3 O NA U14

Table 4-46 GEMAC_CPSW/RMII1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
rmii1_crs_dv RMII Carrier Sense / Data Valid I J18 H17
rmii1_refclk RMII Reference Clock I/O K18 H18
rmii1_rxd0 RMII Receive Data bit 0 I P18 M16
rmii1_rxd1 RMII Receive Data bit 1 I P19 L15
rmii1_rxer RMII Receive Data Error I K19 J15
rmii1_txd0 RMII Transmit Data bit 0 O L18 K17
rmii1_txd1 RMII Transmit Data bit 1 O M18 K16
rmii1_txen RMII Transmit Enable O K17 J16

Table 4-47 GEMAC_CPSW/RMII2 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
rmii2_crs_dv RMII Carrier Sense / Data Valid I R15, U17 T13, T17
rmii2_refclk RMII Reference Clock I/O J19 H16
rmii2_rxd0 RMII Receive Data bit 0 I NA V17
rmii2_rxd1 RMII Receive Data bit 1 I NA T16
rmii2_rxer RMII Receive Data Error I W18 U17
rmii2_txd0 RMII Transmit Data bit 0 O NA V15
rmii2_txd1 RMII Transmit Data bit 1 O NA R14
rmii2_txen RMII Transmit Enable O NA R13

4.3.6.3 I2C

Table 4-48 I2C/I2C0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
I2C0_SCL I2C0 Clock I/OD B19 C16
I2C0_SDA I2C0 Data I/OD C18 C17

Table 4-49 I2C/I2C1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
I2C1_SCL I2C1 Clock I/OD A17, C19, F18, K19 A16, D15, E17, J15
I2C1_SDA I2C1 Data I/OD B17, D18, F19, J18 B16, D16, E18, H17

Table 4-50 I2C/I2C2 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
I2C2_SCL I2C2 Clock I/OD B18, D19, F17 B17, D17, E16
I2C2_SDA I2C2 Data I/OD A18, E17, E19 A17, D18, E15

4.3.6.4 McASP

Table 4-51 McASP/MCASP0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
mcasp0_aclkr McASP0 Receive Bit Clock I/O L19, V18, V6 B12, J17, U18, V2
mcasp0_aclkx McASP0 Transmit Bit Clock I/O N19, V4 A13, K18, U1, V16
mcasp0_ahclkr McASP0 Receive Master Clock I/O V5 C12, U4
mcasp0_ahclkx McASP0 Transmit Master Clock I/O N18, V7 A14, K15, T5
mcasp0_axr0 McASP0 Serial Data (IN/OUT) I/O N17, U5 D12, L17, T16, U3
mcasp0_axr1 McASP0 Serial Data (IN/OUT) I/O N16, W6 D13, L16, V17, V4
mcasp0_axr2 McASP0 Serial Data (IN/OUT) I/O J19, V5, V6 B12, C12, H16, U4, V2
mcasp0_axr3 McASP0 Serial Data (IN/OUT) I/O P18, U6, V7 A14, C13, M16, T5, V3
mcasp0_fsr McASP0 Receive Frame Sync I/O M17, U6, V16 C13, J18, V12, V3
mcasp0_fsx McASP0 Transmit Frame Sync I/O M19, W4 B13, L18, U16, U2

Table 4-52 McASP/MCASP1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
mcasp1_aclkr McASP1 Receive Bit Clock I/O L18, P18 K17, M16
mcasp1_aclkx McASP1 Transmit Bit Clock I/O J18, L19 B12, H17, J17
mcasp1_ahclkr McASP1 Receive Master Clock I/O P18 M16
mcasp1_ahclkx McASP1 Transmit Master Clock I/O K18, P18 H18, M16
mcasp1_axr0 McASP1 Serial Data (IN/OUT) I/O K17, N18 D13, J16, K15
mcasp1_axr1 McASP1 Serial Data (IN/OUT) I/O M18 A14, K16
mcasp1_axr2 McASP1 Serial Data (IN/OUT) I/O J19, L18 H16, K17
mcasp1_axr3 McASP1 Serial Data (IN/OUT) I/O K18, P19 H18, L15
mcasp1_fsr McASP1 Receive Frame Sync I/O M18, P19 K16, L15
mcasp1_fsx McASP1 Transmit Frame Sync I/O K19, M17 C13, J15, J18

4.3.6.5 SPI

Table 4-53 SPI/SPI0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
spi0_cs0 SPI Chip Select I/O A17 A16
spi0_cs1 SPI Chip Select I/O B16 C15
spi0_d0 SPI Data I/O B18 B17
spi0_d1 SPI Data I/O B17 B16
spi0_sclk SPI Clock I/O A18 A17

Table 4-54 SPI/SPI1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
spi1_cs0 SPI Chip Select I/O E17, E19, F18, K18 C12, D18, E15, E17, H18
spi1_cs1 SPI Chip Select I/O C15, D19, E18, F17 A15, C18, D17, E16
spi1_d0 SPI Data I/O F19, J18 B13, E18, H17
spi1_d1 SPI Data I/O F18, K19 D12, E17, J15
spi1_sclk SPI Clock I/O E18, J19 A13, C18, H16

4.3.6.6 UART

Table 4-55 UART/UART0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
uart0_ctsn UART Clear to Send I F19 E18
uart0_rtsn UART Request to Send O F18 E17
uart0_rxd UART Receive Data I E19 E15
uart0_txd UART Transmit Data O F17 E16

Table 4-56 UART/UART1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
uart1_ctsn UART Clear to Send I E17 D18
uart1_dcdn UART Data Carrier Detect I H19, N19 F17, K18
uart1_dsrn UART Data Set Ready I H18, M19 F18, L18
uart1_dtrn UART Data Terminal Ready O H17, N17 G15, L17
uart1_rin UART Ring Indicator I G18, N16 G16, L16
uart1_rtsn UART Request to Send O D19 D17
uart1_rxd UART Receive Data I D18 D16
uart1_txd UART Transmit Data O C19 D15

Table 4-57 UART/UART2 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
uart2_ctsn UART Clear to Send I C18, V4 C17, U1
uart2_rtsn UART Request to Send O B19, W4 C16, U2
uart2_rxd UART Receive Data I A18, G19, J18, N19 A17, G17, H17, K18
uart2_txd UART Transmit Data O B18, G17, K19, M19 B17, G18, J15, L18

Table 4-58 UART/UART3 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
uart3_ctsn UART Clear to Send I G19, P17, U5 G17, M17, U3
uart3_rtsn UART Request to Send O G17, R19, V5 G18, M18, U4
uart3_rxd UART Receive Data I B16, H17, N17 C15, G15, L17
uart3_txd UART Transmit Data O E18, G18, N16 C18, G16, L16

Table 4-59 UART/UART4 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
uart4_ctsn UART Clear to Send I H19, V6 F17, V2
uart4_rtsn UART Request to Send O H18, U6 F18, V3
uart4_rxd UART Receive Data I F19, M17, R15 E18, J18, T17
uart4_txd UART Transmit Data O F18, N18, W18 E17, K15, U17

Table 4-60 UART/UART5 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
uart5_ctsn UART Clear to Send I H17, J18, W6 G15, H17, V4
uart5_rtsn UART Request to Send O G18, K19, V7 G16, J15, T5
uart5_rxd UART Receive Data I J19, P17, W4, W6 H16, M17, U2, V4
uart5_txd UART Transmit Data O K18, L19, R19, V4 H18, J17, M18, U1

4.3.6.7 USB

Table 4-61 USB/USB0 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
USB0_CE USB0 Active high Charger Enable output A T18 M15
USB0_DM USB0 Data minus A U18 N18
USB0_DP USB0 Data plus A U19 N17
USB0_DRVVBUS USB0 Active high VBUS control output O G16 F16
USB0_ID USB0 OTG ID (Micro-A or Micro-B Plug) A V19 P16
USB0_VBUS USB0 VBUS A T19 P15

Table 4-62 USB/USB1 Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4]
USB1_CE USB1 Active high Charger Enable output A NA P18
USB1_DM USB1 Data minus A NA R18
USB1_DP USB1 Data plus A NA R17
USB1_DRVVBUS USB1 Active high VBUS control output O NA F15
USB1_ID USB1 OTG ID (Micro-A or Micro-B Plug) A NA P17
USB1_VBUS USB1 VBUS A NA T18