JAJSDZ0J October 2011 – April 2016 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359
PRODUCTION DATA.
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The AM335x device contains many peripheral interfaces. In order to reduce package size and lower overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex up to eight signal functions. Although there are many combinations of pin multiplexing that are possible, only a certain number of sets, called I/O Sets, are valid due to timing limitations. These valid I/O Sets were carefully chosen to provide many possible application scenarios for the user.
Texas Instruments has developed a Windows-based application called Pin Mux Utility that helps a system designer select the appropriate pin-multiplexing configuration for their AM335x-based product design. The Pin Mux Utility provides a way to select valid I/O Sets of specific peripheral interfaces to ensure the pin-multiplexing configuration selected for a design only uses valid I/O Sets supported by the AM335x device.
The data provided in the following Timing Requirements and Switching Characteristics tables assumes the device is operating within the Recommended Operating Conditions defined in Section 5, unless otherwise noted.
The timing parameter values specified in this data manual do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing or decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers may be used to compensate any timing differences.
The timing parameter values specified in this data manual assume the SLEWCTRL bit in each pad control register is configured for fast mode (0b).
For the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface, it is not necessary to use the IBIS models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface timings are met.
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
Some peripherals and features have limited support when the device is operating in OPP50. A complete list of these limitations follows.
Not supported when operating in OPP50: | Reduced performance when operating in OPP50: |
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For more information, see the Controller Area Network (CAN) section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
ƒbaud(baud) | Maximum programmable baud rate | 1 | Mbps | ||
1 | tw(RX) | Pulse duration, receive data bit | H – 2(1) | H + 2(1) | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
ƒbaud(baud) | Maximum programmable baud rate | 1 | Mbps | ||
2 | tw(TX) | Pulse duration, transmit data bit | H – 2(1) | H + 2(1) | ns |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | tc(TCLKIN) | Cycle time, TCLKIN | 4P + 1(1) | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
2 | tw(TIMERxH) | Pulse duration, high | 4P – 3(1) | ns | |
3 | tw(TIMERxL) | Pulse duration, low | 4P – 3(1) | ns |
The EMAC and Switch implemented in the AM335x device supports GMII mode, but the AM335x design does not pin out 9 of the 24 GMII signals. This was done to reduce the total number of package terminals. Therefore, the AM335x device does not support GMII mode. MII mode is supported with the remaining GMII signals.
The AM335x and AMIC110 Sitara Processors Technical Reference Manual and this document may reference internal signal names when discussing peripheral input and output signals because many of the AM335x package terminals can be multiplexed to one of several peripheral signals. For example, the AM335x terminal names for port 1 of the EMAC and switch have been changed from GMII to MII to indicate their Mode 0 function, but the internal signal is named GMII. However, documents that describe the Ethernet switch reference these signals by their internal signal name. For a cross-reference of internal signal names to terminal names, see Table 4-2.
Operation of the EMAC and switch is not supported for OPP50.
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Input Conditions | |||||
tR | Input signal rise time | 1(1) | 5(1) | ns | |
tF | Input signal fall time | 1(1) | 5(1) | ns | |
Output Condition | |||||
CLOAD | Output load capacitance | 3 | 30 | pF |
NO. | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | tsu(MDIO-MDC) | Setup time, MDIO valid before MDC high | 90 | ns | ||
2 | th(MDIO-MDC) | Hold time, MDIO valid from MDC high | 0 | ns |
NO. | PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | tc(MDC) | Cycle time, MDC | 400 | ns | ||
2 | tw(MDCH) | Pulse duration, MDC high | 160 | ns | ||
3 | tw(MDCL) | Pulse duration, MDC low | 160 | ns | ||
4 | tt(MDC) | Transition time, MDC | 5 | ns |
NO. | PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | td(MDC-MDIO) | Delay time, MDC high to MDIO valid | 10 | 390 | ns |
NO. | 10 Mbps | 100 Mbps | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | tc(RX_CLK) | Cycle time, RX_CLK | 399.96 | 400.04 | 39.996 | 40.004 | ns | ||
2 | tw(RX_CLKH) | Pulse duration, RX_CLK high | 140 | 260 | 14 | 26 | ns | ||
3 | tw(RX_CLKL) | Pulse duration, RX_CLK low | 140 | 260 | 14 | 26 | ns | ||
4 | tt(RX_CLK) | Transition time, RX_CLK | 5 | 5 | ns |
NO. | 10 Mbps | 100 Mbps | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | tc(TX_CLK) | Cycle time, TX_CLK | 399.96 | 400.04 | 39.996 | 40.004 | ns | ||
2 | tw(TX_CLKH) | Pulse duration, TX_CLK high | 140 | 260 | 14 | 26 | ns | ||
3 | tw(TX_CLKL) | Pulse duration, TX_CLK low | 140 | 260 | 14 | 26 | ns | ||
4 | tt(TX_CLK) | Transition time, TX_CLK | 5 | 5 | ns |
NO. | 10 Mbps | 100 Mbps | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | tsu(RXD-RX_CLK) | Setup time, RXD[3:0] valid before RX_CLK | 8 | 8 | ns | ||||
tsu(RX_DV-RX_CLK) | Setup time, RX_DV valid before RX_CLK | ||||||||
tsu(RX_ER-RX_CLK) | Setup time, RX_ER valid before RX_CLK | ||||||||
2 | th(RX_CLK-RXD) | Hold time RXD[3:0] valid after RX_CLK | 8 | 8 | ns | ||||
th(RX_CLK-RX_DV) | Hold time RX_DV valid after RX_CLK | ||||||||
th(RX_CLK-RX_ER) | Hold time RX_ER valid after RX_CLK |
NO. | PARAMETER | 10 Mbps | 100 Mbps | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | td(TX_CLK-TXD) | Delay time, TX_CLK high to TXD[3:0] valid | 5 | 25 | 5 | 25 | ns | ||
td(TX_CLK-TX_EN) | Delay time, TX_CLK to TX_EN valid |
NO. | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | tc(REF_CLK) | Cycle time, REF_CLK | 19.999 | 20.001 | ns | |
2 | tw(REF_CLKH) | Pulse duration, REF_CLK high | 7 | 13 | ns | |
3 | tw(REF_CLKL) | Pulse duration, REF_CLK low | 7 | 13 | ns |
NO. | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | tsu(RXD-REF_CLK) | Setup time, RXD[1:0] valid before REF_CLK | 4 | ns | ||
tsu(CRS_DV-REF_CLK) | Setup time, CRS_DV valid before REF_CLK | |||||
tsu(RX_ER-REF_CLK) | Setup time, RX_ER valid before REF_CLK | |||||
2 | th(REF_CLK-RXD) | Hold time RXD[1:0] valid after REF_CLK | 2 | ns | ||
th(REF_CLK-CRS_DV) | Hold time, CRS_DV valid after REF_CLK | |||||
th(REF_CLK-RX_ER) | Hold time, RX_ER valid after REF_CLK |
NO. | PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | td(REF_CLK-TXD) | Delay time, REF_CLK high to TXD[1:0] valid | 2 | 13 | ns | |
td(REF_CLK-TXEN) | Delay time, REF_CLK to TXEN valid | |||||
2 | tr(TXD) | Rise time, TXD outputs | 1 | 5 | ns | |
tr(TX_EN) | Rise time, TX_EN output | |||||
3 | tf(TXD) | Fall time, TXD outputs | 1 | 5 | ns | |
tf(TX_EN) | Fall time, TX_EN output |
NO. | 10 Mbps | 100 Mbps | 1000 Mbps | UNIT | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | tc(RXC) | Cycle time, RXC | 360 | 440 | 36 | 44 | 7.2 | 8.8 | ns | |||
2 | tw(RXCH) | Pulse duration, RXC high | 160 | 240 | 16 | 24 | 3.6 | 4.4 | ns | |||
3 | tw(RXCL) | Pulse duration, RXC low | 160 | 240 | 16 | 24 | 3.6 | 4.4 | ns | |||
4 | tt(RXC) | Transition time, RXC | 0.75 | 0.75 | 0.75 | ns |
NO. | 10 Mbps | 100 Mbps | 1000 Mbps | UNIT | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | tsu(RD-RXC) | Setup time, RD[3:0] valid before RXC high or low | 1 | 1 | 1 | ns | ||||||
tsu(RX_CTL-RXC) | Setup time, RX_CTL valid before RXC high or low | 1 | 1 | 1 | ||||||||
2 | th(RXC-RD) | Hold time, RD[3:0] valid after RXC high or low | 1 | 1 | 1 | ns | ||||||
th(RXC-RX_CTL) | Hold time, RX_CTL valid after RXC high or low | 1 | 1 | 1 | ||||||||
3 | tt(RD) | Transition time, RD | 0.75 | 0.75 | 0.75 | ns | ||||||
tt(RX_CTL) | Transition time, RX_CTL | 0.75 | 0.75 | 0.75 |
NO. | PARAMETER | 10 Mbps | 100 Mbps | 1000 Mbps | UNIT | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | tc(TXC) | Cycle time, TXC | 360 | 440 | 36 | 44 | 7.2 | 8.8 | ns | |||
2 | tw(TXCH) | Pulse duration, TXC high | 160 | 240 | 16 | 24 | 3.6 | 4.4 | ns | |||
3 | tw(TXCL) | Pulse duration, TXC low | 160 | 240 | 16 | 24 | 3.6 | 4.4 | ns | |||
4 | tt(TXC) | Transition time, TXC | 0.75 | 0.75 | 0.75 | ns |
NO. | PARAMETER | 10 Mbps | 100 Mbps | 1000 Mbps | UNIT | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | tsk(TD-TXC) | TD to TXC output skew | –0.5 | 0.5 | –0.5 | 0.5 | –0.5 | 0.5 | ns | |||
tsk(TX_CTL-TXC) | TX_CTL to TXC output skew | –0.5 | 0.5 | –0.5 | 0.5 | –0.5 | 0.5 | |||||
2 | tt(TD) | Transition time, TD | 0.75 | 0.75 | 0.75 | ns | ||||||
tt(TX_CTL) | Transition time, TX_CTL | 0.75 | 0.75 | 0.75 |
The device includes the following external memory interfaces:
NOTE
For more information, see the Memory Subsystem and General-Purpose Memory Controller section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
The GPMC is the unified memory controller used to interface external memory devices such as:
Table 7-21 and Table 7-22 assume testing over the recommended operating conditions and electrical characteristic conditions shown in Table 7-20 (see Figure 7-17 through Figure 7-21).
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Input Conditions | |||||
tR | Input signal rise time | 1 | 5 | ns | |
tF | Input signal fall time | 1 | 5 | ns | |
Output Condition | |||||
CLOAD | Output load capacitance | 3 | 30 | pF |
NO. | OPP100 | OPP50 | UNIT | |||||
---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||||
F12 | tsu(dV-clkH) | Setup time, input data gpmc_ad[15:0] valid before output clock gpmc_clk high | 3.2 | 13.2 | ns | |||
F13 | th(clkH-dV) | Hold time, input data gpmc_ad[15:0] valid after output clock gpmc_clk high | Industrial extended temperature (-40°C to 125°C) |
4.74 | 4.74 | ns | ||
All other temperature ranges | 4.74 | 2.75 | ||||||
F21 | tsu(waitV-clkH) | Setup time, input wait gpmc_wait[x](1) valid before output clock gpmc_clk high | 3.2 | 13.2 | ns | |||
F22 | th(clkH-waitV) | Hold time, input wait gpmc_wait[x](1) valid after output clock gpmc_clk high | Industrial extended temperature (-40°C to 125°C) |
4.74 | 4.74 | ns | ||
All other temperature ranges | 4.74 | 2.75 |
NO. | PARAMETER | OPP100 | OPP50 | UNIT | ||||
---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||||
F0 | 1 / tc(clk) | Frequency(18), output clock gpmc_clk | 100 | 50 | MHz | |||
F1 | tw(clkH) | Typical pulse duration, output clock gpmc_clk high | 0.5P(15) | 0.5P(15) | 0.5P(15) | 0.5P(15) | ns | |
F1 | tw(clkL) | Typical pulse duration, output clock gpmc_clk low | 0.5P(15) | 0.5P(15) | 0.5P(15) | 0.5P(15) | ns | |
tdc(clk) | Duty cycle error, output clock gpmc_clk | –500 | 500 | –500 | 500 | ps | ||
tJ(clk) | Jitter standard deviation(19), output clock gpmc_clk | 33.33 | 33.33 | ps | ||||
tR(clk) | Rise time, output clock gpmc_clk | 2 | 2 | ns | ||||
tF(clk) | Fall time, output clock gpmc_clk | 2 | 2 | ns | ||||
tR(do) | Rise time, output data gpmc_ad[15:0] | 2 | 2 | ns | ||||
tF(do) | Fall time, output data gpmc_ad[15:0] | 2 | 2 | ns | ||||
F2 | td(clkH-csnV) | Delay time, output clock gpmc_clk rising edge to output chip select gpmc_csn[x](14) transition | F(6) - 2.2 | F(6) + 4.5 | F(6) - 3.2 | F(6) + 9.5 | ns | |
F3 | td(clkH-csnIV) | Delay time, output clock gpmc_clk rising edge to output chip select gpmc_csn[x](14) invalid | E(5) – 2.2 | E(5) + 4.5 | E(5) – 3.2 | E(5) + 9.5 | ns | |
F4 | td(aV-clk) | Delay time, output address gpmc_a[27:1] valid to output clock gpmc_clk first edge | B(2) – 4.5 | B(2) + 2.3 | B(2) – 5.5 | B(2) + 12.3 | ns | |
F5 | td(clkH-aIV) | Delay time, output clock gpmc_clk rising edge to output address gpmc_a[27:1] invalid | –2.3 | 4.5 | –3.3 | 14.5 | ns | |
F6 | td(be[x]nV-clk) | Delay time, output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n valid to output clock gpmc_clk first edge | B(2) – 1.9 | B(2) + 2.3 | B(2) – 2.9 | B(2) + 12.3 | ns | |
F7 | td(clkH-be[x]nIV) | Delay time, output clock gpmc_clk rising edge to output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n invalid(11) | D(4) – 2.3 | D(4) + 1.9 | D(4) – 3.3 | D(4) + 6.9 | ns | |
F7 | td(clkL-be[x]nIV) | Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 invalid(12) | D(4) – 2.3 | D(4) + 1.9 | D(4) – 3.3 | D(4) + 6.9 | ns | |
F7 | td(clkL-be[x]nIV) | Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 invalid(13) | D(4) – 2.3 | D(4) + 1.9 | D(4) – 3.3 | D(4) + 11.9 | ns | |
F8 | td(clkH-advn) | Delay time, output clock gpmc_clk rising edge to output address valid and address latch enable gpmc_advn_ale transition | G(7) – 2.3 | G(7) + 4.5 | G(7) – 3.3 | G(7) + 9.5 | ns | |
F9 | td(clkH-advnIV) | Delay time, output clock gpmc_clk rising edge to output address valid and address latch enable gpmc_advn_ale invalid | D(4) – 2.3 | D(4) + 3.5 | D(4) – 3.3 | D(4) + 9.5 | ns | |
F10 | td(clkH-oen) | Delay time, output clock gpmc_clk rising edge to output enable gpmc_oen transition | H(8) – 2.3 | H(8) + 3.5 | H(8) – 3.3 | H(8) + 8.5 | ns | |
F11 | td(clkH-oenIV) | Delay time, output clock gpmc_clk rising edge to output enable gpmc_oen invalid | E(8) – 2.3 | E(8) + 3.5 | E(8) – 3.3 | E(8) + 8.5 | ns | |
F14 | td(clkH-wen) | Delay time, output clock gpmc_clk rising edge to output write enable gpmc_wen transition | I(9) – 2.3 | I(9) + 4.5 | I(9) – 3.3 | I(9) + 9.5 | ns | |
F15 | td(clkH-do) | Delay time, output clock gpmc_clk rising edge to output data gpmc_ad[15:0] transition(11) | J(10) – 2.3 | J(10) + 1.9 | J(10) – 3.3 | J(10) + 6.9 | ns | |
F15 | td(clkL-do) | Delay time, gpmc_clk falling edge to gpmc_ad[15:0] data bus transition(12) | J(10) – 2.3 | J(10) + 1.9 | J(10) – 3.3 | J(10) + 6.9 | ns | |
F15 | td(clkL-do) | Delay time, gpmc_clk falling edge to gpmc_ad[15:0] data bus transition(13) | J(10) – 2.3 | J(10) + 1.9 | J(10) – 3.3 | J(10) + 11.9 | ns | |
F17 | td(clkH-be[x]n) | Delay time, output clock gpmc_clk rising edge to output lower byte enable and command latch enable gpmc_be0n_cle transition(11) | J(10) – 2.3 | J(10) + 1.9 | J(10) – 3.3 | J(10) + 6.9 | ns | |
F17 | td(clkL-be[x]n) | Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 transition(12) | J(10) – 2.3 | J(10) + 1.9 | J(10) – 3.3 | J(10) + 6.9 | ns | |
F17 | td(clkL-be[x]n) | Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 transition(13) | J(10) – 2.3 | J(10) + 1.9 | J(10) – 3.3 | J(10) + 11.9 | ns | |
F18 | tw(csnV) | Pulse duration, output chip select gpmc_csn[x](14) low | Read | A(1) | A(1) | ns | ||
Write | A(1) | A(1) | ns | |||||
F19 | tw(be[x]nV) | Pulse duration, output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n low | Read | C(3) | C(3) | ns | ||
Write | C(3) | C(3) | ns | |||||
F20 | tw(advnV) | Pulse duration, output address valid and address latch enable gpmc_advn_ale low | Read | K(16) | K(16) | ns | ||
Write | K(16) | K(16) | ns |
Table 7-24 and Table 7-25 assume testing over the recommended operating conditions and electrical characteristic conditions shown in Table 7-23 (see Figure 7-22 through Figure 7-27).
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
Input Conditions | |||||
tR | Input signal rise time | 1 | 5 | ns | |
tF | Input signal fall time | 1 | 5 | ns | |
Output Condition | |||||
CLOAD | Output load capacitance | 3 | 30 | pF |
NO. | OPP100 | OPP50 | UNIT | |||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
FI1 | Delay time, output data gpmc_ad[15:0] generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
FI2 | Delay time, input data gpmc_ad[15:0] capture from internal functional clock GPMC_FCLK(3) | 4 | 4 | ns | ||
FI3 | Delay time, output chip select gpmc_csn[x] generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
FI4 | Delay time, output address gpmc_a[27:1] generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
FI5 | Delay time, output address gpmc_a[27:1] valid from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
FI6 | Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle, output upper-byte enable gpmc_be1n generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
FI7 | Delay time, output enable gpmc_oen generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
FI8 | Delay time, output write enable gpmc_wen generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
FI9 | Skew, internal functional clock GPMC_FCLK(3) | 100 | 100 | ps |
NO. | OPP100 | OPP50 | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
FA5(1) | tacc(d) | Data access time | H(5) | H(5) | ns | ||
FA20(2) | tacc1-pgmode(d) | Page mode successive data access time | P(4) | P(4) | ns | ||
FA21(3) | tacc2-pgmode(d) | Page mode first data access time | H(5) | H(5) | ns |
NO. | PARAMETER | OPP100 | OPP50 | UNIT | ||||
---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||||
tR(d) | Rise time, output data gpmc_ad[15:0] | 2 | 2 | ns | ||||
tF(d) | Fall time, output data gpmc_ad[15:0] | 2 | 2 | ns | ||||
FA0 | tw(be[x]nV) | Pulse duration, output lower-byte enable and command latch enable gpmc_be0n_cle, output upper-byte enable gpmc_be1n valid time | Read | N(12) | N(12) | ns | ||
Write | N(12) | N(12) | ||||||
FA1 | tw(csnV) | Pulse duration, output chip select gpmc_csn[x](13) low | Read | A(1) | A(1) | ns | ||
Write | A(1) | A(1) | ||||||
FA3 | td(csnV-advnIV) | Delay time, output chip select gpmc_csn[x](13) valid to output address valid and address latch enable gpmc_advn_ale invalid | Read | B(2) – 0.2 | B(2) + 2.0 | B(2) – 5 | B(2) + 5 | ns |
Write | B(2) – 0.2 | B(2) + 2.0 | B(2) – 5 | B(2) + 5 | ||||
FA4 | td(csnV-oenIV) | Delay time, output chip select gpmc_csn[x](13) valid to output enable gpmc_oen invalid (Single read) | C(3) – 0.2 | C(3) + 2.0 | C(3) – 5 | C(3) + 5 | ns | |
FA9 | td(aV-csnV) | Delay time, output address gpmc_a[27:1] valid to output chip select gpmc_csn[x](13) valid | J(9) – 0.2 | J(9) + 2.0 | J(9) – 5 | J(9) + 5 | ns | |
FA10 | td(be[x]nV-csnV) | Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle, output upper-byte enable gpmc_be1n valid to output chip select gpmc_csn[x](13) valid | J(9) – 0.2 | J(9) + 2.0 | J(9) – 5 | J(9) + 5 | ns | |
FA12 | td(csnV-advnV) | Delay time, output chip select gpmc_csn[x](13) valid to output address valid and address latch enable gpmc_advn_ale valid | K(10) – 0.2 | K(10) + 2.0 | K(10) – 5 | K(10) + 5 | ns | |
FA13 | td(csnV-oenV) | Delay time, output chip select gpmc_csn[x](13) valid to output enable gpmc_oen valid | L(11) – 0.2 | L(11) + 2.0 | L (11) – 5 | L(11) + 5 | ns | |
FA16 | tw(aIV) | Pulse durationm output address gpmc_a[26:1] invalid between 2 successive read and write accesses | G(7) | G(7) | ns | |||
FA18 | td(csnV-oenIV) | Delay time, output chip select gpmc_csn[x](13) valid to output enable gpmc_oen invalid (Burst read) | I(8) – 0.2 | I(8) + 2.0 | I(8) – 5 | I(8) + 5 | ns | |
FA20 | tw(aV) | Pulse duration, output address gpmc_a[27:1] valid - 2nd, 3rd, and 4th accesses | D(4) | D(4) | ns | |||
FA25 | td(csnV-wenV) | Delay time, output chip select gpmc_csn[x](13) valid to output write enable gpmc_wen valid | E(5) – 0.2 | E(5) + 2.0 | E(5) – 5 | E(5) + 5 | ns | |
FA27 | td(csnV-wenIV) | Delay time, output chip select gpmc_csn[x](13) valid to output write enable gpmc_wen invalid | F(6) – 0.2 | F(6) + 2.0 | F(6) – 5 | F(6) + 5 | ns | |
FA28 | td(wenV-dV) | Delay time, output write enable gpmc_ wen valid to output data gpmc_ad[15:0] valid | 2.0 | 5 | ns | |||
FA29 | td(dV-csnV) | Delay time, output data gpmc_ad[15:0] valid to output chip select gpmc_csn[x](13) valid | J(9) – 0.2 | J(9) + 2.0 | J(9) – 5 | J(9) + 5 | ns | |
FA37 | td(oenV-aIV) | Delay time, output enable gpmc_oen valid to output address gpmc_ad[15:0] phase end | 2.0 | 5 | ns |
Table 7-28 and Table 7-29 assume testing over the recommended operating conditions and electrical characteristic conditions shown in Table 7-27 (see Figure 7-28 through Figure 7-31).
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Input Conditions | |||||
tR | Input signal rise time | 1 | 5 | ns | |
tF | Input signal fall time | 1 | 5 | ns | |
Output Condition | |||||
CLOAD | Output load capacitance | 3 | 30 | pF |
NO. | OPP100 | OPP50 | UNIT | |||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
GNFI1 | Delay time, output data gpmc_ad[15:0] generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
GNFI2 | Delay time, input data gpmc_ad[15:0] capture from internal functional clock GPMC_FCLK(3) | 4.0 | 4.0 | ns | ||
GNFI3 | Delay time, output chip select gpmc_csn[x] generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
GNFI4 | Delay time, output address valid and address latch enable gpmc_advn_ale generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
GNFI5 | Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
GNFI6 | Delay time, output enable gpmc_oen generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
GNFI7 | Delay time, output write enable gpmc_wen generation from internal functional clock GPMC_FCLK(3) | 6.5 | 6.5 | ns | ||
GNFI8 | Skew, functional clock GPMC_FCLK(3) | 100 | 100 | ps |
NO. | OPP100 | OPP50 | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
GNF12(1) | tacc(d) | Access time, input data gpmc_ad[15:0] | J(2) | J(2) | ns |
NO. | PARAMETER | OPP100 | OPP50 | UNIT | |||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
tR(d) | Rise time, output data gpmc_ad[15:0] | 2 | 2 | ns | |||
tF(d) | Fall time, output data gpmc_ad[15:0] | 2 | 2 | ns | |||
GNF0 | tw(wenV) | Pulse duration, output write enable gpmc_wen valid | A(1) | A(1) | ns | ||
GNF1 | td(csnV-wenV) | Delay time, output chip select gpmc_csn[x](13) valid to output write enable gpmc_wen valid | B(2) – 0.2 | B(2) + 2.0 | B(2) – 5 | B(2) + 5 | ns |
GNF2 | tw(cleH-wenV) | Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle high to output write enable gpmc_wen valid | C(3) – 0.2 | C(3) + 2.0 | C(3) – 5 | C(3) + 5 | ns |
GNF3 | tw(wenV-dV) | Delay time, output data gpmc_ad[15:0] valid to output write enable gpmc_wen valid | D(4) – 0.2 | D(4) + 2.0 | D(4) – 5 | D(4) + 5 | ns |
GNF4 | tw(wenIV-dIV) | Delay time, output write enable gpmc_wen invalid to output data gpmc_ad[15:0] invalid | E(5) – 0.2 | E(5) + 5 | E(5) – 5 | E(5) + 5 | ns |
GNF5 | tw(wenIV-cleIV) | Delay time, output write enable gpmc_wen invalid to output lower-byte enable and command latch enable gpmc_be0n_cle invalid | F(6) – 0.2 | F(6) + 2.0 | F(6) – 5 | F(6) + 5 | ns |
GNF6 | tw(wenIV-csnIV) | Delay time, output write enable gpmc_wen invalid to output chip select gpmc_csn[x](13) invalid | G(7) – 0.2 | G(7) + 2.0 | G(7) – 5 | G(7) + 5 | ns |
GNF7 | tw(aleH-wenV) | Delay time, output address valid and address latch enable gpmc_advn_ale high to output write enable gpmc_wen valid | C(3) – 0.2 | C(3) + 2.0 | C(3) – 5 | C(3) + 5 | ns |
GNF8 | tw(wenIV-aleIV) | Delay time, output write enable gpmc_wen invalid to output address valid and address latch enable gpmc_advn_ale invalid | F(6) – 0.2 | F(6) + 2.0 | F(6) – 5 | F(6) + 5 | ns |
GNF9 | tc(wen) | Cycle time, write | H(8) | H(8) | ns | ||
GNF10 | td(csnV-oenV) | Delay time, output chip select gpmc_csn[x](13) valid to output enable gpmc_oen valid | I(9) – 0.2 | I(9) + 2.0 | I(9) – 5 | I(9) + 5 | ns |
GNF13 | tw(oenV) | Pulse duration, output enable gpmc_oen valid | K(10) | K(10) | ns | ||
GNF14 | tc(oen) | Cycle time, read | L(11) | L(11) | ns | ||
GNF15 | tw(oenIV-csnIV) | Delay time, output enable gpmc_oen invalid to output chip select gpmc_csn[x](13) invalid | M(12) – 0.2 | M(12) + 2.0 | M(12) – 5 | M(12) + 5 | ns |
The device has a dedicated interface to mDDR(LPDDR), DDR2, DDR3, and DDR3L SDRAM. It supports JEDEC standard compliant mDDR(LPDDR), DDR2, DDR3, and DDR3L SDRAM devices with a 16-bit data path to external SDRAM memory.
For more details on the mDDR(LPDDR), DDR2, DDR3, and DDR3L memory interface, see the EMIF section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
It is common to find industry references to mobile double data rate (mDDR) when discussing JEDEC defined low-power double-data rate (LPDDR) memory devices. The following guidelines use LPDDR when referencing JEDEC defined low-power double-data rate memory devices.
TI only supports board designs that follow the guidelines outlined in this document. The switching characteristics and the timing diagram for the LPDDR memory interface are shown in Table 7-31 and Figure 7-32.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | tc(DDR_CK)
tc(DDR_CKn) |
Cycle time, DDR_CK and DDR_CKn | 5 | (1) | ns |
This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the need for a complex timing closure process. For more information regarding the guidelines for using this LPDDR specification, see Understanding TI’s PCB Routing Rule-Based DDR Timing Specification. This application report provides generic guidelines and approach. All the specifications provided in the data manual take precedence over the generic guidelines and must be adhered to for a reliable LPDDR interface operation.
Figure 7-33 shows the schematic connections for 16-bit interface on the AM335x device using one x16 LPDDR device. The AM335x LPDDR memory interface only supports 16-bit-wide mode of operation. The AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and one load connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see Section 7.7.2.1.2.8.
Table 7-32 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface. Generally, the LPDDR interface is compatible with x16 LPDDR400 speed grade LPDDR devices.
NO. | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
1 | JEDEC LPDDR device speed grade | LPDDR400 | ||
2 | JEDEC LPDDR device bit width | x16 | x16 | Bits |
3 | JEDEC LPDDR device count | 1 | Devices | |
4 | JEDEC LPDDR device terminal count | 60 | Terminals |
The minimum stackup required for routing the AM335x device is a 4-layer stackup as shown in Table 7-33. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
LAYER | TYPE | DESCRIPTION |
---|---|---|
1 | Signal | Top signal routing |
2 | Plane | Ground |
3 | Plane | Split Power Plane |
4 | Signal | Bottom signal routing |
Complete stackup specifications are provided in Table 7-34.
NO. | PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | PCB routing and plane layers | 4 | ||||
2 | Signal routing layers | 2 | ||||
3 | Full ground layers under LPDDR routing region | 1 | ||||
4 | Number of ground plane cuts allowed within LPDDR routing region | 0 | ||||
5 | Full VDDS_DDR power reference layers under LPDDR routing region | 1 | ||||
6 | Number of layers between LPDDR routing layer and reference ground plane | 0 | ||||
7 | PCB routing feature size | 4 | mils | |||
8 | PCB trace width, w | 4 | mils | |||
9 | PCB BGA escape via pad size(2) | 18 | 20 | mils | ||
10 | PCB BGA escape via hole size(2) | 10 | mils | |||
11 | Single-ended impedance, Zo(3) | 50 | 75 | Ω | ||
12 | Impedance control(4)(5) | Zo-5 | Zo | Zo+5 | Ω |
Figure 7-34 shows the required placement for the LPDDR devices. The dimensions for this figure are defined in Table 7-35. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory LPDDR systems, the second LPDDR device is omitted from the placement.
NO. | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
1 | X(2)(3) | 1750 | mils | |
2 | Y(2)(3) | 1280 | mils | |
3 | Y Offset(2)(3)(4) | 650 | mils | |
4 | Clearance from non-LPDDR signal to LPDDR keepout region(5)(6) | 4 | w |
The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR keepout region is defined for this purpose and is shown in Figure 7-35. This region should encompass all LPDDR circuitry and the region size varies with component placement and LPDDR routing. Additional clearances required for the keepout region are shown in Table 7-35. Non-LPDDR signals must not be routed on the same signal layer as LPDDR signals within the LPDDR keepout region. Non-LPDDR signals may be routed in the region provided they are routed on layers separated from LPDDR signal layers by a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition, the VDDS_DDR power plane should cover the entire keepout region.
Bulk bypass capacitors are required for moderate speed bypassing of the LPDDR and other circuitry. Table 7-36 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the AM335x LPDDR interface and LPDDR devices. Additional bulk bypass capacitance may be needed for other circuitry.
NO. | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
1 | AM335x VDDS_DDR bulk bypass capacitor count | 1 | Devices | |
2 | AM335x VDDS_DDR bulk bypass total capacitance | 10 | μF | |
3 | LPDDR#1 bulk bypass capacitor count | 1 | Devices | |
4 | LPDDR#1 bulk bypass total capacitance | 10 | μF | |
5 | LPDDR#2 bulk bypass capacitor count(2) | 1 | Devices | |
6 | LPDDR#2 bulk bypass total capacitance(2) | 10 | μF |
High-speed (HS) bypass capacitors are critical for proper LPDDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device LPDDR power, and the AM335x device LPDDR ground connections. Table 7-37 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB.
NO. | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
1 | HS bypass capacitor package size(1) | 0402 | 10 mils | |
2 | Distance from HS bypass capacitor to device being bypassed | 250 | mils | |
3 | Number of connection vias for each HS bypass capacitor(2) | 2 | Vias | |
4 | Trace length from bypass capacitor contact to connection via | 30 | mils | |
5 | Number of connection vias for each AM335x VDDS_DDR and VSS terminal | 1 | Vias | |
6 | Trace length from AM335x VDDS_DDR and VSS terminal to connection via | 35 | mils | |
7 | Number of connection vias for each LPDDR device power and ground terminal | 1 | Vias | |
8 | Trace length from LPDDR device power and ground terminal to connection via | 35 | mils | |
9 | AM335x VDDS_DDR HS bypass capacitor count(3) | 10 | Devices | |
10 | AM335x VDDS_DDR HS bypass capacitor total capacitance | 0.6 | μF | |
11 | LPDDR device HS bypass capacitor count(3)(4) | 8 | Devices | |
12 | LPDDR device HS bypass capacitor total capacitance(4) | 0.4 | μF |
Table 7-38 lists the clock net classes for the LPDDR interface. Table 7-39 lists the signal net classes, and associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the termination and routing rules that follow.
CLOCK NET CLASS | AM335x PIN NAMES |
---|---|
CK | DDR_CK and DDR_CKn |
DQS0 | DDR_DQS0 |
DQS1 | DDR_DQS1 |
SIGNAL NET CLASS | ASSOCIATED CLOCK NET CLASS |
AM335x PIN NAMES |
---|---|---|
ADDR_CTRL | CK | DDR_BA[1:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn, DDR_WEn, DDR_CKE |
DQ0 | DQS0 | DDR_D[7:0], DDR_DQM0 |
DQ1 | DQS1 | DDR_D[15:8], DDR_DQM1 |
There is no specific need for adding terminations on the LPDDR interface. However, system designers may evaluate the need for serial terminators for EMI and overshoot reduction. Placement of serial terminations for DQS[x] and DQ[x] net class signals should be determined based on PCB analysis. Placement of serial terminations for ADDR_CTRL net class signals should be close to the AM335x device. Table 7-40 shows the specifications for the serial terminators in such cases.
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
1 | CK net class(1) | 0 | 22 | Zo(2) | Ω |
2 | ADDR_CTRL net class(1)(3)(4) | 0 | 22 | Zo(2) | Ω |
3 | DQS0, DQS1, DQ0, and DQ1 net classes | 0 | 22 | Zo(2) | Ω |
Figure 7-36 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of signal path AB and AC should be minimized with emphasis to minimize lengths C and D such that length A is the majority of the total length of signal path AB and AC.
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
1 | Center-to-center CK spacing | 2w | |||
2 | CK differential pair skew length mismatch(2)(3) | 25 | mils | ||
3 | CK B-to-CK C skew length mismatch | 25 | mils | ||
4 | Center-to-center CK to other LPDDR trace spacing(4) | 4w | |||
5 | CK and ADDR_CTRL nominal trace length(5) | CACLM-50 | CACLM | CACLM+50 | mils |
6 | ADDR_CTRL-to-CK skew length mismatch | 100 | mils | ||
7 | ADDR_CTRL-to-ADDR_CTRL skew length mismatch | 100 | mils | ||
8 | Center-to-center ADDR_CTRL to other LPDDR trace spacing(4) | 4w | |||
9 | Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(4) | 3w | |||
10 | ADDR_CTRL A-to-B and ADDR_CTRL A-to-C skew length mismatch(2) | 100 | mils | ||
11 | ADDR_CTRL B-to-C skew length mismatch | 100 | mils |
Figure 7-37 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended.
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
1 | Center-to-center DQS[x] spacing | 2w | |||
2 | Center-to-center DDR_DQS[x] to other LPDDR trace spacing(2) | 4w | |||
3 | DQS[x] and DQ[x] nominal trace length(3) | DQLM-50 | DQLM | DQLM+50 | mils |
4 | DQ[x]-to-DQS[x] skew length mismatch(3) | 100 | mils | ||
5 | DQ[x]-to-DQ[x] skew length mismatch(3) | 100 | mils | ||
6 | Center-to-center DQ[x] to other LPDDR trace spacing(2)(4) | 4w | |||
7 | Center-to-center DQ[x] to other DQ[x] trace spacing(2)(5) | 3w |
TI only supports board designs that follow the guidelines outlined in this document. Table 7-43 and Figure 7-38 show the switching characteristics and timing diagram for the DDR2 memory interface.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | tc(DDR_CK)
tc(DDR_CKn) |
Cycle time, DDR_CK and DDR_CKn | 3.75 | 8(1) | ns |
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need for a complex timing closure process. For more information regarding the guidelines for using this DDR2 specification, see Understanding TI’s PCB Routing Rule-Based DDR Timing Specification. This application report provides generic guidelines and approach. All the specifications provided in the data manual take precedence over the generic guidelines and must be adhered to for a reliable DDR2 interface operation.
Figure 7-39 shows the schematic connections for 16-bit interface on the AM335x device using one x16 DDR2 device and Figure 7-40 shows the schematic connections for 16-bit interface on the AM335x device using two x8 DDR2 devices. The AM335x DDR2 memory interface only supports 16-bit-wide mode of operation. The AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and two loads connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see Section 7.7.2.2.2.8.
Table 7-44 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface. Generally, the DDR2 interface is compatible with x16 or x8 DDR2-533 speed grade DDR2 devices.
NO. | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
1 | JEDEC DDR2 device speed grade(2) | DDR2-533 | ||
2 | JEDEC DDR2 device bit width | x8 | x16 | bits |
3 | JEDEC DDR2 device count | 1 | 2 | devices |
4 | JEDEC DDR2 device terminal count(3) | 60 | 84 | terminals |
The minimum stackup required for routing the AM335x device is a 4-layer stackup as shown in Table 7-45. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
LAYER | TYPE | DESCRIPTION |
---|---|---|
1 | Signal | Top signal routing |
2 | Plane | Ground |
3 | Plane | Split power plane |
4 | Signal | Bottom signal routing |
Complete stackup specifications are provided in Table 7-46.
NO. | PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | PCB routing and plane layers | 4 | ||||
2 | Signal routing layers | 2 | ||||
3 | Full ground layers under DDR2 routing region | 1 | ||||
4 | Number of ground plane cuts allowed within DDR2 routing region | 0 | ||||
5 | Full VDDS_DDR power reference layers under DDR2 routing region | 1 | ||||
6 | Number of layers between DDR2 routing layer and reference ground plane | 0 | ||||
7 | PCB routing feature size | 4 | mils | |||
8 | PCB trace width, w | 4 | mils | |||
9 | PCB BGA escape via pad size(2) | 18 | 20 | mils | ||
10 | PCB BGA escape via hole size(2) | 10 | mils | |||
11 | Single-ended impedance, Zo(3) | 50 | 75 | Ω | ||
12 | Impedance control(4)(5) | Zo-5 | Zo | Zo+5 | Ω |
Figure 7-41 shows the required placement for the DDR2 devices. The dimensions for this figure are defined in Table 7-47. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the placement.
NO. | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
1 | X(2)(3) | 1750 | mils | |
2 | Y(2)(3) | 1280 | mils | |
3 | Y Offset(2)(3)(4) | 650 | mils | |
4 | Clearance from non-DDR2 signal to DDR2 keepout region(5)(6) | 4 | w |
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keepout region is defined for this purpose and is shown in Figure 7-42. This region should encompass all DDR2 circuitry and the region size varies with component placement and DDR2 routing. Additional clearances required for the keepout region are shown in Table 7-47. Non-DDR2 signals must not be routed on the same signal layer as DDR2 signals within the DDR2 keepout region. Non-DDR2 signals may be routed in the region provided they are routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition, the VDDS_DDR power plane should cover the entire keepout region.
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry. Table 7-48 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the AM335x DDR2 interface and DDR2 devices. Additional bulk bypass capacitance may be needed for other circuitry.
NO. | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
1 | AM335x VDDS_DDR bulk bypass capacitor count | 1 | devices | |
2 | AM335x VDDS_DDR bulk bypass total capacitance | 10 | μF | |
3 | DDR2 number 1 bulk bypass capacitor count | 1 | devices | |
4 | DDR2 number 1 bulk bypass total capacitance | 10 | μF | |
5 | DDR2 number 2 bulk bypass capacitor count(2) | 1 | devices | |
6 | DDR2 number 2 bulk bypass total capacitance(2) | 10 | μF |
HS bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device DDR2 power, and the AM335x device DDR2 ground connections. Table 7-49 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB.
NO. | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
1 | HS bypass capacitor package size(1) | 0402 | 10 mils | |
2 | Distance from HS bypass capacitor to device being bypassed | 250 | mils | |
3 | Number of connection vias for each HS bypass capacitor(2) | 2 | vias | |
4 | Trace length from bypass capacitor contact to connection via | 30 | mils | |
5 | Number of connection vias for each AM335x VDDS_DDR and VSS terminal | 1 | vias | |
6 | Trace length from AM335x VDDS_DDR and VSS terminal to connection via | 35 | mils | |
7 | Number of connection vias for each DDR2 device power and ground terminal | 1 | vias | |
8 | Trace length from DDR2 device power and ground terminal to connection via | 35 | mils | |
9 | AM335x VDDS_DDR HS bypass capacitor count(3) | 10 | devices | |
10 | AM335x VDDS_DDR HS bypass capacitor total capacitance | 0.6 | μF | |
11 | DDR2 device HS bypass capacitor count(3)(4) | 8 | devices | |
12 | DDR2 device HS bypass capacitor total capacitance(4) | 0.4 | μF |
Table 7-50 lists the clock net classes for the DDR2 interface. Table 7-51 lists the signal net classes, and associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the termination and routing rules that follow.
Signal terminations are required on the CK and ADDR_CTRL net class signals. Serial terminations should be used on the CK and ADDR_CTRL lines and is the preferred termination scheme. On-device terminations (ODTs) are required on the DQS[x] and DQ[x] net class signals. They should be enabled to ensure signal integrity. Table 7-52 shows the specifications for the series terminators. Placement of serial terminations for ADDR_CTRL net class signals should be close to the AM335x device.
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
1 | CK net class(1) | 0 | 10 | Ω | |
2 | ADDR_CTRL net class(1)(2)(3) | 0 | 22 | Zo(4) | Ω |
3 | DQS0, DQS1, DQ0, and DQ1 net classes(5) | N/A | N/A | Ω |
If the DDR2 interface is operated at a lower frequency (<200-MHz clock rate), on-device terminations are not specifically required for the DQS[x] and DQ[x] net class signals and serial terminations for the CK and ADDR_CTRL net class signals are not mandatory. System designers may evaluate the need for serial terminators for EMI and overshoot reduction. Placement of serial terminations for DQS[x] and DQ[x] net class signals should be determined based on PCB analysis. Placement of serial terminations for ADDR_CTRL net class signals should be close to the AM335x device. Table 7-53 shows the specifications for the serial terminators in such cases.
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
1 | CK net class(1) | 0 | 22 | Zo(2) | Ω |
2 | ADDR_CTRL net class(1)(3)(4) | 0 | 22 | Zo(2) | Ω |
3 | DQS0, DQS1, DQ0, and DQ1 net classes | 0 | 22 | Zo(2) | Ω |
DDR_VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM335x device. DDR_VREF is intended to be half the DDR2 power supply voltage and should be created using a resistive divider as shown in Figure 7-39 and Figure 7-40. TI does not recommend other methods of creating DDR_VREF. Figure 7-43 shows the layout guidelines for DDR_VREF.
Figure 7-44 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of signal path AB and AC should be minimized with emphasis to minimize lengths C and D such that length A is the majority of the total length of signal path AB and AC.
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
1 | Center-to-center CK spacing | 2w | |||
2 | CK differential pair skew length mismatch(2)(3) | 25 | mils | ||
3 | CK B-to-CK C skew length mismatch | 25 | mils | ||
4 | Center-to-center CK to other DDR2 trace spacing(4) | 4w | |||
5 | CK and ADDR_CTRL nominal trace length(5) | CACLM-50 | CACLM | CACLM+50 | mils |
6 | ADDR_CTRL-to-CK skew length mismatch | 100 | mils | ||
7 | ADDR_CTRL-to-ADDR_CTRL skew length mismatch | 100 | mils | ||
8 | Center-to-center ADDR_CTRL to other DDR2 trace spacing(4) | 4w | |||
9 | Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(4) | 3w | |||
10 | ADDR_CTRL A-to-B and ADDR_CTRL A-to-C skew length mismatch(2) | 100 | mils | ||
11 | ADDR_CTRL B-to-C skew length mismatch | 100 | mils |
Figure 7-45 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended.
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
1 | Center-to-center DQS[x] spacing | 2w | |||
2 | DQS[x] differential pair skew length mismatch(2) | 25 | mils | ||
3 | Center-to-center DDR_DQS[x] to other DDR2 trace spacing(3) | 4w | |||
4 | DQS[x] and DQ[x] nominal trace length(4) | DQLM-50 | DQLM | DQLM+50 | mils |
5 | DQ[x]-to-DQS[x] skew length mismatch(4) | 100 | mils | ||
6 | DQ[x]-to-DQ[x] skew length mismatch(4) | 100 | mils | ||
7 | Center-to-center DQ[x] to other DDR2 trace spacing(3)(5) | 4w | |||
8 | Center-to-center DQ[x] to other DQ[x] trace spacing(3)(6) | 3w |
NOTE
All references to DDR3 in this section apply to DDR3 and DDR3L devices, unless otherwise noted.
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory interface are shown in Table 7-56 and Figure 7-46.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | tc(DDR_CK)
tc(DDR_CKn) |
Cycle time, DDR_CK and DDR_CKn | 2.5 | 3.3(1) | ns |
This specification only covers AM335x PCB designs that use DDR3 memory. Designs using DDR2 memory should use the DDR2 routing guidleines described in Section 7.7.2.2. While similar, the two memory systems have different requirements. It is currently not possible to design one PCB that meets the requirements of both DDR2 and DDR3.
Because there are several possible combinations of device counts and single-side or dual-side mounting, Table 7-57 summarizes the supported device configurations.
NUMBER OF DDR3 DEVICES | DDR3 DEVICE WIDTH (BITS) | MIRRORED? | DDR3 EMIF WIDTH (BITS) |
---|---|---|---|
1 | 16 | N | 16 |
2 | 8 | Y(1) | 16 |
This section provides the timing specification for the DDR3 interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR3 memory system without the need for a complex timing closure process. For more information regarding the guidelines for using this DDR3 specification, see Understanding TI's PCB Routing Rule-Based DDR Timing Specification. This application report provides generic guidelines and approach. All the specifications provided in the data manual take precedence over the generic guidelines and must be adhered to for a reliable DDR3 interface operation.
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used. Figure 7-47 shows the schematic connections for 16-bit interface on the AM335x device using one x16 DDR3 device and Figure 7-49 shows the schematic connections for 16-bit interface on the AM335x device using two x8 DDR3 devices. The AM335x DDR3 memory interface only supports 16-bit wide mode of operation. The AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and two loads connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see Section 7.7.2.3.3.8.
Table 7-58 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
NO. | PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT |
---|---|---|---|---|---|
1 | JEDEC DDR3 device speed grade | tC(DDR_CK) and tC(DDR_CKn) = 3.3 ns | DDR3-800 | ||
tC(DDR_CK) and tC(DDR_CKn) = 2.5 ns | DDR3-1600 | ||||
2 | JEDEC DDR3 device bit width | x8 | x16 | bits | |
3 | JEDEC DDR3 device count(1) | 1 | 2 | devices |
The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 7-59. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
LAYER | TYPE | DESCRIPTION |
---|---|---|
1 | Signal | Top signal routing |
2 | Plane | Ground |
3 | Plane | Split Power Plane |
4 | Signal | Bottom signal routing |
NO. | PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | PCB routing and plane layers | 4 | ||||
2 | Signal routing layers | 2 | ||||
3 | Full ground reference layers under DDR3 routing region(2) | 1 | ||||
4 | Full VDDS_DDR power reference layers under the DDR3 routing region(2) | 1 | ||||
5 | Number of reference plane cuts allowed within DDR3 routing region(3) | 0 | ||||
6 | Number of layers between DDR3 routing layer and reference plane(4) | 0 | ||||
7 | PCB routing feature size | 4 | mils | |||
8 | PCB trace width, w | 4 | mils | |||
9 | PCB BGA escape via pad size(5) | 18 | 20 | mils | ||
10 | PCB BGA escape via hole size | 10 | mils | |||
11 | Single-ended impedance, Zo(6) | 50 | 75 | Ω | ||
12 | Impedance control(7)(8) | Zo-5 | Zo | Zo+5 | Ω |
Figure 7-50 shows the required placement for the AM335x device as well as the DDR3 devices. The dimensions for this figure are defined in Table 7-61. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space.
NO. | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
1 | X1(2)(3)(4) | 1000 | mils | |
2 | X2(2)(3) | 600 | mils | |
3 | Y Offset(2)(3)(4) | 1500 | mils | |
4 | Clearance from non-DDR3 signal to DDR3 keepout region(5)(6) | 4 | w |
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout region is defined for this purpose and is shown in Figure 7-51. This region should encompass all DDR3 circuitry and the region size varies with component placement and DDR3 routing. Additional clearances required for the keepout region are shown in Table 7-61. Non-DDR3 signals must not be routed on the same signal layer as DDR3 signals within the DDR3 keepout region. Non-DDR3 signals may be routed in the region provided they are routed on layers separated from DDR3 signal layers by a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition, the VDDS_DDR power plane should cover the entire keepout region.
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. Table 7-62 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the AM335x DDR3 interface and DDR3 devices. Additional bulk bypass capacitance may be needed for other circuitry.
NO. | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
1 | AM335x VDDS_DDR bulk bypass capacitor count | 2 | devices | |
2 | AM335x VDDS_DDR bulk bypass total capacitance | 20 | μF | |
3 | DDR3 number 1 bulk bypass capacitor count | 2 | devices | |
4 | DDR3 number 1 bulk bypass total capacitance | 20 | μF | |
5 | DDR3 number 2 bulk bypass capacitor count(2) | 2 | devices | |
6 | DDR3 number 2 bulk bypass total capacitance(2) | 20 | μF |
High-speed (HS) bypass capacitors are critical for proper DDR3 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device DDR3 power, and the AM335x device DDR3 ground connections. Table 7-63 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
1 | HS bypass capacitor package size(1) | 0201 | 0402 | 10 mils | |
2 | Distance, HS bypass capacitor to AM335x VDDS_DDR and VSS terminal being bypassed(2)(3)(4) | 400 | mils | ||
3 | AM335x VDDS_DDR HS bypass capacitor count | 20 | devices | ||
4 | AM335x VDDS_DDR HS bypass capacitor total capacitance | 1 | μF | ||
5 | Trace length from AM335x VDDS_DDR and VSS terminal to connection via(2) | 35 | 70 | mils | |
6 | Distance, HS bypass capacitor to DDR3 device being bypassed(5) | 150 | mils | ||
7 | DDR3 device HS bypass capacitor count(6) | 12 | devices | ||
8 | DDR3 device HS bypass capacitor total capacitance(6) | 0.85 | μF | ||
9 | Number of connection vias for each HS bypass capacitor(7)(8) | 2 | vias | ||
10 | Trace length from bypass capacitor connect to connection via(2)(8) | 35 | 100 | mils | |
11 | Number of connection vias for each DDR3 device power and ground terminal(9) | 1 | vias | ||
12 | Trace length from DDR3 device power and ground terminal to connection via(2)(7) | 35 | 60 | mils |
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals hopping from one signal layer to another. The bypass capacitor here provides a path for the return current to hop planes along with the signal. As many of these return current bypass capacitors should be used as possible. Because these are returns for signal current, the signal via size may be used for these capacitors.
Table 7-64 lists the clock net classes for the DDR3 interface. Table 7-65 lists the signal net classes, and associated clock net classes, for signals in the DDR3 interface. These net classes are used for the termination and routing rules that follow.
CLOCK NET CLASS | AM335x PIN NAMES |
---|---|
CK | DDR_CK and DDR_CKn |
DQS0 | DDR_DQS0 and DDR_DQSn0 |
DQS1 | DDR_DQS1 and DDR_DQSn1 |
SIGNAL NET CLASS | ASSOCIATED CLOCK NET CLASS | AM335x PIN NAMES |
---|---|---|
ADDR_CTRL | CK | DDR_BA[2:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn, DDR_WEn, DDR_CKE, DDR_ODT |
DQ0 | DQS0 | DDR_D[7:0], DDR_DQM0 |
DQ1 | DQS1 | DDR_D[15:8], DDR_DQM1 |
Signal terminations are required for the CK and ADDR_CTRL net class signals. On-device terminations (ODTs) are required on the DQS[x] and DQ[x] net class signals. Detailed termination specifications are covered in the routing rules in the following sections.
Figure 7-48 provides an example DDR3 schematic with a single 16-bit DDR3 memory device that does not have VTT termination on the address and control signals. A typical DDR3 point-to-point topology may provide acceptable signal integrity without VTT termination. System performance should be verified by performing signal integrity analysis using specific PCB design details before implementing this topology.
DDR_VREF is used as a reference by the input buffers of the DDR3 memories as well as the AM335x device. DDR_VREF is intended to be half the DDR3 power supply voltage and is typically generated with a voltage divider connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to accommodate routing congestion.
Like DDR_VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike DDR_VREF, VTT is expected to source and sink current, specifically the termination current for the ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power sub-plane. VTT should be bypassed near the terminator resistors.
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew between them. CK is a bit more complicated because it runs at a higher transition rate and is differential. The following subsections show the topology and routing for various DDR3 configurations for CK and ADDR_CTRL. The figures in the following subsections define the terms for the routing specification detailed in Table 7-66.
Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as one 16-bit bank. These two devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
Figure 7-52 shows the topology of the CK net classes and Figure 7-53 shows the topology for the corresponding ADDR_CTRL net classes.
Figure 7-54 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 7-55 shows the corresponding ADDR_CTRL routing.
To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased routing and assembly complexity. Figure 7-56 and Figure 7-57 show the routing for CK and ADDR_CTRL, respectively, for two DDR3 devices mirrored in a single-pair configuration.
One DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged as one 16-bit bank.
Figure 7-58 shows the topology of the CK net classes and Figure 7-59 shows the topology for the corresponding ADDR_CTRL net classes.
Figure 7-60 shows the CK routing for one DDR3 device. Figure 7-61 shows the corresponding ADDR_CTRL routing.
No matter the number of DDR3 devices used, the data line topology is always point to point, so its definition is simple.
DQS[x] lines are point-to-point differential, and DQ[x] lines are point-to-point single-ended. Figure 7-62 and Figure 7-63 show these topologies.
Figure 7-64 and Figure 7-65 show the DQS[x] and DQ[x] routing.
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. A metric to establish this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the length between the points when connecting them only with horizontal or vertical segments. A reasonable trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address Control Longest Manhattan distance.
Given the clock and address pin locations on the AM335x device and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 7-66 shows this distance for two loads. The specifications on the lengths of the transmission lines for the address bus are determined from this distance. CACLM is determined similarly for other address bus configurations; that is, it is based on the longest net of the CK and ADDR_CTRL net class. For CK and ADDR_CTRL routing, these specifications are contained in Table 7-66.
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
1 | A1 + A2 length | 2500 | mils | ||
2 | A1 + A2 skew | 25 | mils | ||
3 | A3 length | 660 | mils | ||
4 | A3 skew(4) | 25 | mils | ||
5 | A3 skew(5) | 125 | mils | ||
6 | AS length | 100 | mils | ||
7 | AS skew | 25 | mils | ||
8 | AS+ and AS– length | 70 | mils | ||
9 | AS+ and AS– skew | 5 | mils | ||
10 | AT length(6) | 500 | mils | ||
11 | AT skew(7) | 100 | mils | ||
12 | AT skew(8) | 5 | mils | ||
13 | CK and ADDR_CTRL nominal trace length(9) | CACLM-50 | CACLM | CACLM+50 | mils |
14 | Center-to-center CK to other DDR3 trace spacing(10) | 4w | |||
15 | Center-to-center ADDR_CTRL to other DDR3 trace spacing(10)(11) | 4w | |||
16 | Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(10) | 3w | |||
17 | CK center-to-center spacing(12) | ||||
18 | CK spacing to other net(10) | 4w | |||
19 | Rcp(13) | Zo-1 | Zo | Zo+1 | Ω |
20 | Rtt(13)(14) | Zo-5 | Zo | Zo+5 | Ω |
Skew within the DQS[x] and DQ[x] net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. DQLMn is defined as DQ Longest Manhattan distance n, where n is the byte number. For a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.
NOTE
Matching the lengths across all bytes is not required, nor is it recommended. Length matching is only required within each byte.
Given the DQS[x] and DQ[x] pin locations on the AM335x device and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 7-67 shows this distance for a two-load case. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. For DQS[x] and DQ[x] routing, these specifications are contained in Table 7-67.
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
1 | DQ0 nominal length(3)(4) | DQLM0 | mils | ||
2 | DQ1 nominal length(3)(5) | DQLM1 | mils | ||
3 | DQ[x] skew(6) | 25 | mils | ||
4 | DQS[x] skew | 5 | mils | ||
5 | DQS[x]-to-DQ[x] skew(6)(7) | 25 | mils | ||
6 | Center-to-center DQ[x] to other DDR3 trace spacing(8)(9) | 4w | |||
7 | Center-to-center DQ[x] to other DQ[x] trace spacing(8)(10) | 3w | |||
8 | DQS[x] center-to-center spacing(11) | ||||
9 | DQS[x] center-to-center spacing to other net(8) | 4w |
For more information, see the Inter-Integrated Circuit (I2C) section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
PARAMETER | STANDARD MODE | FAST MODE | UNIT | |||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
Output Condition | ||||||
Cb | Capacitive load for each bus line | 400 | 400 | pF |
NO. | STANDARD MODE | FAST MODE | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
1 | tc(SCL) | Cycle time, SCL | 10 | 2.5 | µs | ||
2 | tsu(SCLH-SDAL) | Setup time, SCL high before SDA low (for a repeated START condition) | 4.7 | 0.6 | µs | ||
3 | th(SDAL-SCLL) | Hold time, SCL low after SDA low (for a START and a repeated START condition) | 4 | 0.6 | µs | ||
4 | tw(SCLL) | Pulse duration, SCL low | 4.7 | 1.3 | µs | ||
5 | tw(SCLH) | Pulse duration, SCL high | 4 | 0.6 | µs | ||
6 | tsu(SDAV-SCLH) | Setup time, SDA valid before SCL high | 250 | 100(1) | ns | ||
7 | th(SCLL-SDAV) | Hold time, SDA valid after SCL low | 0(2) | 3.45(3) | 0(2) | 0.9(3) | µs |
8 | tw(SDAH) | Pulse duration, SDA high between STOP and START conditions | 4.7 | 1.3 | µs | ||
9 | tr(SDA) | Rise time, SDA | 1000 | 300 | ns | ||
10 | tr(SCL) | Rise time, SCL | 1000 | 300 | ns | ||
11 | tf(SDA) | Fall time, SDA | 300 | 300 | ns | ||
12 | tf(SCL) | Fall time, SCL | 300 | 300 | ns | ||
13 | tsu(SCLH-SDAH) | Setup time, high before SDA high (for STOP condition) | 4 | 0.6 | µs | ||
14 | tw(SP) | Pulse duration, spike (must be suppressed) | 0 | 50 | 0 | 50 | ns |
NO. | PARAMETER | STANDARD MODE | FAST MODE | UNIT | |||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
15 | tc(SCL) | Cycle time, SCL | 10 | 2.5 | µs | ||
16 | tsu(SCLH-SDAL) | Setup time, SCL high before SDA low (for a repeated START condition) | 4.7 | 0.6 | µs | ||
17 | th(SDAL-SCLL) | Hold time, SCL low after SDA low (for a START and a repeated START condition) | 4 | 0.6 | µs | ||
18 | tw(SCLL) | Pulse duration, SCL low | 4.7 | 1.3 | µs | ||
19 | tw(SCLH) | Pulse duration, SCL high | 4 | 0.6 | µs | ||
20 | tsu(SDAV-SCLH) | Setup time, SDA valid before SCL high | 250 | 100 | ns | ||
21 | th(SCLL-SDAV) | Hold time, SDA valid after SCL low | 0 | 3.45 | 0 | 0.9 | µs |
22 | tw(SDAH) | Pulse duration, SDA high between STOP and START conditions | 4.7 | 1.3 | µs | ||
23 | tr(SDA) | Rise time, SDA | 1000 | 300 | ns | ||
24 | tr(SCL) | Rise time, SCL | 1000 | 300 | ns | ||
25 | tf(SDA) | Fall time, SDA | 300 | 300 | ns | ||
26 | tf(SCL) | Fall time, SCL | 300 | 300 | ns | ||
27 | tsu(SCLH-SDAH) | Setup time, high before SDA high (for STOP condition) | 4 | 0.6 | µs |
NO. | OPP100 | OPP50 | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
1 | tc(TCK) | Cycle time, TCK | 81.5 | 104.5 | ns | ||
1a | tw(TCKH) | Pulse duration, TCK high (40% of tc) | 32.6 | 41.8 | ns | ||
1b | tw(TCKL) | Pulse duration, TCK low (40% of tc) | 32.6 | 41.8 | ns | ||
3 | tsu(TDI-TCKH) | Input setup time, TDI valid to TCK high | 3 | 3 | ns | ||
tsu(TMS-TCKH) | Input setup time, TMS valid to TCK high | 3 | 3 | ns | |||
4 | th(TCKH-TDI) | Input hold time, TDI valid from TCK high | 8.05 | 8.05 | ns | ||
th(TCKH-TMS) | Input hold time, TMS valid from TCK high | 8.05 | 8.05 | ns |
NO. | PARAMETER | OPP100 | OPP50 | UNIT | |||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
2 | td(TCKL-TDO) | Delay time, TCK low to TDO valid | 3 | 27.6 | 4 | 36.8 | ns |
The LCDC consists of two independent controllers, the raster controller and the LCD interface display driver (LIDD) controller. Each controller operates independently from the other and only one of them is active at any given time.
The maximum resolution for the LCD controller is 2048 × 2048 pixels. The maximum frame rate is determined by the image size in combination with the pixel clock rate.
PARAMETER | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
Output Condition | ||||||
CLOAD | Output load capacitance | LIDD mode | 5 | 60 | pF | |
Raster mode | 3 | 30 |
NO. | OPP100 | UNIT | |||
---|---|---|---|---|---|
MIN | MAX | ||||
16 | tsu(LCD_DATA-LCD_MEMORY_CLK) | Setup time, LCD_DATA[15:0] valid before LCD_MEMORY_CLK high | 18 | ns | |
17 | th(LCD_MEMORY_CLK-LCD_DATA) | Hold time, LCD_DATA[15:0] valid after LCD_MEMORY_CLK high | 0 | ns | |
18 | tt(LCD_DATA) | Transition time, LCD_DATA[15:0] | 1 | 3 | ns |
NO. | PARAMETER | OPP100 | UNIT | ||
---|---|---|---|---|---|
MIN | MAX | ||||
1 | tc(LCD_MEMORY_CLK) | Cycle time, LCD_MEMORY_CLK | 23.7 | ns | |
2 | tw(LCD_MEMORY_CLKH) | Pulse duration, LCD_MEMORY_CLK high | 0.45tc | 0.55tc | ns |
3 | tw(LCD_MEMORY_CLKL) | Pulse duration, LCD_MEMORY_CLK low | 0.45tc | 0.55tc | ns |
4 | td(LCD_MEMORY_CLK-LCD_DATAV) | Delay time, LCD_MEMORY_CLK high to LCD_DATA[15:0] valid (write) | 7 | ns | |
5 | td(LCD_MEMORY_CLK-LCD_DATAI) | Delay time, LCD_MEMORY_CLK high to LCD_DATA[15:0] invalid (write) | 0 | ns | |
6 | td(LCD_MEMORY_CLK-LCD_AC_BIAS_EN) | Delay time, LCD_MEMORY_CLK high to LCD_AC_BIAS_EN | 0 | 6.8 | ns |
7 | tt(LCD_AC_BIAS_EN) | Transition time, LCD_AC_BIAS_EN | 1 | 10 | ns |
8 | td(LCD_MEMORY_CLK-LCD_VSYNC) | Delay time, LCD_MEMORY_CLK high to LCD_VSYNC | 0 | 7 | ns |
9 | tt(LCD_VSYNC) | Transition time, LCD_VSYNC | 1 | 10 | ns |
10 | td(LCD_MEMORY_CLK-LCD_HYSNC) | Delay time, LCD_MEMORY_CLK high to LCD_HSYNC | 0 | 7 | ns |
11 | tt(LCD_HSYNC) | Transition time, LCD_HYSNC | 1 | 10 | ns |
12 | td(LCD_MEMORY_CLK-LCD_PCLK) | Delay time, LCD_MEMORY_CLK high to LCD_PCLK | 0 | 7 | ns |
13 | tt(LCD_PCLK) | Transition time, LCD_PCLK | 1 | 10 | ns |
14 | td(LCD_MEMORY_CLK-LCD_DATAZ) | Delay time, LCD_MEMORY_CLK high to LCD_DATA[15:0] high-Z | 0 | 7 | ns |
15 | td(LCD_MEMORY_CLK-LCD_DATA) | Delay time, LCD_MEMORY_CLK high to LCD_DATA[15:0] driven | 0 | 7 | ns |
19 | tt(LCD_MEMORY_CLK) | Transition time, LCD_MEMORY_CLK | 1 | 2.5 | ns |
20 | tt(LCD_DATA) | Transition time, LCD_DATA | 1 | 10 | ns |
NO. | PARAMETER | OPP50 | OPP100 | UNIT | |||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
1 | tc(LCD_PCLK) | Cycle time, pixel clock | 15.8 | 7.9 | ns | ||
2 | tw(LCD_PCLKH) | Pulse duration, pixel clock high | 0.45tc | 0.55tc | 0.45tc | 0.55tc | ns |
3 | tw(LCD_PCLKL) | Pulse duration, pixel clock low | 0.45tc | 0.55tc | 0.45tc | 0.55tc | ns |
4 | td(LCD_PCLK-LCD_DATAV) | Delay time, LCD_PCLK to LCD_DATA[23:0] valid (write) | 3.0 | 1.9 | ns | ||
5 | td(LCD_PCLK-LCD_DATAI) | Delay time, LCD_PCLK to LCD_DATA[23:0] invalid (write) | –3.0 | –1.7 | ns | ||
6 | td(LCD_PCLK-LCD_AC_BIAS_EN) | Delay time, LCD_PCLK to LCD_AC_BIAS_EN | –3.0 | 3.0 | –1.7 | 1.9 | ns |
7 | tt(LCD_AC_BIAS_EN) | Transition time, LCD_AC_BIAS_EN | 0.5 | 2.4 | 0.5 | 2.4 | ns |
8 | td(LCD_PCLK-LCD_VSYNC) | Delay time, LCD_PCLK to LCD_VSYNC | –3.0 | 3.0 | –1.7 | 1.9 | ns |
9 | tt(LCD_VSYNC) | Transition time, LCD_VSYNC | 0.5 | 2.4 | 0.5 | 2.4 | ns |
10 | td(LCD_PCLK-LCD_HSYNC) | Delay time, LCD_PCLK to LCD_HSYNC | –3.0 | 3.0 | –1.7 | 1.9 | ns |
11 | tt(LCD_HSYNC) | Transition time, LCD_HSYNC | 0.5 | 2.4 | 0.5 | 2.4 | ns |
12 | tt(LCD_PCLK) | Transition time, LCD_PCLK | 0.5 | 2.4 | 0.5 | 2.4 | ns |
13 | tt(LCD_DATA) | Transition time, LCD_DATA | 0.5 | 2.4 | 0.5 | 2.4 | ns |
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1) register:
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
LCD_AC_BIAS_EN timing is derived through the following parameter in the LCD (RASTER_TIMING_2) register:
The display format produced in raster mode is shown in Figure 7-81. An entire frame is delivered one line at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the activation of I/O signal LCD_HSYNC.
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission (DIT).
The device includes two multichannel audio serial port (McASP) interface peripherals (McASP0 and McASP1). The McASP module consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or, alternatively, the transmit and receive sections may be synchronized. The McASP module also includes shift registers that may be configured to operate as either transmit data or receive data.
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for SPDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP peripheral supports the TDM synchronous serial format.
The McASP module can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the same format; however, the transmit and receive formats need not be the same. Both the transmit and receive sections of the McASP also support burst mode, which is useful for nonaudio data (for example, passing control information between two devices).
The McASP peripheral has additional capability for flexible clock generation and error detection/handling, as well as error management.
The device McASP0 and McASP1 modules have up to four serial data pins each. The McASP FIFO size is 256 bytes and two DMA and two interrupt requests are supported. Buffers are used transparently to better manage DMA, which can be leveraged to manage data flow more efficiently.
For more detailed information on and the functionality of the McASP peripheral, see the Multichannel Audio Serial Port (McASP) section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Input Conditions | |||||
tR | Input signal rise time | 1(1) | 4(1) | ns | |
tF | Input signal fall time | 1(1) | 4(1) | ns | |
Output Condition | |||||
CLOAD | Output load capacitance | 15 | 30 | pF |
NO. | OPP100 | OPP50 | UNIT | |||||
---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||||
1 | tc(AHCLKRX) | Cycle time, McASP[x]_AHCLKR and McASP[x]_AHCLKX | 20 | 40 | ns | |||
2 | tw(AHCLKRX) | Pulse duration, McASP[x]_AHCLKR and McASP[x]_AHCLKX high or low | 0.5P - 2.5(2) | 0.5P - 2.5(2) | ns | |||
3 | tc(ACLKRX) | Cycle time, McASP[x]_ACLKR and McASP[x]_ACLKX | 20 | 40 | ns | |||
4 | tw(ACLKRX) | Pulse duration, McASP[x]_ACLKR and McASP[x]_ACLKX high or low | 0.5R - 2.5(3) | 0.5R - 2.5(3) | ns | |||
5 | tsu(AFSRX-ACLKRX) | Setup time, McASP[x]_AFSR and McASP[x]_AFSX input valid before McASP[x]_ACLKR and McASP[x]_ACLKX | ACLKR and ACLKX int | 11.5 | 15.5 | ns | ||
ACLKR and ACLKX ext in | 4 | 6 | ||||||
ACLKR and ACLKX ext out | 4 | 6 | ||||||
6 | th(ACLKRX-AFSRX) | Hold time, McASP[x]_AFSR and McASP[x]_AFSX input valid after McASP[x]_ACLKR and McASP[x]_ACLKX | ACLKR and ACLKX int | -1 | -1 | ns | ||
ACLKR and ACLKX ext in | 0.4 | 0.4 | ||||||
ACLKR and ACLKX ext out | 0.4 | 0.4 | ||||||
7 | tsu(AXR-ACLKRX) | Setup time, McASP[x]_AXR input valid before McASP[x]_ACLKR and McASP[x]_ACLKX | ACLKR and ACLKX int | 11.5 | 15.5 | ns | ||
ACLKR and ACLKX ext in | 4 | 6 | ||||||
ACLKR and ACLKX ext out | 4 | 6 | ||||||
8 | th(ACLKRX-AXR) | Hold time, McASP[x]_AXR input valid after McASP[x]_ACLKR and McASP[x]_ACLKX | ACLKR and ACLKX int | -1 | -1 | ns | ||
ACLKR and ACLKX ext in | 0.4 | 0.4 | ||||||
ACLKR and ACLKX ext out | 0.4 | 0.4 |
NO. | PARAMETER | OPP100 | OPP50 | UNIT | ||||
---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||||
9 | tc(AHCLKRX) | Cycle time, McASP[x]_AHCLKR and McASP[x]_AHCLKX | 20(2) | 40 | ns | |||
10 | tw(AHCLKRX) | Pulse duration, McASP[x]_AHCLKR and McASP[x]_AHCLKX high or low | 0.5P – 2.5(3) | 0.5P – 2.5(3) | ns | |||
11 | tc(ACLKRX) | Cycle time, McASP[x]_ACLKR and McASP[x]_ACLKX | 20 | 40 | ns | |||
12 | tw(ACLKRX) | Pulse duration, McASP[x]_ACLKR and McASP[x]_ACLKX high or low | 0.5P – 2.5(3) | 0.5P – 2.5(3) | ns | |||
13 | td(ACLKRX-AFSRX) | Delay time, McASP[x]_ACLKR and McASP[x]_ACLKX transmit edge to McASP[x]_AFSR and McASP[x]_AFSX output valid | ACLKR and ACLKX int | 0 | 6 | 0 | 6 | ns |
ACLKR and ACLKX ext in | 2 | 13.5 | 2 | 18 | ||||
Delay time, McASP[x]_ACLKR and McASP[x]_ACLKX transmit edge to McASP[x]_AFSR and McASP[x]_AFSX output valid with Pad Loopback | ACLKR and ACLKX ext out | 2 | 13.5 | 2 | 18 | |||
14 | td(ACLKX-AXR) | Delay time, McASP[x]_ACLKX transmit edge to McASP[x]_AXR output valid | ACLKX int | 0 | 6 | 0 | 6 | ns |
ACLKX ext in | 2 | 13.5 | 2 | 18 | ||||
Delay time, McASP[x]_ACLKX transmit edge to McASP[x]_AXR output valid with Pad Loopback | ACLKX ext out | 2 | 13.5 | 2 | 18 | |||
15 | tdis(ACLKX-AXR) | Disable time, McASP[x]_ACLKX transmit edge to McASP[x]_AXR output high impedance | ACLKX int | 0 | 6 | 0 | 6 | ns |
ACLKX ext in | 2 | 13.5 | 2 | 18 | ||||
Disable time, McASP[x]_ACLKX transmit edge to McASP[x]_AXR output high impedance with pad loopback | ACLKX ext out | 2 | 13.5 | 2 | 18 |
For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
The following timings are applicable to the different configurations of McSPI in master or slave mode for any McSPI and any channel (n).
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
Input Conditions | ||||
tr | Input signal rise time | 5 | ns | |
tf | Input signal fall time | 5 | ns | |
Output Condition | ||||
Cload | Output load capacitance | 20 | pF |
NO. | OPP100 | OPP50 | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
1 | tc(SPICLK) | Cycle time, SPI_CLK | 62.5 | 124.8 | ns | ||
2 | tw(SPICLKL) | Typical pulse duration, SPI_CLK low | 0.5P – 3.12(1) | 0.5P + 3.12(1) | 0.5P – 3.12(1) | 0.5P + 3.12(1) | ns |
3 | tw(SPICLKH) | Typical pulse duration, SPI_CLK high | 0.5P – 3.12(1) | 0.5P + 3.12(1) | 0.5P – 3.12(1) | 0.5P + 3.12(1) | ns |
4 | tsu(SIMO-SPICLK) | Setup time, SPI_D[x] (SIMO) valid before SPI_CLK active edge(2)(3) | 12.92 | 12.92 | ns | ||
5 | th(SPICLK-SIMO) | Hold time, SPI_D[x] (SIMO) valid after SPI_CLK active edge(2)(3) | 12.92 | 12.92 | ns | ||
8 | tsu(CS-SPICLK) | Setup time, SPI_CS valid before SPI_CLK first edge(2) | 12.92 | 12.92 | ns | ||
9 | th(SPICLK-CS) | Hold time, SPI_CS valid after SPI_CLK last edge(2) | 12.92 | 12.92 | ns |
NO. | PARAMETER | OPP100 | OPP50 | UNIT | |||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
6 | td(SPICLK-SOMI) | Delay time, SPI_CLK active edge to SPI_D[x] (SOMI) transition(1)(2) | –4.00 | 17.12 | –4.00 | 17.12 | ns |
7 | td(CS-SOMI) | Delay time, SPI_CS active edge to SPI_D[x] (SOMI) transition(1)(2) | 17.12 | 17.12 | ns |
PARAMETER | LOW LOAD | HIGH LOAD | UNIT | |||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
Input Conditions | ||||||
tr | Input signal rise time | 8 | 8 | ns | ||
tf | Input signal fall time | 8 | 8 | ns | ||
Output Condition | ||||||
Cload | Output load capacitance | 5 | 25 | pF |
NO. | OPP100 | OPP50 | UNIT | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
LOW LOAD | HIGH LOAD | LOW LOAD | HIGH LOAD | |||||||||
MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | |||||
4 | tsu(SOMI-SPICLKH) | Setup time, SPI_D[x] (SOMI) valid before SPI_CLK active edge(1) | 2.29 | 3.02 | 2.29 | 3.02 | ns | |||||
5 | th(SPICLKH-SOMI) | Hold time, SPI_D[x] (SOMI) valid after SPI_CLK active edge(1) | Industrial extended temperature (-40°C to 125°C) |
7.1 | 7.1 | 7.1 | 7.1 | ns | ||||
All other temperature ranges | 4.7 | 4.7 | 4.7 | 4.7 |
NO. | PARAMETER | OPP100 | OPP50 | UNIT | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
LOW LOAD | HIGH LOAD | LOW LOAD | HIGH LOAD | |||||||||
MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | |||||
1 | tc(SPICLK) | Cycle time, SPI_CLK | 20.8 | 20.8 | 41.6 | 41.6 | ns | |||||
2 | tw(SPICLKL) | Typical pulse duration, SPI_CLK low | 0.5P – 1.04(1) | 0.5P + 1.04(1) | 0.5P – 2.08(1) | 0.5P + 2.08(1) | 0.5P – 1.04(1) | 0.5P + 1.04(1) | 0.5P – 2.08(1) | 0.5P + 2.08(1) | ns | |
3 | tw(SPICLKH) | Typical pulse duration, SPI_CLK high | 0.5P – 1.04(1) | 0.5P + 1.04(1) | 0.5P – 2.08(1) | 0.5P + 2.08(1) | 0.5P – 1.04(1) | 0.5P + 1.04(1) | 0.5P – 2.08(1) | 0.5P + 2.08(1) | ns | |
tr(SPICLK) | Rising time, SPI_CLK | 3.82 | 3.82 | 3.82 | 3.82 | ns | ||||||
tf(SPICLK) | Falling time, SPI_CLK | 3.44 | 3.44 | 3.44 | 3.44 | ns | ||||||
6 | td(SPICLK-SIMO) | Delay time, SPI_CLK active edge to SPI_D[x] (SIMO) transition(2) | –3.57 | 3.57 | –4.62 | 4.62 | –3.57 | 3.57 | –4.62 | 4.62 | ns | |
7 | td(CS-SIMO) | Delay time, SPI_CS active edge to SPI_D[x] (SIMO) transition(2) | 3.57 | 4.62 | 3.57 | 4.62 | ns | |||||
8 | td(CS-SPICLK) | Delay time, SPI_CS active to SPI_CLK first edge | Mode 1 and 3(3) | A – 4.2(4) | A – 2.54(4) | A – 4.2(4) | A – 2.54(4) | ns | ||||
Mode 0 and 2(3) | B – 4.2(5) | B – 2.54(5) | B – 4.2(5) | B – 2.54(5) | ns | |||||||
9 | td(SPICLK-CS) | Delay time, SPI_CLK last edge to SPI_CS inactive | Mode 1 and 3(3) | B – 4.2(5) | B – 2.54(5) | B – 4.2(5) | B – 2.54(5) | ns | ||||
Mode 0 and 2(3) | A – 4.2(4) | A – 2.54(4) | A – 4.2(4) | A – 2.54(4) | ns |
For more information, see the Multimedia Card (MMC) section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Input Conditions | |||||
tr | Input signal rise time | 1 | 5 | ns | |
tf | Input signal fall time | 1 | 5 | ns | |
Output Condition | |||||
Cload | Output load capacitance | 3 | 30 | pF |
NO. | 1.8-V MODE | 3.3-V MODE | UNIT | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||||
1 | tsu(CMDV-CLKH) | Setup time, MMC_CMD valid before MMC_CLK rising clock edge | 4.1 | 4.1 | ns | ||||||
2 | th(CLKH-CMDV) | Hold time, MMC_CMD valid after MMC_CLK rising clock edge | Industrial extended temperature (–40°C to 125°C) |
MMC0-2 | 3.76 | 3.76 | ns | ||||
All other temperature ranges | MMC0 | 3.76 | 2.52 | ||||||||
MMC1 | 3.76 | 3.03 | |||||||||
MMC2 | 3.76 | 3.0 | |||||||||
3 | tsu(DATV-CLKH) | Setup time, MMC_DATx valid before MMC_CLK rising clock edge | 4.1 | 4.1 | ns | ||||||
4 | th(CLKH-DATV) | Hold time, MMC_DATx valid after MMC_CLK rising clock edge | Industrial extended temperature (–40°C to 125°C) |
MMC0-2 | 3.76 | 3.76 | ns | ||||
All other temperature ranges | MMC0 | 3.76 | 2.52 | ||||||||
MMC1 | 3.76 | 3.03 | |||||||||
MMC2 | 3.76 | 3.0 |
NO. | PARAMETER | STANDARD MODE | HIGH-SPEED MODE | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
5 | ƒop(CLK) | Operating frequency, MMC_CLK | 24 | 48 | MHz | ||||
tcop(CLK) | Operating period: MMC_CLK | 41.7 | 20.8 | ns | |||||
fid(CLK) | Identification mode frequency, MMC_CLK | 400 | 400 | kHz | |||||
tcid(CLK) | Identification mode period: MMC_CLK | 2500 | 2500 | ns | |||||
6 | tw(CLKL) | Pulse duration, MMC_CLK low | (0.5 × P) – tf(CLK)(1) | (0.5 × P) – tf(CLK)(1) | ns | ||||
7 | tw(CLKH) | Pulse duration, MMC_CLK high | (0.5 × P) – tr(CLK)(1) | (0.5 × P) – tr(CLK)(1) | ns | ||||
8 | tr(CLK) | Rise time, all signals (10% to 90%) | 2.2 | 2.2 | ns | ||||
9 | tf(CLK) | Fall time, all signals (10% to 90%) | 2.2 | 2.2 | ns |
NO. | PARAMETER | OPP100 | OPP50 | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
10 | td(CLKL-CMD) | Delay time, MMC_CLK falling clock edge to MMC_CMD transition | –4 | 14 | –4 | 17.5 | ns | ||
11 | td(CLKL-DAT) | Delay time, MMC_CLK falling clock edge to MMC_DATx transition | –4 | 14 | –4 | 17.5 | ns |
NO. | PARAMETER | OPP100 | OPP50 | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
12 | td(CLKL-CMD) | Delay time, MMC_CLK rising clock edge to MMC_CMD transition | 3 | 14 | 3 | 17.5 | ns | ||
13 | td(CLKL-DAT) | Delay time, MMC_CLK rising clock edge to MMC_DATx transition | 3 | 14 | 3 | 17.5 | ns |
For more information, see the Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem Interface (PRU-ICSS) section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
Output Condition | ||||
Cload | Capacitive load for each bus line | 30 | pF |
NO. | MIN | MAX | UNIT | |||
---|---|---|---|---|---|---|
1 | tw(GPI) | Pulse width, GPI | 2 × P(1) | ns | ||
2 | tr(GPI) | Rise time, GPI | 1.00 | 3.00 | ns | |
tf(GPI) | Fall time, GPI | 1.00 | 3.00 | ns | ||
3 | tsk(GPI) | Internal skew between GPI[n:0] signals(2) | PRU0 | 1.00 | ns | |
PRU1 | 3.00 |
NO. | PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | tw(GPO) | Pulse width, GPO | 2 × P(1) | ns | ||
2 | tr(GPO) | Rise time, GPO | 1.00 | 3.00 | ns | |
tf(GPO) | Fall time, GPO | 1.00 | 3.00 | ns | ||
3 | tsk(GPO) | Internal skew between GPO[n:0] signals(2) | PRU0 | 1.00 | ns | |
PRU1 | 5.00 |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | tc(CLOCKIN) | Cycle time, CLOCKIN | 20.00 | ns | |
2 | tw(CLOCKIN_L) | Pulse duration, CLOCKIN low | 10.00 | ns | |
3 | tw(CLOCKIN_H) | Pulse duration, CLOCKIN high | 10.00 | ns | |
4 | tr(CLOCKIN) | Rising time, CLOCKIN | 1.00 | 3.00 | ns |
5 | tf(CLOCKIN) | Falling time, CLOCKIN | 1.00 | 3.00 | ns |
6 | tsu(DATAIN-CLOCKIN) | Setup time, DATAIN valid before CLOCKIN | 5.00 | ns | |
7 | th(CLOCKIN-DATAIN) | Hold time, DATAIN valid after CLOCKIN | 0.00 | ns | |
8 | tr(DATAIN) | Rising time, DATAIN | 1.00 | 3.00 | ns |
tf(DATAIN) | Falling time, DATAIN | 1.00 | 3.00 | ns |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | tc(DATAIN) | Cycle time, DATAIN | 10.00 | ns | |
2 | tw(DATAIN) | Pulse width, DATAIN | 0.45 × P(1) | 0.55 × P(1) | ns |
3 | tr(DATAIN) | Rising time, DATAIN | 1.00 | 3.00 | ns |
4 | tf(DATAIN) | Falling time, DATAIN | 1.00 | 3.00 | ns |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | tc(CLOCKOUT) | Cycle time, CLOCKOUT | 10.00 | ns | |
2 | tw(CLOCKOUT) | Pulse width, CLOCKOUT | 0.45 × P(1) | 0.55 × P(1) | ns |
3 | tr(CLOCKOUT) | Rising time, CLOCKOUT | 1.00 | 3.00 | ns |
4 | tf(CLOCKOUT) | Falling time, CLOCKOUT | 1.00 | 3.00 | ns |
5 | td(CLOCKOUT-DATAOUT) | Delay time, CLOCKOUT to DATAOUT valid | 0.00 | 3.00 | ns |
6 | tr(DATAOUT) | Rising time, DATAOUT | 1.00 | 3.00 | ns |
tf(DATAOUT) | Falling time, DATAOUT | 1.00 | 3.00 | ns |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
Output Condition | ||||
Cload | Capacitive load for each bus line | 30 | pF |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | tw(EDIO_LATCH_IN) | Pulse width, EDIO_LATCH_IN | 100.00 | ns | |
2 | tr(EDIO_LATCH_IN) | Rising time, EDIO_LATCH_IN | 1.00 | 3.00 | ns |
3 | tf(EDIO_LATCH_IN) | Falling time, EDIO_LATCH_IN | 1.00 | 3.00 | ns |
4 | tsu(EDIO_DATA_IN-EDIO_LATCH_IN) | Setup time, EDIO_DATA_IN valid before EDIO_LATCH_IN active edge | 20.00 | ns | |
5 | th(EDIO_LATCH_IN-EDIO_DATA_IN) | Hold time, EDIO_DATA_IN valid after EDIO_LATCH_IN active edge | 20.00 | ns | |
6 | tr(EDIO_DATA_IN) | Rising time, EDIO_DATA_IN | 1.00 | 3.00 | ns |
tf(EDIO_DATA_IN) | Falling time, EDIO_DATA_IN | 1.00 | 3.00 | ns |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | tw(EDC_SYNCx_OUT) | Pulse width, EDC_SYNCx_OUT | 100.00 | ns | |
2 | tr(EDC_SYNCx_OUT) | Rising time, EDC_SYNCx_OUT | 1.00 | 3.00 | ns |
3 | tf(EDC_SYNCx_OUT) | Falling time, EDC_SYNCx_OUT | 1.00 | 3.00 | ns |
4 | tsu(EDIO_DATA_IN-EDC_SYNCx_OUT) | Setup time, EDIO_DATA_IN valid before EDC_SYNCx_OUT active edge | 20.00 | ns | |
5 | th(EDC_SYNCx_OUT-EDIO_DATA_IN) | Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT active edge | 20.00 | ns | |
6 | tr(EDIO_DATA_IN) | Rising time, EDIO_DATA_IN | 1.00 | 3.00 | ns |
tf(EDIO_DATA_IN) | Falling time, EDIO_DATA_IN | 1.00 | 3.00 | ns |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | tw(EDIO_SOF) | Pulse duration, EDIO_SOF | 4 × P(1) | 5 × P(1) | ns |
2 | tr(EDIO_SOF) | Rising time, EDIO_SOF | 1.00 | 3.00 | ns |
3 | tf(EDIO_SOF) | Falling time, EDIO_SOF | 1.00 | 3.00 | ns |
4 | tsu(EDIO_DATA_IN-EDIO_SOF) | Setup time, EDIO_DATA_IN valid before EDIO_SOF active edge | 20.00 | ns | |
5 | th(EDIO_SOF-EDIO_DATA_IN) | Hold time, EDIO_DATA_IN valid after EDIO_SOF active edge | 20.00 | ns | |
6 | tr(EDIO_DATA_IN) | Rising time, EDIO_DATA_IN | 1.00 | 3.00 | ns |
tf(EDIO_DATA_IN) | Falling time, EDIO_DATA_IN | 1.00 | 3.00 | ns |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | tw(EDC_LATCHx_IN) | Pulse duration, EDC_LATCHx_IN | 3 × P(1) | ns | |
2 | tr(EDC_LATCHx_IN) | Rising time, EDC_LATCHx_IN | 1.00 | 3.00 | ns |
3 | tf(EDC_LATCHx_IN) | Falling time, EDC_LATCHx_IN | 1.00 | 3.00 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | tw(EDIO_OUTVALID) | Pulse duration, EDIO_OUTVALID | 14 × P(1) | 32 × P(1) | ns |
2 | tr(EDIO_OUTVALID) | Rising time, EDIO_OUTVALID | 1.00 | 3.00 | ns |
3 | tf(EDIO_OUTVALID) | Falling time, EDIO_OUTVALID | 1.00 | 3.00 | ns |
4 | td(EDIO_OUTVALID-EDIO_DATA_OUT) | Delay time, EDIO_OUTVALID to EDIO_DATA_OUT | 0.00 | 18 × P(1) | ns |
5 | tr(EDIO_DATA_OUT) | Rising time, EDIO_DATA_OUT | 1.00 | 3.00 | ns |
6 | tf(EDIO_DATA_OUT) | Falling time, EDIO_DATA_OUT | 1.00 | 3.00 | ns |
7 | tsk(EDIO_DATA_OUT) | EDIO_DATA_OUT skew | 8.00 | ns |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Input Conditions | |||||
tR | Input signal rise time | 1(1) | 3(1) | ns | |
tF | Input signal fall time | 1(1) | 3(1) | ns | |
Output Condition | |||||
CLOAD | Output load capacitance | 3 | 20 | pF |
NO. | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | tsu(MDIO-MDC) | Setup time, MDIO valid before MDC high | 90 | ns | ||
2 | th(MDIO-MDC) | Hold time, MDIO valid from MDC high | 0 | ns |
NO. | PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | tc(MDC) | Cycle time, MDC | 400 | ns | ||
2 | tw(MDCH) | Pulse duration, MDC high | 160 | ns | ||
3 | tw(MDCL) | Pulse duration, MDC low | 160 | ns | ||
4 | tt(MDC) | Transition time, MDC | 5 | ns |
NO. | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | td(MDC-MDIO) | Delay time, MDC high to MDIO valid | 10 | 390 | ns |
NOTE
In order to guarantee the MII_RT I/O timing values published in the device data manual, the PRU ocp_clk clock must be configured for 200 MHz (default value) and the TX_CLK_DELAY bit field in the PRUSS_MII_RT_TXCFG0/1 register must be set to 6 h (non-default value).
NO. | 10 Mbps | 100 Mbps | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | tc(RX_CLK) | Cycle time, RX_CLK | 399.96 | 400.04 | 39.996 | 40.004 | ns | ||
2 | tw(RX_CLKH) | Pulse duration, RX_CLK high | 140 | 260 | 14 | 26 | ns | ||
3 | tw(RX_CLKL) | Pulse duration, RX_CLK low | 140 | 260 | 14 | 26 | ns | ||
4 | tt(RX_CLK) | Transition time, RX_CLK | 3 | 3 | ns |
NO. | 10 Mbps | 100 Mbps | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | tc(TX_CLK) | Cycle time, TX_CLK | 399.96 | 400.04 | 39.996 | 40.004 | ns | ||
2 | tw(TX_CLKH) | Pulse duration, TX_CLK high | 140 | 260 | 14 | 26 | ns | ||
3 | tw(TX_CLKL) | Pulse duration, TX_CLK low | 140 | 260 | 14 | 26 | ns | ||
4 | tt(TX_CLK) | Transition time, TX_CLK | 3 | 3 | ns |
NO. | 10 Mbps | 100 Mbps | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | tsu(RXD-RX_CLK) | Setup time, RXD[3:0] valid before RX_CLK | 8 | 8 | ns | ||||
tsu(RX_DV-RX_CLK) | Setup time, RX_DV valid before RX_CLK | ||||||||
tsu(RX_ER-RX_CLK) | Setup time, RX_ER valid before RX_CLK | ||||||||
2 | th(RX_CLK-RXD) | Hold time RXD[3:0] valid after RX_CLK | 8 | 8 | ns | ||||
th(RX_CLK-RX_DV) | Hold time RX_DV valid after RX_CLK | ||||||||
th(RX_CLK-RX_ER) | Hold time RX_ER valid after RX_CLK |
NO. | 10 Mbps | 100 Mbps | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
1 | td(TX_CLK-TXD) | Delay time, TX_CLK high to TXD[3:0] valid | 5 | 25 | 5 | 25 | ns | ||
td(TX_CLK-TX_EN) | Delay time, TX_CLK to TX_EN valid |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
3 | tw(RX) | Pulse duration, receive start, stop, data bit | 0.96U(1) | 1.05U(1) | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | ƒbaud(baud) | Maximum programmable baud rate | 0 | 12 | MHz |
2 | tw(TX) | Pulse duration, transmit start, stop, data bit | U – 2(1) | U + 2(1) | ns |
For more information, see the Universal Asynchronous Receiver Transmitter (UART) section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
3 | tw(RX) | Pulse duration, receive start, stop, data bit | 0.96U(1) | 1.05U(1) | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | ƒbaud(baud) | Maximum programmable baud rate | 3.6864 | MHz | |
2 | tw(TX) | Pulse duration, transmit start, stop, data bit | U – 2(1) | U + 2(1) | ns |
The IrDA module operates in three different modes:
Figure 7-115 shows the UART IrDA pulse parameters. Table 7-115 and Table 7-116 list the signaling rates and pulse durations for UART IrDA receive and transmit modes.
SIGNALING RATE | ELECTRICAL PULSE DURATION | UNIT | |
---|---|---|---|
MIN | MAX | ||
SIR | |||
2.4 kbps | 1.41 | 88.55 | µs |
9.6 kbps | 1.41 | 22.13 | µs |
19.2 kbps | 1.41 | 11.07 | µs |
38.4 kbps | 1.41 | 5.96 | µs |
57.6 kbps | 1.41 | 4.34 | µs |
115.2 kbps | 1.41 | 2.23 | µs |
MIR | |||
0.576 Mbps | 297.2 | 518.8 | ns |
1.152 Mbps | 149.6 | 258.4 | ns |
FIR | |||
4 Mbps (single pulse) | 67 | 164 | ns |
4 Mbps (double pulse) | 190 | 289 | ns |
SIGNALING RATE | ELECTRICAL PULSE DURATION | UNIT | |
---|---|---|---|
MIN | MAX | ||
SIR | |||
2.4 kbps | 78.1 | 78.1 | µs |
9.6 kbps | 19.5 | 19.5 | µs |
19.2 kbps | 9.75 | 9.75 | µs |
38.4 kbps | 4.87 | 4.87 | µs |
57.6 kbps | 3.25 | 3.25 | µs |
115.2 kbps | 1.62 | 1.62 | µs |
MIR | |||
0.576 Mbps | 414 | 419 | ns |
1.152 Mbps | 206 | 211 | ns |
FIR | |||
4 Mbps (single pulse) | 123 | 128 | ns |
4 Mbps (double pulse) | 248 | 253 | ns |