SPRS550F October   2009  – July 2014 AM3505 , AM3517

PRODUCTION DATA.  

  1. 1Device Summary
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Features Comparison
    2. 3.2 ZCN and ZER Package Differences
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Assignments
      1. 4.1.1 Pin Map (Top View)
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Description
      1. 4.4.1 External Memory Interfaces
      2. 4.4.2 Video Interfaces
      3. 4.4.3 Serial Communication Interfaces
      4. 4.4.4 Removable Media Interfaces
      5. 4.4.5 Test Interfaces
      6. 4.4.6 Miscellaneous
      7. 4.4.7 General-Purpose IOs
      8. 4.4.8 System and Miscellaneous Terminals
      9. 4.4.9 Power Supplies
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Handling Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Characteristics
    7. 5.7  Core Voltage Decoupling
    8. 5.8  Power-up and Power-down
      1. 5.8.1 Power-up Sequence
      2. 5.8.2 Power-down Sequence
    9. 5.9  Clock Specifications
      1. 5.9.1 Oscillator
      2. 5.9.2 Input Clock Specifications
      3. 5.9.3 Output Clock Specifications
      4. 5.9.4 DPLL Specifications
        1. 5.9.4.1 Digital Phase-Locked Loop (DPLL)
          1. 5.9.4.1.1 DPLL1 (MPU)
          2. 5.9.4.1.2 DPLL3 (CORE)
          3. 5.9.4.1.3 DPLL4 (Peripherals)
          4. 5.9.4.1.4 DPLL5 (Second peripherals DPLL)
        2. 5.9.4.2 DPLL Noise Isolation
    10. 5.10 Video DAC Specifications
      1. 5.10.1 Interface Description
      2. 5.10.2 Electrical Specifications Over Recommended Operating Conditions
      3. 5.10.3 Analog Supply (vdda_dac) Noise Requirements
      4. 5.10.4 External Component Value Choice
  6. 6Timing Requirements and Switching Characteristics
    1. 6.1 Timing Test Conditions
    2. 6.2 Interface Clock Specifications
      1. 6.2.1 Interface Clock Terminology
      2. 6.2.2 Interface Clock Frequency
      3. 6.2.3 Clock Jitter Specifications
      4. 6.2.4 Clock Duty Cycle Error
    3. 6.3 Timing Parameters
    4. 6.4 External Memory Interfaces
      1. 6.4.1 General-Purpose Memory Controller (GPMC)
        1. 6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing
        2. 6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing
        3. 6.4.1.3 GPMC/NAND Flash Interface Timing
      2. 6.4.2 SDRAM Controller (SDRC)
        1. 6.4.2.1 LPDDR Interface
          1. 6.4.2.1.1 LPDDR Interface Schematic
          2. 6.4.2.1.2 Compatible JEDEC LPDDR Devices
          3. 6.4.2.1.3 PCB Stackup
          4. 6.4.2.1.4 Placement
          5. 6.4.2.1.5 LPDDR Keep Out Region
          6. 6.4.2.1.6 Net Classes
          7. 6.4.2.1.7 LPDDR Signal Termination
          8. 6.4.2.1.8 LPDDR CK and ADDR_CTRL Routing
        2. 6.4.2.2 DDR2 Interface
          1. 6.4.2.2.1  DDR2 Interface Schematic
          2. 6.4.2.2.2  Compatible JEDEC DDR2 Devices
          3. 6.4.2.2.3  PCB Stackup
          4. 6.4.2.2.4  Placement
          5. 6.4.2.2.5  DDR2 Keep Out Region
          6. 6.4.2.2.6  Bulk Bypass Capacitors
          7. 6.4.2.2.7  High-Speed Bypass Capacitors
          8. 6.4.2.2.8  Net Classes
          9. 6.4.2.2.9  DDR2 Signal Termination
          10. 6.4.2.2.10 VREF Routing
          11. 6.4.2.2.11 DDR2 CLK and ADDR_CTRL Routing
          12. 6.4.2.2.12 On Die Termination (ODT)
    5. 6.5 Video Interfaces
      1. 6.5.1 Video Processing Subsystem (VPSS)
        1. 6.5.1.1 Video Processing Front End (VPFE)
          1. 6.5.1.1.1 Video Processing Front End (VPFE) Timing
      2. 6.5.2 Display Subsystem (DSS)
        1. 6.5.2.1 LCD Display Support in Bypass Mode
          1. 6.5.2.1.1 LCD Display in TFT Mode
          2. 6.5.2.1.2 LCD Display in STN Mode
    6. 6.6 Serial Communications Interfaces
      1. 6.6.1  Multichannel Buffered Serial Port (McBSP) Timing
        1. 6.6.1.1 McBSP in Normal Mode
          1. 6.6.1.1.1 McBSP1
          2. 6.6.1.1.2 McBSP2
          3. 6.6.1.1.3 McBSP3
            1. 6.6.1.1.3.1 McBSP3 Multiplexed on McBSP3 Pins
            2. 6.6.1.1.3.2 McBSP3 Multiplexed on UART2 or McBSP1 Pins
          4. 6.6.1.1.4 McBSP4
          5. 6.6.1.1.5 McBSP5
          6. 6.6.1.1.6 McBSP in TDM Mode
          7. 6.6.1.1.7 McBSP Timing Diagrams
      2. 6.6.2  Multichannel Serial Port Interface (McSPI) Timing
        1. 6.6.2.1 McSPI in Slave Mode
        2. 6.6.2.2 McSPI in Master Mode
      3. 6.6.3  Multiport Full-Speed Universal Serial Bus (USB) Interface
        1. 6.6.3.1 Multiport Full-Speed Universal Serial Bus (USB) - Unidirectional Standard 6-pin Mode
        2. 6.6.3.2 Multiport Full-Speed Universal Serial Bus (USB) - Bidirectional Standard 4-pin Mode
        3. 6.6.3.3 Multiport Full-Speed Universal Serial Bus (USB) - Bidirectional Standard 3-pin Mode
      4. 6.6.4  Multiport High-Speed Universal Serial Bus (USB) Timing
        1. 6.6.4.1 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 12-bit Master Mode
      5. 6.6.5  USB0 OTG (USB2.0 OTG)
        1. 6.6.5.1 USB OTG Electrical Parameters
      6. 6.6.6  High-End Controller Area Network Controller (HECC) Timing
        1. 6.6.6.1 HECC Timing Requirements
        2. 6.6.6.2 HECC Switching Characteristics
      7. 6.6.7  Ethernet Media Access Controller (EMAC)
        1. 6.6.7.1 EMAC Electrical Data/ Timing
      8. 6.6.8  Management Data Input/Output (MDIO)
        1. 6.6.8.1 Management Data Input/Output (MDIO) Electrical Data/Timing
      9. 6.6.9  Universal Asynchronous Receiver/Transmitter (UART)
        1. 6.6.9.1 UART IrDA Interface
          1. 6.6.9.1.1 IrDA—Receive Mode
          2. 6.6.9.1.2 IrDA—Transmit Mode
      10. 6.6.10 HDQ / 1-Wire Interfaces
        1. 6.6.10.1 HDQ Protocol
        2. 6.6.10.2 1-Wire Protocol
      11. 6.6.11 I2C Interface
        1. 6.6.11.1 I2C Standard/Fast-Speed Mode
        2. 6.6.11.2 I2C High-Speed Mode
    7. 6.7 Removable Media Interfaces
      1. 6.7.1 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing
        1. 6.7.1.1 MMC/SD/SDIO in SD Identification Mode
        2. 6.7.1.2 MMC/SD/SDIO in High-Speed MMC Mode
        3. 6.7.1.3 MMC/SD/SDIO in Standard MMC Mode and MMC Identification Mode
        4. 6.7.1.4 MMC/SD/SDIO in High-Speed SD Mode
        5. 6.7.1.5 MMC/SD/SDIO in Standard SD Mode
    8. 6.8 Test Interfaces
      1. 6.8.1 Embedded Trace Macro Interface (ETM)
      2. 6.8.2 JTAG Interfaces
        1. 6.8.2.1 JTAG Free Running Clock Mode
        2. 6.8.2.2 JTAG Adaptive Clock Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
        1. 7.1.1.1 Getting Started and Next Steps
      2. 7.1.2 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
    3. 7.3 Related Links
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Package Option Addendum

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZER|484
  • ZCN|491
サーマルパッド・メカニカル・データ
発注情報

1 Device Summary

1.1 Features

  • AM3517/05 Sitara Processor:
    • MPU Subsystem
      • 600-MHz Sitara ARM Cortex®-A8 Core
      • NEON™ SIMD Coprocessor and Vector Floating-Point (FP) Coprocessor
    • Memory Interfaces:
      • 166-MHz 16- and 32-Bit mDDR/DDR2 Interface with 1GB of Total Addressable Space
      • Up to 83 MHz General-Purpose Memory Interface Supporting 16-Bit-Wide Multiplexed Address/Data Bus
      • 64KB of SRAM
      • 3 Removable Media Interfaces [MMC/SD/SDIO]
    • IO Voltage:
      • mDDR/DDR2 IOs: 1.8V
      • Other IOs: 1.8V and 3.3V
    • Core Voltage: 1.2V
    • Commercial and Extended Temperature Grade
      (operating restrictions apply)
    • 16-Bit Video Input Port Capable of Capturing HD Video
    • HD Resolution Display Subsystem
    • Serial Communication
      • High-End CAN Controller
      • 10/100 Mbit Ethernet MAC
      • USB OTG Subsystem with Standard DP/DM Interface [HS/FS/LS]
      • Multiport USB Host Subsystem [HS/FS/LS]
        • 12-Pin ULPI or 6-, 4-, or 3-Pin Serial Interface
      • Four Master and Slave Multichannel Serial Port Interface (McSPI) Ports
      • Five Multichannel Buffered Serial Ports (McBSPs)
        • 512-Byte Transmit and Receive Buffer (McBSP1/3/4/5)
        • 5-KB Transmit and Receive Buffer (McBSP2)
        • SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
        • 128-Channel Transmit and Receive Mode
        • Direct Interface to I2S and PCM Device and TDM Buses
      • HDQ/1-Wire Interface
      • 4 UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
      • 3 Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
      • Twelve 32-bit General-Purpose Timers
      • One 32-bit Watchdog Timer
      • One 32-bit 32-kHz Sync Timer
      • Up to 186 General-Purpose I/O (GPIO) Pins
  • Display Subsystem
    • Parallel Digital Output
    • Up to 24-Bit RGB
    • Supports Up to 2 LCD Panels
    • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
    • Two 10-Bit Digital-to-Analog Converters (DACs) Supporting
      • Composite NTSC/PAL Video
      • Luma/Chroma Separate Video (S-Video)
    • Rotation of 90, 180, and 270 Degrees
    • Resize Images From 1/4x to 8x
    • Color Space Converter
    • 8-Bit Alpha Blending
  • Video Processing Front End (VPFE) 16-Bit Video Input Port
    • RAW Data Interface
    • 75-MHz Maximum Pixel Clock
    • Supports REC656/CCIR656 Standard
    • Supports YCbCr422 Format (8-Bit or 16-Bit with Discrete Horizontal and Vertical Sync Signals)
    • Generates Optical Black Clamping Signals
    • Built-in Digital Clamping and Black Level Compensation
    • 10-Bit to 8-Bit A-law Compression Hardware
    • Supports up to 16K Pixels (Image Size) in Horizontal and Vertical Directions
  • System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
  • Comprehensive Power, Reset, and Clock Management
  • ARM Cortex-A8 Memory Architecture
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Microprocessor Core
      • ARM NEON Multimedia Architecture
      • Over 2x Performance of ARMv6 SIMD
      • Supports Both Integer and Floating-Point SIMD
      • Jazelle® RCT Execution Environment Architecture
      • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer and 8-Entry Return Stack
      • Embedded Trace Macrocell [ETM] Support for Noninvasive Debug
      • 16KB of Instruction Cache (4-Way Set-Associative)
      • 16KB of Data Cache (4-Way Set-Associative)
      • 256KB of L2 Cache
    • PowerVR SGX™ Graphics Accelerator (AM3517 Only)
      • Tile-Based Architecture Delivering up to 10 MPoly/sec
      • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Programmable, High-Quality Image Anti-Aliasing
    • Endianess
      • ARM Instructions – Little Endian
      • ARM Data – Configurable
    • SDRC Memory Controller
      • 16- and 32-Bit Memory Controller with 1GB of Total Address Space
      • Double Data Rate (DDR2) SDRAM, Mobile Double Data Rate (mDDR)SDRAM
      • SDRAM Memory Scheduler (SMS) and Rotation Engine
    • General Purpose Memory Controller (GPMC)
      • 16-Bit-Wide Multiplexed Address/Data Bus
      • Up to 8 Chip-Select Pins with 128MB of Address Space per Chip-Select Pin
      • Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM and Pseudo-SRAM
      • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
      • Nonmultiplexed Address/Data Mode (Limited 2-KB Address Space)
    • Test Interfaces
      • IEEE-1149.1 (JTAG) Boundary-Scan Compatible
      • Embedded Trace Macro Interface (ETM)
    • 65-nm CMOS Technology
    • Packages:
      • 491-Pin BGA (17 x 17, 0.65-mm Pitch)
        [ZCN Suffix]
        with Via Channel™ Array Technology
      • 484-Pin PBGA (23 x 23, 1-mm Pitch)
        [ZER Suffix]

    1.2 Applications

    • Single-Board Computers
    • Industrial and Home Automation
    • Digital Signage
    • Point of Service
    • Portable Media Player
    • Portable Industrial
    • Transportation
    • Navigation
    • Smart White Goods
    • Digital TV
    • Digital Video Camera
    • Gaming

    1.3 Description

    AM3517/05 is a high-performance ARM Cortex-A8 microprocessor with speeds up to 600 MHz. The device offers 3D graphics acceleration while also supporting numerous peripherals, including DDR2, CAN, EMAC, and USB OTG PHY that are well suited for industrial apllications.

    The processor can support other applications, including:

    • Single-board computers
    • Home and industrial automation
    • Human machine Interface

    The device supports high-level operating systems (OSs), such as:

    • Linux®
    • Windows® CE
    • Android™

    The following subsystems are part of the device:

    • Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
    • PowerVR SGX graphics accelerator (AM3517 device only) subsystem for 3D graphics acceleration to support display and gaming effects
    • Display subsystem with several features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC/PAL video out.
    • High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme.

    AM3517/05 devices are available in a 491-pin BGA package and a 484-pin PBGA package.

    This AM3517/05 data manual presents the electrical and mechanical specifications for the AM3517/05 Sitara processor.

    Device Information(1)

    PART NUMBER PACKAGE BODY SIZE
    AM3505 NFBGA (491) 17.10 mm x 17.10 mm
    AM3505 BGA (484) 23.20 mm x 23.20 mm
    AM3517 NFBGA (491) 17.10 mm x 17.10 mm
    AM3517 BGA (484) 23.20 mm x 23.20 mm
    (1) For more information, see Section 8, Mechanical Packaging and Orderable Information.

    1.4 Functional Block Diagram

    Figure 1-1 shows the functional block diagram of the AM3517/05 Sitara ARM microprocessor.

    fbdnew3_sprs550.gifFigure 1-1 AM3517/05 Functional Block Diagram