6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing

Table 6-2 through Table 6-4 assume testing over the recommended operating conditions and electrical characteristic conditions.

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-2 GPMC/NOR Flash Synchronous Single Read (GpmcFCLKDivider = 0)

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-3 GPMC/NOR Flash Synchronous Burst Read 4x16-bit (GpmcFCLKDivider = 0)

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-4 GPMC/NOR Flash Synchronous Burst Write (GpmcFCLKDivider = 0)

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-5 GPMC/Multiplexed NOR Flash Synchronous Burst Read

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-6 GPMC/Multiplexed NOR Flash Synchronous Burst Write

6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing

Table 6-5 through Table 6-8 assume testing over the recommended operating conditions and electrical characteristic conditions.

1. For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
   For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
   For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
   For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n being the page burst access number
2. For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK
   For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK
3. C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK
4. D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
5. E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK
6. F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK
7. G = Cycle2CycleDelay * GPMC_FCLK
8. I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK
9. J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK
10. K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK
11. L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK
12. For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
    For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
    For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
    For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
13. In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
14. M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK
    Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR behavior is automatically handled by GPMC controller.

Figure 6-7 GPMC/NOR Flash – Asynchronous Read – Single Word Timing^(1)(2)(3)

1. In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
2. FA5 parameter provides amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bit field.
3. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 6-8 GPMC/NOR Flash – Asynchronous Read – 32-bit Timing^(1)(2)(3)

1. In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
2. FA5 parameter provides amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bit field.
3. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 6-9 GPMC/NOR Flash – Asynchronous Read – Page Mode 4x16-bit Timing^(1)(2)(3)(4)

1. In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
2. FA21 parameter provides amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside AccessTime register bit field.
3. FA20 parameter provides amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bit field.
4. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-10 GPMC/NOR Flash – Asynchronous Write – Single Word Timing

Figure 6-11 GPMC/Multiplexed NOR Flash – Asynchronous Read – Single Word Timing^(1)(2)(3)

1. In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
2. FA5 parameter provides amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bit field.
3. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-12 GPMC/Multiplexed NOR Flash – Asynchronous Write – Single Word Timing

6.4.1.3 GPMC/NAND Flash Interface Timing

Table 6-9 through Table 6-12 assume testing over the recommended operating conditions and electrical characteristic conditions.

1. A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
2. B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK
3. C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK
4. D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK
5. E = (WrCycleTime – WEOffTime * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay ) * GPMC_FCLK
6. F = (ADVWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay ) * GPMC_FCLK
7. G = (CSWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay ) * GPMC_FCLK
8. H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
9. I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK
10. K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK
11. L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
12. M = (CSRdOffTime – OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay ) * GPMC_FCLK
13. In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

Figure 6-13 GPMC/NAND Flash – Command Latch Cycle Timing

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

Figure 6-14 GPMC/NAND Flash – Address Latch Cycle Timing

Figure 6-15 GPMC/NAND Flash – Data Read Cycle Timing^(1)(2)(3)

1. The GNF12 parameter provides amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
2. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
3. In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3.

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 or 1.

Figure 6-16 GPMC/NAND Flash – Data Write Cycle Timing

6.4.2.1 LPDDR Interface

This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the need for a complex timing closure process. For more information regarding guidelines for using this LPDDR specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing Specification Application Report (SPRAAV0).

6.4.2.1.1 LPDDR Interface Schematic

Figure 6-17 and Figure 6-18 show the LPDDR interface schematics for a LPDDR memory system. The 1 x16 LPDDR system schematic is identical to Figure 6-17 except that the high word LPDDR device is deleted.

Figure 6-17 AM3517/05 LPDDR High Level Schematic (x16 memories)

Figure 6-18 AM3517/05 LPDDR High Level Schematic (x32 memory)

6.4.2.1.4 Placement

Figure 6-19 shows the required placement for the microprocessor as well as the LPDDR devices. The dimensions for Figure 6-19 are defined in Table 6-16. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For 1x16 and 1x32 LPDDR memory systems, the second LPDDR device is omitted from the placement.

Figure 6-19 AM3517/05 and LPDDR Device Placement

Table 6-16 Placement Specifications

NO.	PARAMETER	MIN	MAX	UNIT	NOTES
1	X		1440	Mils	See Notes(1), (2)
2	Y		1030	Mils	See Notes(1), (2)
3	Y Offset		525	Mils	See Notes(1),(2),(3)
4	LPDDR Keepout Region				See Note(4)
5	Clearance from non-LPDDR signal to LPDDR Keepout Region	4		w	See Note(5)

(1) See Figure 6-19 for dimension definitions.

(2) Measurements from center of device to center of LPDDR device.

(3) For 16 bit memory systems it is recommended that Y Offset be as small as possible.

(4) LPDDR keepout region to encompass entire LPDDR routing area.

(5) Non-LPDDR signals allowed within LPDDR keepout region provided they are separated from LPDDR routing layers by a ground plane.

6.4.2.1.5 LPDDR Keep Out Region

The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR keep out region is defined for this purpose and is shown in Figure 6-20. The size of this region varies with the placement and LPDDR routing. Additional clearances required for the keep out region are listed in Table 6-16.

Figure 6-20 LPDDR Keepout Region

6.4.2.1.8 LPDDR CK and ADDR_CTRL Routing

Figure 6-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized.

Figure 6-21 CK and ADDR_CTRL Routing and Topology

Table 6-20 CK and ADDR_CTRL Routing Specification

NO.	PARAMETER	MIN	TYP	MAX	UNIT	NOTES
1	Center to Center CK-CK spacing			2w
2	CK A to B/A to C Skew Length Mismatch			25	Mils	See Note(1)
3	CK B to C Skew Length Mismatch			25	Mils
4	Center to Center CK to other LPDDR trace spacing	4w				See Note(2)
5	CK/ADDR_CTRL nominal trace length	CACLM-50	CACLM	CACLM+50	Mils	See Note(3)
6	ADDR_CTRL to CK Skew Length Mismatch			100	Mils
7	ADDR_CTRL to ADDR_CTRL Skew Length Mismatch			100	Mils
8	Center to Center ADDR_CTRL to other LPDDR trace 4w spacing	4w				See Note(2)
9	Center to Center ADDR_CTRL to other ADDR_CTRL 3w trace spacing	3w				See Note(2)
10	ADDR_CTRL A to B/A to C Skew Length Mismatch			100	Mils	See Note(1)
11	ADDR_CTRL B to C Skew Length Mismatch			100	Mils

(1) Series terminator, if used, should be located closest to device.

(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.

Figure 6-22 shows the topology and routing for the DQS and DQ net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended.

Figure 6-22 DQS and DQ Routing and Topology

Table 6-21 DQS and DQ Routing Specification⁽¹⁾

NO.	PARAMETER	MIN	TYP	MAX	UNIT	NOTES
2	DQS E Skew Length Mismatch			25	Mils
3	Center to Center DQS to other LPDDR trace spacing	4w				See Note(2)
4	DQS/DQ nominal trace length	DQLM - 50	DQLM	DQLM + 50	Mils	See Note(2)
5	DQ to DQS Skew Length Mismatch			100	Mils
6	DQ to DQ Skew Length Mismatch			100	Mils
7	Center to Center DQ to other LPDDR trace spacing	4w				See Note(2)
8	Center to Center DQ to other DQ trace spacing	3w				See Note(2),(3)
9	DQ E Skew Length Mismatch			100	Mils

(1) Series terminator, if used, should be located closest to LPDDR.

(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(3) DQLM is the longest Manhattan distance of the DQS and DQ net classes.

6.4.2.2 DDR2 Interface

This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need for a complex timing closure process. For more information regarding guidelines for using this DDR2 specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).

6.4.2.2.3 PCB Stackup

The minimum stackup required for routing the AM3517/05 is a six-layer stack as listed in Table 6-23. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint.

Table 6-23 Minimum PCB Stack Up

Layer	Type	Description
1	Signal	Top Routing Mostly Horizontal
2	Plane	Ground
3	Plane	Power
4	Signal	Internal Routing
5	Plane	Ground
6	Signal	Bottom Routing Mostly Vertical

Complete stack up specifications are provided in Table 6-24.

Figure 6-23 DDR2 Dual-Memory High Level Schematic

Figure 6-24 DDR2 Single-Memory High Level Schematic

Table 6-24 PCB Stack Up Specifications

No.	Parameter	Min	Typ	Max	Unit	Notes
1	PCB Routing/Plane Layers	6
2	Signal Routing Layers	3
3	Full ground layers under DDR2 routing Region	2
4	Number of ground plane cuts allowed within DDR routing region			0
5	Number of ground reference planes required for each DDR2 routing layer	1
6	Number of layers between DDR2 routing layer and ground plane			0
7	PCB Routing Feature Size		4		Mils
8	PCB Trace Width w		4		Mils
9	PCB BGA escape via pad size		20		Mils
10	PCB BGA escape via hole size		10		Mils
11	AM3517/05 BGA pad size		12			See Note (1)
12	DDR2 Device BGA pad size					See Note (2)
13	Single Ended Impedance, Zo	50		75	Ω
14	Impedance Control	Z-5	Z	Z+5	Ω	See Note (3)

(1) The recommended pad size is 0.3 mm per IPC-7351 specification.

(2) Please refer to IPC standard IPC-7351 or manufacturer's recommendations for correct BGA pad size.

(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.

6.4.2.2.4 Placement

Figure 6-24 shows the required placement for the DDR2 devices. The dimensions for Figure 6-25 are defined in Table 6-25. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the placement.

Figure 6-25 DDR2 Device Placement

Table 6-25 Placement Specifications

No.	Parameter	Min	Max	Unit	Notes
1	X		1750	Mils	See Notes (1), (2)
2	Y		1280	Mils	See Notes (1), (2)
3	Y Offset		650	Mils	See Notes (1). (2), (3)
4	DDR2 Keepout Region				See Note (4)
5	Clearance from non-DDR2 signal to DDR2 Keepout Region	4		w	See Note (5)

(1) See Figure 6-23 for dimension definitions.

(2) Measurements from center of AM3517/05 device to center of DDR2 device.

(3) For single memory systems it is recommended that Y Offset be as small as possible.

(4) DDR2 Keepout region to encompass entire DDR2 routing area

(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.

6.4.2.2.5 DDR2 Keep Out Region

The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep out region is defined for this purpose and is shown in Figure 6-26. The size of this region varies with the placement and DDR routing. Additional clearances required for the keep out region are listed in Table 6-25.

Figure 6-26 DDR2 Keepout Region

6.4.2.2.10 VREF Routing

VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM3517/05. VREF is intended to be half of the DDR2 power supply voltage and should be created using a resistive divider as shown in Figure 6-23. Other methods of creating VREF are not recommended. Figure 6-27 shows the layout guidelines for VREF.

Figure 6-27 VREF Routing and Topology

6.4.2.2.11 DDR2 CLK and ADDR_CTRL Routing

Figure 6-28 shows the topology of the routing for the CLK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized.

Figure 6-28 CLK and ADDR_CTRL Routing and Topology

Table 6-31 CLK and ADDR_CTRL Routing Specification ⁽¹⁾

No	Parameter	Min	Typ	Max	Unit	Notes
1	Center to center DQS-DQSN spacing			2w
2	CK differential pair Skew Length Mismatch(4)			25	Mils	See Note (1)
3	CLKB to CLKC Skew Length Mismatch			25	Mils
4	Center to center CLK to other DDR2 trace spacing	4w				See Note (3)
5	CK/ADDR_CTRL nominal trace length	CACLM-50	CACLM	CACLM+50	Mils	See Note (2)
6	ADDR_CTRL to CLK Skew Length Mismatch			100	Mils
7	ADDR_CTRL to ADDR_CTRL Skew Length Mismatch			100	Mils
8	Center to center ADDR_CTRL to other DDR2 trace spacing	4w				See Note (3)
9	Center to center ADDR_CTRL to other ADDR_CTRL trace spacing	3w				See Note (3)
10	ADDR_CTRL A to B, ADDR_CTRL A to C, Skew Length Mismatch			100	Mils	See Note (1)
11	ADDR_CTRL B to C Skew Length Mismatch			100	Mils

(1) Series terminator, if used, should be located closest to AM3517/05.

(2) CACLM is the longest Manhattan distance of the CLK and ADDR_CTRL net classes.

(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(4) Differential impedance should be 100-ohms.

Figure 6-29 shows the topology and routing for the DQS and Dx net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended.

Figure 6-29 DQS and Dx Routing and Topology

Table 6-32 DQS and Dx Routing Specification⁽⁶⁾⁽¹⁾

No.	Parameter	Min	Typ	Max	Unit	Notes
1	Center to center DQS-DQSN spacing			2w
2	DQS E differential pair Skew Length Mismatch(7)			25	Mils
3	Center to center DQS to other DDR2 trace spacing	4w				See Note (4)
4	DQS/Dx nominal trace length	DQLM-50	DQLM	DQLM+50	Mils	See Notes (1), (3)
5	Dx to DQS Skew Length Mismatch			100	Mils	See Note (3)
6	Dx to Dx Skew Length Mismatch			100	Mils	See Note (3)
7	Center to center Dx to other DDR2 trace spacing	4w				See Notes (4), (5)
8	Center to Center Dx to other Dx trace spacing	3w				See Notes (2), (4)

(1) Series terminator, if used, should be located closest to DDR.

(2) DQLM is the longest Manhattan distance of each of the DQS and Dx net classes.

(3) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte 1.

(4) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(5) Dx's from other DQS domains are considered other DDR2 trace.

(6) "Dx" indicates a data line. E indicates length of DQS differential pair or Dx signal.

(7) Differential impedance should be 100-ohms.

Figure 6-30 shows the routing for the SDRC_STRBENx net classes. Table 6-33 contains the routing specification. SDRC_STRBENx net classes should be shielded from or routed on different layers than the DQx net classes.

Figure 6-30 SDRC_STRBENx Routing

Table 6-33 SDRC_STRBENx Routing Specification⁽⁴⁾⁽⁵⁾

No.	Parameter	Min	Typ	Max	Unit	Notes
1	SDRC_STRBEN0 Length F		CKB0B1			See Note (1)
	SDRC_STRBEN1 Length F		CKB0B2			See Note (2)
3	Center to center SDRC_STRBENx to any other trace spacing	4w
4	DQS/Dx nominal trace length	DQLM-50	DQLM	DQLM+50	Mils
5	SDRC_STRBENx Skew			100	Mils	See Note (3)

(1) CKB0B1 is the sum of the length of the CLK (the portion that goes to the memory associated with DQS0 and DQS1) plus the average length of the DQS0 and DQS1 differential pairs.

(2) CKB0B2 is the sum of the length of the CLK (the portion that goes to the memory associated with DQS2 and DQS3) plus the average length of the DQS2 and DQS3 differential pairs.

(3) Skew from CKB0B1 or CKB0B2.

(4) STRBENx termination resistors should be placed close to AM3517/05 STRBENx signal (not close to STRBEN_DLYx signal).

(5) Ensure signal velocities across different layers are taken into account when calculating STRBENx length. For example, if DQS0 and DSQ1 are 1inch each, and DQS0 is on a layer that is 10% faster, use 1.1inch as the length for DQS0.

6.4.2.2.12 On Die Termination (ODT)

ODT should only be used with 1 chip select as shown in Figure 6-31. If using sdrc_cs0 and sdrc_cs1, sdrc_odt should not be used. ODT signals should be tied off at the memory.

Figure 6-31 ODT Connection Using One Chip select (sdrc_cs0)

6.5.1.1 Video Processing Front End (VPFE)

The Video Processing Front-End (VPFE) controller receives input video/image data from external capture devices and stores it to external memory which is transferred into the external memory via a built in DMA engine. An internal buffer block provides a high bandwidth path between the VPSS module and the external memory. The Cortex-A8 will process the image data based on application requirements.

6.5.1.1.1 Video Processing Front End (VPFE) Timing

Table 6-34 and Table 6-35 assume testing over recommended operating conditions.

Table 6-34 VPFE Timing Requirements

NO.	PARAMETER		1.8V, 3.3V
			MIN	MAX	UNIT
VF1	tc(VDIN_CLK)	Cycle time, pixel clock input, VDIN_CLK	13.33	100	ns
VF2	tsu(VDIN_D-VDIN_CLK)	Setup time, VDIN_D to VDIN_CLK rising edge	3.5		ns
VF3	tsu(VDIN_HD-VDIN_CLK)	Setup time, VDIN_HD to VDIN_CLK rising edge	3.5		ns
VF4	tsu(VDIN_VD-VDIN_CLK)	Setup time, VDIN_VD to VDIN_CLK rising edge	3.5		ns
VF5	tsu(VDIN_WEN-VDIN_CLK)	Setup time, VDIN_WEN to VDIN_CLK rising edge	3.5		ns
VF6	tsu(C_FLD-VDIN_CLK)	Setup time, VDIN_FIELD to VDIN_CLK rising edge	3.5		ns
VF7	th(VDIN_CLK-VDIN_D)	Hold time, VDIN_D valid after VDIN_CLK rising edge	2.5		ns
VF8	th(VDIN-HD-VDIN_CLK)	Hold time, VDIN_HD to VDIN_CLK rising edge	2.5		ns
VF9	th(VDIN_VD-VDIN_CLK)	Hold time, VDIN_VD to VDIN_CLK rising edge	2.5		ns
VF10	th(VDIN_WEN-VDIN_CLK)	Hold time, VDIN_WEN to VDIN_CLK rising edge	2.5		ns
VF11	th(C_FLD-VDIN_CLK)	Hold time, VDIN_FIELD to VDIN_CLK rising edge	2.5		ns

Table 6-35 VPFE Output Switching Characteristics

NO.	PARAMETER		1.8V, 3.3V
			MIN	MAX	UNIT
VF12	td(VDIN_HD-VDIN_CLK)	Output delay time, VDIN_HD to CLK rising edge		10	ns
VF13	td(VDIN_VD-VDIN_CLK)	Output delay time, VDIN_VD to CLK rising edge		10	ns
VF14	td(VDIN_WEN-VDIN_CLK)	Output delay time, VDIN_WEN to CLK rising edge		10	ns
VF15	toh(VDIN_HD-VDIN_CLK)	Output hold time, VDIN_HD to CLK rising edge	0.5		ns
VF16	toh(VDIN_VD-VDIN_CLK)	Output hold time, VDIN_VD to CLK rising edge	0.5		ns
VF17	toh(C_FLD-VDIN_CLK)	Output hold time, VDIN_FLD to CLK rising edge	0.5		ns

Figure 6-32 VPFE0 Input Timings

Figure 6-33 VPFE Output Timings

Figure 6-34 VPFE Input Timings With VDIN0_HD as Pixel Clock

6.5.2.1 LCD Display Support in Bypass Mode

Two types of LCD panel are supported:

• Thin film transistor (TFT) or active matrix technology
• Supertwisted nematic (STN) or passive matrix technology

Both configurations are discussed in the following paragraphs.

6.5.2.1.1 LCD Display in TFT Mode

Table 6-36 assumes testing over the recommended operating conditions (see Figure 6-35).

Table 6-36 LCD Display Interface Switching Characteristics in TFT Mode⁽²⁾

NO.	PARAMETER		1.8V, 3.3V		UNIT
			MIN	MAX
DL0	td(PCLKA-HSYNCT)	Delay time, dss_pclk active edge to dss_hsync transition	-4.215	4.215	ns
DL1	td(PCLKA-VSYNCT)	Delay time, dss_pclk active edge to dss_vsync transition	-4.215	4.215	ns
DL2	td(PCLKA-ACBIASA)	Delay time, dss_pclk active edge to dss_acbias active level	-4.215	4.215	ns
DL3	td(PCLKA-DATAV)	Delay time, dss_pclk active edge to dss_data bus valid	-4.215	4.215	ns
DL4	tc(PCLK)	Cycle time(1), dss_pclk	13.468		ns
DL5	tw(PCLK)	Pulse duration, dss_pclk low or high	6.06	7.46	ns
	cload	Load capacitance		25	pF

(1) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the DISPC_DIVISOR register.

(2) The capacitive load is equivalent to 25 pF.

Figure 6-35 LCD Display in TFT Mode^(1)(2)(3)(4)

1. The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
2. The pixel clock frequency is programmable.
3. All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.
4. For more information, see the AM35x ARM Microprocessor Technical Reference Manual (SPRUGR0).

6.5.2.1.2 LCD Display in STN Mode

Table 6-37 assumes testing over the recommended operating conditions (see Figure 6-36).

Table 6-37 LCD Display Interface Switching Characteristics in STN Mode^(2)(3)(4)

NO.	PARAMETER		1.8V, 3.3V		UNIT
			MIN	MAX
DL3	td(PCLKA-DATAV)	Delay time, dss_pclk active edge to dss_data bus valid	-4.21	6.9	ns
DL4	tc(PCLK)	Cycle time(1), dss_pclk	22.73		ns
DL5	tw(PCLK)	Pulse duration, dss_pclk low or high	10.23	12.5	ns
	cload	Load capacitance		40	pF

(1) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the DISPC_DIVISOR register.

(2) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.

(3) The capacitive load is equivalent to 40 pF.

(4) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (SPRUGR0).

Figure 6-36 LCD Display in STN Mode^{(1)(2)(3)(4)(5)}

1. The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
2. All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.
3. dss_vsync width must be programmed to be as small as possible.
4. The pixel clock frequency is programmable.
5. For more information, see the AM35x ARM Microprocessor Technical Reference Manual (SPRUGR0).

6.6.1.1 McBSP in Normal Mode

Table 6-38 through Table 6-40 assume testing over the recommended operating conditions.