Table 5-1 Absolute Maximum Ratings Over Operating Junction Temperature Range

Table 5-2 Handling Ratings

Table 5-3 Recommended Operating Conditions

Table 5-4 Estimated Power Consumption at Ball Level

Table 5-5 DC Electrical Characteristics

Table 5-6 Package Thermal Resistance Characteristics [ZCN Package]

Table 5-7 Package Thermal Resistance Characteristics [ZER]⁽⁴⁾

Table 5-8 Core Voltage Decoupling Characteristics

5.8.1 Power-up Sequence

The following steps give an example of power-up sequence supported by the AM3517/05.

1. IO 1.8V supply (VDDS), Band-gap and LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) and oscillator supply (VDDSOSC) should come up first to a stable state.
2. IO 3.3V (VDDSHV) supply should be ramped up next to a stable state.
3. Core (VDD_CORE) supply follows next to a stable state.
4. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) and 1.8 V complex IO supplies (VDDA_DAC, VDDA1P8V_USBPHY) should be ramped up next to a stable state.
5. Finally, 3.3 V complex IO (VDDA_3P3V_USBPHY) should be ramped up.
6. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the sys_32k and sys_xtalin clocks are stable.

Note: In VDDSHV 1.8 V operation mode, VDDSHV can be grouped and powered up together with VDDS, VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU and VDDSOSC.

Figure 5-3 shows the power-up sequence.

Figure 5-3 Power-up Sequence

5.8.2 Power-down Sequence

The AM3517/05 device proceeds with the power-down sequence shown below.

The following steps give an example of the power-down sequence supported by the AM3517/05 device.

1. Reset AM3517/05 device.
2. Stop all signals driven to AM3517/05.
3. Option 1: Power down all domains simutaneously.
4. Option 2: If all domains cannot be powered down simultaneously, follow the below sequence:
   1. Power off all complex I/O domains
   2. Power off core domain (VDD_CORE)
   3. Power off all PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE)
   4. Power off all SRAM LDOs
   5. Power off all standard I/O domains (VDDS and VDDSHV)

5.9.1 Oscillator

The sys_xtalin (26 MHz) oscillator provides the primary reference clock for the device. The on-chip oscillator requires an external crystal connected across the sys_xtalin and sys_xtalout pins, along with two load capacitors, as shown in Figure 4-3. The external crystal load capacitors must be connected only to the oscillator ground pin (VSSOSC). Do not connect to board ground (VSS).

Note: If an external oscillator is to be used, the external oscillator clock signal should be connected to the sys_xtalin pin with a 1.8V amplitude. The sys_xtalout should be left unconnected and the VSSOSC signal should be connected to board ground (VSS).

A. Oscillator components (Crystal, C₁, C₂) must be located close to the AM35x package. Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator. The VSSOSC terminal provides a Kelvin ground reference for the external crystal components. External crystal component grounds should only be connected to the VSSOSC terminal and should not be connected to the PCB ground plane.

B. C₁ and C₂ represent the total capacitance of the respective PCB trace, load capacitor, and other components (excluding the crystal) connected to each crystal terminal. The value of capacitors C₁ and C₂ should be selected to provide the total load capacitance, C_L, specified by the crystal manufacturer. The total load capacitance is C_L = [(C₁*C₂)/(C₁+C₂)] + C_shunt, where C_shunt is the crystal shunt capacitance (C₀) specified by the crystal manufacturer plus any mutual capacitance (C_pkg + C_PCB) seen across the AM3517/05 sys_xtalin and sys_xtalout signals. For recommended values of crystal circuit components, see Table 5-9.

AM3517/05 Oscillator Connections

5.9.2 Input Clock Specifications

The clock system accepts three input clock sources:

• 32-kHz digital CMOS clock
• Crystal oscillator clock or CMOS digital clock (26 MHz)
• Alternate clock (48 or 54 MHz, or other up to 54 MHz)

Table 5-11 and Table 5-12 detail the electrical characteristics and input requirements of the 32-kHz input clock.

Table 5-13 and Table 5-14 detail the electrical characteristics and input requirements of the 48- or 54-MHz input clock.

5.9.3 Output Clock Specifications

Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:

• sys_clkout1 can output the oscillator clock (26 MHz) at any time. It can be controlled by software or externally using sys_clkreq control. When the device is in the off state, the sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the device. The off state polarity of sys_clkout1 is programmable.
• sys_clkout2 can output sys_clk (26 MHz), core_clk (core DPLL output), APLL-96 MHz, or APLL-54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. This output is active only when the core domain is active.

Table 5-15 summarizes the sys_clkout1 output clock electrical characteristics.

Table 5-16 details the sys_clkout1 output clock timing characteristics.

Figure 5-6 SYS_CLKOUT1 System Output Clock

Table 5-17 summarizes the sys_clkout2 output clock electrical characteristics.

Table 5-18 details the sys_clkout2 output clock timing characteristics.

Figure 5-7 SYS_CLKOUT2 System Output Clock

5.9.4 DPLL Specifications

The AM3517/05 integrates four DPLLs. The PRM and CM drive them.

The four main DPLLs are:

• DPLL1 (MPU)
• DPLL3 (Core)
• DPLL4 (Peripherals)
• DPLL5 (Second Peripherals DPLL)

Figure 5-8 shows the DPLL implementation.

Figure 5-8 DPLL Implementation

5.9.4.2 DPLL Noise Isolation

The DPLL requires dedicated power supply pins to isolate the core analog circuit from the switching noise generated by the core logic that can cause jitter on the clock output signal. Guard rings are added to the cell to isolate it from substrate noise injection.

The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the supply rails. The maximum input noise level allowed is 30 mV_PP for frequencies below 1 MHz.

Figure 5-9 shows an example of a noise filter.

Figure 5-9 DPLL Noise Filter

Table 5-19 specifies the noise filter requirements.

Table 5-19 DPLL Noise Filter Requirements

NAME	MIN	TYP	MAX	UNIT
Filtering capacitor		100		nF

1. The capacitors must be inserted between power and ground as close as possible.
2. This circuit is provided only as an example.
3. The filter must be located as close as possible to the device.
4. No filtering required if noise is below 10 mV_PP.

5.10.1 Interface Description

Table 5-20 summarizes the external pins of the video DAC.

5.10.2 Electrical Specifications Over Recommended Operating Conditions

(T_MIN to T_MAX, vdda_dac = 1.8 V, R_OUT1/2 = 1650Ω , R_LOAD = 75Ω , unless otherwise noted)

(T_MIN to T_MAX, vdda_dac = 1.8 V, R_OUT1/2 = 1650 , R_LOAD = 75 , unless otherwise noted)

5.10.3 Analog Supply (vdda_dac) Noise Requirements

In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the noise requirements stated in this section.

The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of supply variation as shown in the following equation:

Depending on frequency, the PSRR is defined in Table 5-23.

A graphic representation is shown in Figure 5-11.

Figure 5-11 Video DAC Power Supply Rejection Ratio

To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements translate to the following limits on vdda_dac (for the Video DAC).

The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-24:

The maximum noise spectral density (white noise) is defined in Table 5-25:

Because the DAC PSRR deteriorates at a rate of 20 dB/dec after 100 kHz, it is highly recommended to have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: Section 5.10.4, External Component Value Choice).

5.10.4 External Component Value Choice

The full-scale output voltage V_OUTMAX is regulated by the reference amplifier, and is set by an internal resistor R_SET. I_OUTMAX can be expressed as:

Where:

The output current I_OUT appearing at DAC output is a function of both the input code and I_OUTMAX and can be expressed as:

Where:

The output voltage is:

Where:

The TV-out buffer requires a per channel external resistors: R_OUT1/2. The equation below can be used to select different resistor values (if necessary):

Recommended parameter values are:

In order to limit the reference noise bandwidth and to suppress transients on V_REF, it is necessary to connect a large decoupling capacitor ©_BG) between the tv_vref and vssa_dac pins.