SPRS681G October   2010  – March 2015 AM3892 , AM3894

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 ARM Subsystem
      1. 3.2.1 ARM Cortex-A8 RISC Processor
      2. 3.2.2 Embedded Trace Module (ETM)
      3. 3.2.3 ARM Cortex-A8 Interrupt Controller (AINTC)
      4. 3.2.4 System Interconnect
    3. 3.3 Media Controller
    4. 3.4 Inter-Processor Communication
      1. 3.4.1 Mailbox Module
        1. 3.4.1.1 Mailbox Registers
      2. 3.4.2 Spinlock Module
        1. 3.4.2.1 Spinlock Registers
    5. 3.5 Power, Reset and Clock Management (PRCM) Module
    6. 3.6 SGX530 (AM3894 only)
    7. 3.7 Memory Map Summary
      1. 3.7.1 L3 Memory Map
      2. 3.7.2 L4 Memory Map
        1. 3.7.2.1 L4 Standard Peripheral
        2. 3.7.2.2 L4 High-Speed Peripheral
      3. 3.7.3 TILER Extended Addressing Map
      4. 3.7.4 Cortex™-A8 Memory Map
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Assignments
      1. 4.1.1 Pin Map (Bottom View)
    2. 4.2 Terminal Functions
      1. 4.2.1  Boot Configuration
      2. 4.2.2  DDR2 and DDR3 Memory Controller Signals
      3. 4.2.3  Ethernet Media Access Controller (EMAC) Signals
      4. 4.2.4  General-Purpose Input/Output (GPIO) Signals
      5. 4.2.5  General-Purpose Memory Controller (GPMC) Signals
      6. 4.2.6  High-Definition Multimedia Interface (HDMI) Signals
      7. 4.2.7  Inter-Integrated Circuit (I2C) Signals
      8. 4.2.8  Multichannel Audio Serial Port Signals
      9. 4.2.9  Multichannel Buffered Serial Port Signals
      10. 4.2.10 Oscillator/Phase-Locked Loop (PLL) Signals
      11. 4.2.11 Peripheral Component Interconnect Express (PCIe) Signals
      12. 4.2.12 Reset, Interrupts, and JTAG Interface Signals
      13. 4.2.13 Secure Digital/Secure Digital Input Output (SD/SDIO) Signals
      14. 4.2.14 Serial ATA Signals
      15. 4.2.15 Serial Peripheral Digital Interconnect Format (SPI) Signals
      16. 4.2.16 Timer Signals
      17. 4.2.17 Universal Asynchronous Receiver/Transmitter (UART) Signals
      18. 4.2.18 Universal Serial Bus (USB) Signals
      19. 4.2.19 Video Input Signals
      20. 4.2.20 Digital Video Output Signals
      21. 4.2.21 Analog Video Output Signals
      22. 4.2.22 Reserved Pins
      23. 4.2.23 Supply Voltages
      24. 4.2.24 Ground Pins (VSS)
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (Unless Otherwise Noted)
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Resistance Characteristics
  6. 6 Device Configurations
    1. 6.1 Control Module
    2. 6.2 Revision Identification
    3. 6.3 Debugging Considerations
      1. 6.3.1 Pullup and Pulldown Resistors
    4. 6.4 Boot Sequence
      1. 6.4.1 Boot Mode Registers
    5. 6.5 Pin Multiplexing Control
      1. 6.5.1 PINCTRLx Register Descriptions
    6. 6.6 How to Handle Unused Pins
  7. 7 System Interconnect
    1. 7.1 L3 Interconnect
    2. 7.2 L4 Interconnect
  8. 8 Power, Reset, Clocking, and Interrupts
    1. 8.1 Power Supplies
      1. 8.1.1 Voltage and Power Domains
      2. 8.1.2 Power Domains
      3. 8.1.3 1-V AVS and 1-V Constant Power Domains
      4. 8.1.4 SmartReflex™
      5. 8.1.5 Memory Power Management
      6. 8.1.6 IO Power-Down Modes
      7. 8.1.7 Supply Sequencing
      8. 8.1.8 Power-Supply Decoupling
    2. 8.2 Reset
      1. 8.2.1  System-Level Reset Sources
      2. 8.2.2  Power-On Reset (POR pin)
      3. 8.2.3  External Warm Reset (RESET pin)
      4. 8.2.4  Emulation Warm Reset
      5. 8.2.5  Watchdog Reset
      6. 8.2.6  Software Global Cold Reset
      7. 8.2.7  Software Global Warm Reset
      8. 8.2.8  Test Reset (TRST pin)
      9. 8.2.9  Local Reset
      10. 8.2.10 Reset Priority
      11. 8.2.11 Reset Status Register
      12. 8.2.12 PCIe Reset Isolation
      13. 8.2.13 RSTOUT
      14. 8.2.14 Effect of Reset on Emulation and Trace
      15. 8.2.15 Reset During Power Domain Switching
      16. 8.2.16 Pin Behaviors at Reset
      17. 8.2.17 Reset Electrical Data and Timing
    3. 8.3 Clocking
      1. 8.3.1 Device Clock Inputs
        1. 8.3.1.1 Using the Internal Oscillators
      2. 8.3.2 SERDES_CLKN and SERDES_CLKP Input Clock
      3. 8.3.3 CLKIN32 Input Clock
      4. 8.3.4 PLLs
        1. 8.3.4.1 PLL Programming Limits
        2. 8.3.4.2 PLL Power Supply Filtering
        3. 8.3.4.3 PLL Locking Sequence
        4. 8.3.4.4 PLL Registers
      5. 8.3.5 SYSCLKs
      6. 8.3.6 Module Clocks
      7. 8.3.7 Output Clock Select Logic
    4. 8.4 Interrupts
      1. 8.4.1 Interrupt Summary List
      2. 8.4.2 Cortex™-A8 Interrupts
  9. 9 Peripheral Information and Timings
    1. 9.1  Parameter Information
      1. 9.1.1 1.8-V and 3.3-V Signal Transition Levels
      2. 9.1.2 3.3-V Signal Transition Rates
      3. 9.1.3 Timing Parameters and Board Routing Analysis
    2. 9.2  Recommended Clock and Control Signal Transition Behavior
    3. 9.3  DDR2 and DDR3 Memory Controller
      1. 9.3.1 DDR2 Routing Specifications
        1. 9.3.1.1 Board Designs
        2. 9.3.1.2 DDR2 Interface
          1. 9.3.1.2.1  DDR2 Interface Schematic
          2. 9.3.1.2.2  Compatible JEDEC DDR2 Devices
          3. 9.3.1.2.3  PCB Stackup
          4. 9.3.1.2.4  Placement
          5. 9.3.1.2.5  DDR2 Keepout Region
          6. 9.3.1.2.6  Bulk Bypass Capacitors
          7. 9.3.1.2.7  High-Speed Bypass Capacitors
          8. 9.3.1.2.8  Net Classes
          9. 9.3.1.2.9  DDR2 Signal Termination
          10. 9.3.1.2.10 VREFSSTL_DDR Routing
        3. 9.3.1.3 DDR2 CK and ADDR_CTRL Routing
      2. 9.3.2 DDR3 Routing Specifications
        1. 9.3.2.1  Board Designs
          1. 9.3.2.1.1 DDR3 versus DDR2
        2. 9.3.2.2  DDR3 Device Combinations
          1. 9.3.2.2.1 DDR3 EMIFs
        3. 9.3.2.3  DDR3 Interface Schematic
          1. 9.3.2.3.1 32-Bit DDR3 Interface
          2. 9.3.2.3.2 16-Bit DDR3 Interface
        4. 9.3.2.4  Compatible JEDEC DDR3 Devices
        5. 9.3.2.5  PCB Stackup
        6. 9.3.2.6  Placement
        7. 9.3.2.7  DDR3 Keepout Region
        8. 9.3.2.8  Bulk Bypass Capacitors
        9. 9.3.2.9  High-Speed Bypass Capacitors
          1. 9.3.2.9.1 Return Current Bypass Capacitors
        10. 9.3.2.10 Net Classes
        11. 9.3.2.11 DDR3 Signal Termination
        12. 9.3.2.12 VREFSSTL_DDR Routing
        13. 9.3.2.13 VTT
        14. 9.3.2.14 CK and ADDR_CTRL Topologies and Routing Definition
          1. 9.3.2.14.1 Four DDR3 Devices
            1. 9.3.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 9.3.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 9.3.2.14.2 Two DDR3 Devices
            1. 9.3.2.14.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 9.3.2.14.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 9.3.2.14.3 One DDR3 Device
            1. 9.3.2.14.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 9.3.2.14.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
        15. 9.3.2.15 Data Topologies and Routing Definition
          1. 9.3.2.15.1 DQS, DQ and DM Topologies, Any Number of Allowed DDR3 Devices
          2. 9.3.2.15.2 DQS, DQ and DM Routing, Any Number of Allowed DDR3 Devices
        16. 9.3.2.16 Routing Specification
          1. 9.3.2.16.1 CK and ADDR_CTRL Routing Specification
          2. 9.3.2.16.2 DQS and DQ Routing Specification
      3. 9.3.3 DDR2 and DDR3 Memory Controller Register Descriptions
      4. 9.3.4 DDR2 and DDR3 PHY Register Descriptions
      5. 9.3.5 DDR2 and DDR3 Memory Controller Electrical Data and Timing
    4. 9.4  Emulation Features and Capability
      1. 9.4.1 Advanced Event Triggering (AET)
      2. 9.4.2 Trace
      3. 9.4.3 IEEE 1149.1 JTAG
        1. 9.4.3.1 JTAG ID (JTAGID) Register Description
        2. 9.4.3.2 JTAG Electrical Data and Timing
      4. 9.4.4 IEEE 1149.7 cJTAG
    5. 9.5  Enhanced Direct Memory Access (EDMA) Controller
      1. 9.5.1 EDMA Channel Synchronization Events
      2. 9.5.2 EDMA Peripheral Register Descriptions
    6. 9.6  Ethernet Media Access Controller (EMAC)
      1. 9.6.1 EMAC Peripheral Register Descriptions
      2. 9.6.2 EMAC Electrical Data and Timing
      3. 9.6.3 Management Data Input and Output (MDIO)
        1. 9.6.3.1 MDIO Peripheral Register Descriptions
        2. 9.6.3.2 MDIO Electrical Data and Timing
    7. 9.7  General-Purpose Input and Output (GPIO)
      1. 9.7.1 GPIO Peripheral Register Descriptions
      2. 9.7.2 GPIO Electrical Data and Timing
    8. 9.8  General-Purpose Memory Controller (GPMC) and Error Locator Module (ELM)
      1. 9.8.1 GPMC and ELM Peripheral Register Descriptions
      2. 9.8.2 GPMC Electrical Data and Timing
        1. 9.8.2.1 GPMC and NOR Flash Interface Synchronous Mode Timing
        2. 9.8.2.2 GPMC and NOR Flash Interface Asynchronous Mode Timing
        3. 9.8.2.3 GPMC and NAND Flash Interface Asynchronous Mode Timing
    9. 9.9  High-Definition Multimedia Interface (HDMI)
      1. 9.9.1 HDMI Interface Design Specifications
        1. 9.9.1.1 HDMI Interface Schematic
        2. 9.9.1.2 TMDS Routing
        3. 9.9.1.3 DDC Signals
        4. 9.9.1.4 HDMI ESD Protection Device (Required)
        5. 9.9.1.5 PCB Stackup Specifications
        6. 9.9.1.6 Grounding
      2. 9.9.2 HDMI Peripheral Register Descriptions
    10. 9.10 High-Definition Video Processing Subsystem (HDVPSS)
      1. 9.10.1 HDVPSS Electrical Data and Timing
      2. 9.10.2 Video DAC Guidelines and Electrical Data and Timing
    11. 9.11 Inter-Integrated Circuit (I2C)
      1. 9.11.1 I2C Peripheral Register Descriptions
      2. 9.11.2 I2C Electrical Data and Timing
    12. 9.12 Multichannel Audio Serial Port (McASP)
      1. 9.12.1 McASP Device-Specific Information
      2. 9.12.2 McASP0, McASP1, and McASP2 Peripheral Register Descriptions
      3. 9.12.3 McASP Electrical Data and Timing
    13. 9.13 Multichannel Buffered Serial Port (McBSP)
      1. 9.13.1 McBSP Peripheral Registers
      2. 9.13.2 McBSP Electrical Data and Timing
    14. 9.14 Peripheral Component Interconnect Express (PCIe)
      1. 9.14.1 PCIe Design and Layout Specifications
        1. 9.14.1.1 Clock Source
        2. 9.14.1.2 PCIe Connections and Interface Compliance
          1. 9.14.1.2.1 Coupling Capacitors
          2. 9.14.1.2.2 Polarity Inversion
          3. 9.14.1.2.3 Lane Reversal
        3. 9.14.1.3 Non-Standard PCIe Connections
          1. 9.14.1.3.1 PCB Stackup Specifications
          2. 9.14.1.3.2 Routing Specifications
      2. 9.14.2 PCIe Peripheral Register Descriptions
      3. 9.14.3 PCIe Electrical Data and Timing
    15. 9.15 Real-Time Clock (RTC)
      1. 9.15.1 RTC Register Descriptions
    16. 9.16 Secure Digital and Secure Digital Input Output (SD and SDIO)
      1. 9.16.1 SD and SDIO Peripheral Register Descriptions
      2. 9.16.2 SD and SDIO Electrical Data and Timing
        1. 9.16.2.1 SD Identification and Standard SD Mode
        2. 9.16.2.2 High-Speed SD Mode
    17. 9.17 Serial ATA Controller (SATA)
      1. 9.17.1 SATA Interface Design Specifications
        1. 9.17.1.1 SATA Interface Schematic
        2. 9.17.1.2 Compatible SATA Components and Modes
        3. 9.17.1.3 PCB Stackup Specifications
        4. 9.17.1.4 Routing Specifications
        5. 9.17.1.5 Coupling Capacitors
      2. 9.17.2 SATA Peripheral Register Descriptions
    18. 9.18 Serial Peripheral Interface (SPI)
      1. 9.18.1 SPI Peripheral Register Descriptions
      2. 9.18.2 SPI Electrical Data and Timing
    19. 9.19 Timers
      1. 9.19.1 Timer Peripheral Register Descriptions
      2. 9.19.2 Timer Electrical Data and Timing
    20. 9.20 Universal Asynchronous Receiver and Transmitter (UART)
      1. 9.20.1 UART Peripheral Register Descriptions
      2. 9.20.2 UART Electrical Data and Timing
    21. 9.21 Universal Serial Bus (USB2.0)
      1. 9.21.1 USB2.0 Peripheral Register Descriptions
      2. 9.21.2 USB2.0 Electrical Data and Timing
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
      2. 10.1.2 Device and Development Support-Tool Nomenclature
      3. 10.1.3 Device Speed Range Overview
    2. 10.2 Documentation Support
    3. 10.3 Related Links
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

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発注情報

3 Device Comparison

There are variations in the availability of some functions of the AM389x devices. A comparison of the devices, highlighting the differences, is shown in Table 3-1. For more detailed information on the significant device features, see Section 3.1, Device Characteristics.

Table 3-1 Device Comparison

FEATURES DEVICES
AM3894 AM3892
SGX530 Y N

3.1 Device Characteristics

Table 3-2 provides an overview of the significant features of the AM389xdevices, including the capacity of on-chip RAM, peripherals, and the package type with pin count.

Table 3-2 Characteristics of the Processor

HARDWARE FEATURES AM3894 and AM3892
Peripherals


Not all peripherals pins are available at the same time (for more detail, see Section 6, Device Configurations).		 HD Video Processing Subsystem (HDVPSS) 1 16-bit and 24-bit HD Capture Channel or
2 8-bit SD Capture Channels
and
1 16-bit HD Capture Channel or
2 8-bit SD Capture Channels
and
1 16-bit, 24-bit, and 32-bit HD Display Channel
and
1 16-bit HD Display Channel
and
3 HD and 4 SD Video DACs
and
1 HDMI 1.3 Transmitter
DDR2 and DDR3 Memory Controller 2 (32-bit Bus Widths)
GPMC and ELM Asynchronous (8-bit and 16-bit bus width) RAM, NOR, NAND
EDMA 64 Independent Channels
8 QDMA Channels
10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MAC with Management Data Input and Output (MDIO) 2 (with MII and GMII Interface)
USB 2.0 2 (Supports High-Speed and Full-Speed as a Device and High-Speed, Full-Speed, and Low-Speed as a Host)
PCI Express 2.0 1 Port (2 5.0GT per second lanes)
Timers 7 (32-bit General Purpose)
and
1 (Watchdog)
UART 3 (with SIR, MIR, CIR support and RTS and CTS flow control)
(UART0 Supports Modem Interface)
SPI 1 (Supports 4 slave devices)
SD and SDIO 1 (1-bit or 4-bit)
I2C 2 (Master or Slave)
McASP 3 (1 Six-Serializer and 2 Dual Serializers, Each with Transmit and Receive and DIT Capability)
McBSP 1 (2 Data Pins, Transmit and Receive)
Serial ATA (SATA) Supports 2 Interfaces
RTC 1
GPIO Up to 64 pins
On-Chip Memory Organization ARM
32KB I-cache
32KB D-cache
256KB L2 Cache
64KB RAM
48KB Boot ROM
MEDIA CONTROLLER
32KB Shared L1 Cache
256KB L2 RAM
ADDITIONAL SHARED MEMORY
512KB On-chip RAM
CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1003
JTAG BSDL_ID JTAGID Register 0x2B81 E02F
CPU Frequency MHz Up to 1350 MHz
Voltage Core Logic (V) 1.0 V with Required AVS Capability
USB Logic (V) 0.9 V
RAM (V) 1.0 V
IO (V) 1.5 V, 1.8 V, 3.3 V
Package 25 x 25 mm 1031-Pin BGA (CYG)
Process Technology µm 0.04 µm
Product Status(1) Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

3.2 ARM Subsystem

The ARM subsystem is designed to give the ARM Cortex-A8 master control of the device. In general, the ARM Cortex-A8 is responsible for configuration and control of the various subsystem, peripherals, and external memories.

The ARM subsystem includes the following features:

  • ARM Cortex-A8 RISC processor:
    • ARMv7 ISA plus Thumb®-2, Jazelle-X, and media extensions
    • NEON floating-point unit
    • Enhanced memory management unit (MMU)
    • Little Endian
    • 32KB L1 instruction cache
    • 32KB L1 data cache
    • 256KB L2 cache
  • Foresight embedded trace module (ETM)
  • ARM Cortex-A8 interrupt controller (AINTC)
  • 64KB internal RAM
  • 48KB internal public ROM.
AM3894 AM3892 arm_subsys_sprs614.gifFigure 3-1 ARM Cortex-A8 Subsystem Block Diagram

3.2.1 ARM Cortex-A8 RISC Processor

The ARM Cortex-A8 subsystem integrates the ARM Cortex-A8 processor. The ARM Cortex-A8 processor is a member of ARM Cortex family of general-purpose processors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM Cortex-A8 processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM Cortex-A8 processor has a Harvard architecture and provides a complete high-performance subsystem, including:

  • ARM Cortex-A8 integer core
  • Superscalar ARMv7 instruction set
  • Thumb-2 instruction set
  • Jazelle RCT acceleration
  • CP14 debug coprocessor
  • CP15 system control coprocessor
  • NEON 64-bit and 128-bit hybrid SIMD engine for multimedia
  • Enhanced memory management unit (MMU)
  • Separate level-1 instruction and data caches
  • Integrated level-2 cache
  • 128-bit interconnect to system memories and peripherals
  • Embedded trace module (ETM).

3.2.2 Embedded Trace Module (ETM)

To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an embedded trace module (ETM). The ETM consists of two parts:

  • The Trace port provides real-time trace capability for the ARM Cortex-A8.
  • Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers.

The ARM Cortex-A8 trace port is connected to the system-level embedded trace buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are required to read and interpret the captured trace data.

For more details on the ETB, see Section 9.4.2.

3.2.3 ARM Cortex-A8 Interrupt Controller (AINTC)

The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor. For more details on the AINTC, see Section 8.4.

3.2.4 System Interconnect

The ARM Cortex-A8 processor in connected through the arbiter to both an L3 interconnect port and a DMM port. The DMM port is 128-bits wide and provides the ARM Cortex-A8 direct access to the DDR memories, while the L3 interconnect port is 64-bits wide and provides access to the remaining device modules.

3.3 Media Controller

The Media Controller has the responsibility of managing the HDVPSS module.

3.4 Inter-Processor Communication

This device is a multi-core device that requires software to efficiently manage and communicate between the cores. The following are the main features that need to be implemented by such software:

  1. Device management of the slave processors from the host processor.
  2. Inter-processor communication between the cores for transfer and exchange of information between them.

For implementing efficient inter-processor communication between the multiple cores on the device, the following hardware features are provided:

  • Mailbox interrupts
  • Hardware spinlocks

Mailboxes provide a mechanism for one processor to write a value to a register and send an interrupt to another processor. Spinlocks facilitate access to shared resources in the system.

3.4.1 Mailbox Module

The device Mailbox module facilitates communication between the ARM Cortex-A8 and the Media Controller. It consists of twelve mailboxes, each supporting communication between two of the above processors. The sender sends information to the receiver by writing a message to the mailbox registers. Interrupt signaling is used to notify the receiver that a message has been queued or to notify the sender about an overflow situation.

The Mailbox module supports the following features (see Figure 3-2):

  • 12 mailboxes
  • Four-message FIFO depth for each message queue
  • 32-bit message width
  • Message reception and queue-not-full notification using interrupts
  • Three interrupts (one to ARM Cortex-A8, two to Media Controller).
AM3894 AM3892 mailbox_bd_sprs681.gifFigure 3-2 Mailbox Module Block Diagram

3.4.1.1 Mailbox Registers

Table 3-3 lists the Mailboxes available on this device. The register set below is applicable to these mailboxes. Table 3-4 lists the Mailbox registers.

Table 3-3 Mailboxes

MAILBOX TYPE USER NUMBER (u) MAILBOX NUMBER (m) MESSAGES PER MAILBOX
System Mailbox 0 to 3 0 to 11 4

Table 3-4 Mailbox Registers Summary(1)

HEX ADDRESS ACRONYM REGISTER NAME
0x480C 8000 MAILBOX_REVISION Mailbox Revision
0x480C 8010 MAILBOX_SYSCONFIG Mailbox System Configuration
0x480C 8040 + (0x4 * m) MAILBOX_MESSAGE_m Mailbox Message
0x480C 8080 + (0x4 * m) MAILBOX_FIFOSTATUS_m Mailbox FIFO Status
0x480C 80C0 + (0x4 * m) MAILBOX_MSGSTATUS_m Mailbox Message Status
0x480C 8100 + (0x10 * u) MAILBOX_IRQSTATUS_RAW_u Mailbox IRQ RAW Status
0x480C 8104 + (0x10 * u) MAILBOX_IRQSTATUS_CLR_u Mailbox IRQ Clear Status
0x480C 8108 + (0x10 * u) MAILBOX_IRQENABLE_SET_u Mailbox IRQ Enable Set
0x480C 810C + (0x10 * u) MAILBOX_IRQENABLE_CLR_u Mailbox IRQ Enable Clear
0x480C 8140 - Reserved
(1) For the range of m and u, see Table 3-3.

3.4.2 Spinlock Module

The Spinlock module provides hardware assistance for synchronizing the processes running on multiple processors in the device:

  • ARM Cortex-A8 processor
  • Media Controller processors.

The Spinlock module implements 64 spinlocks (or hardware semaphores) that provide an efficient way to perform a lock operation of a device resource using a single read-access, avoiding the need for a read-modify-write bus transfer of which the programmable cores are not capable.

3.4.2.1 Spinlock Registers

Table 3-5 Spinlock Registers Summary(1)

HEX ADDRESS ACRONYM REGISTER NAME
0x480C A000 SPINLOCK_REV Revision
0x480C A010h SPINLOCK_SYSCFG System Configuration
0x480C A014h SPINLOCK_SYSSTAT System Status
0x480C A800 + (0x4*i) SPINLOCK_LOCK_REG_i Lock
(1) i = 0 to 63

3.5 Power, Reset and Clock Management (PRCM) Module

The PRCM module is the centralized management module for the power, reset, and clock control signals of the device. It interfaces with all the components on the device for power, clock, and reset management through power-control signals. It integrates enhanced features to allow the device to adapt energy consumption dynamically, according to changing application and performance requirements. The innovative hardware architecture allows a substantial reduction in leakage current.

The PRCM module is composed of two main entities:

  • Power reset manager (PRM): Handles the power, reset, wake-up management, and system clock source control (oscillator)
  • Clock manager (CM): Handles the clock generation, distribution, and management.

Table 3-6 lists the physical addresses of the PRM and CM modules. Table 3-7 through Table 3-18 provide register mapping summaries of the PRM and CM registers.

For more details on the PRCM, see Section 8 of this data sheet, Power, Reset, Clocking and Interrupts, and the PRCM chapter of the AM389x Sitara ARM Processors Technical Reference Manual (literature number SPRUGX7).

Table 3-6 PRCM Register Address Summary

ADDRESS OFFSET MODULE NAME SIZE SEE
0x0000 PRM_DEVICE 256 Bytes Table 3-7
0x0100 CM_DEVICE 256 Bytes Table 3-8
0x0300 CM_DPLL 256 Bytes Table 3-10
0x0400 CM_ACTIVE 256 Bytes Table 3-11
0x0500 CM_DEFAULT 256 Bytes Table 3-12
0x0900 CM_SGX 256 Bytes Table 3-13
0x0A00 PRM_ACTIVE 256 Bytes Table 3-14
0x0B00 PRM_DEFAULT 256 Bytes Table 3-15
0x0F00 PRM_SGX 256 Bytes Table 3-16
0x1400 CM_ALWON 1 KBytes Table 3-17
0x1800 PRM_ALWON 1 KBytes Table 3-18

Table 3-7 PRM_DEVICE Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 00A0 PRM_RSTCTRL Global software cold and warm reset control
0x4818 00A4 PRM_RSTTIME Reset duration control
0x4818 00A8 PRM_RSTST Global reset sources log

Table 3-8 CM_DEVICE Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 0100 CM_CLKOUT_CTRL SYS_CCCLKOUT output control

Table 3-9 OCP_SOCKET_PRM Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 0200 REVISION_PRM PRCM IP revision code

Table 3-10 CM_DPLL Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 0300 CM_SYSCLK1_CLKSEL SYSCLK1 clock divider value select
0x4818 0304 CM_SYSCLK2_CLKSEL SYSCLK2 clock divider value select
0x4818 0308 CM_SYSCLK3_CLKSEL SYSCLK3 clock divider value select
0x4818 030C CM_SYSCLK4_CLKSEL SYSCLK4 clock divider value select
0x4818 0310 CM_SYSCLK5_CLKSEL SYSCLK5 clock divider value select
0x4818 0314 CM_SYSCLK6_CLKSEL SYSCLK6 clock divider value select
0x4818 0318 CM_SYSCLK7_CLKSEL SYSCLK7 clock divider value select
0x4818 0324 CM_SYSCLK10_CLKSEL SYSCLK10 clock divider value select
0x4818 032C CM_SYSCLK11_CLKSEL SYSCLK11 clock divider value select
0x4818 0334 CM_SYSCLK13_CLKSEL SYSCLK13 clock divider value select
0x4818 0338 CM_SYSCLK15_CLKSEL SYSCLK15 clock divider value select
0x4818 0340 CM_VPB3_CLKSEL Video PLL B3 clock divider value select
0x4818 0344 CM_VPC1_CLKSEL Video PLL C1 clock divider value select
0x4818 0348 CM_VPD1_CLKSEL Video PLL D1 clock divider value select
0x4818 034C CM_SYSCLK19_CLKSEL SYSCLK19 clock divider value select
0x4818 0350 CM_SYSCLK20_CLKSEL SYSCLK20 clock divider value select
0x4818 0354 CM_SYSCLK21_CLKSEL SYSCLK21 clock divider value select
0x4818 0358 CM_SYSCLK22_CLKSEL SYSCLK22 clock divider value select
0x4818 035C CM_APA_CLKSEL Audio PLL A clock divider value select
0x4818 0370 CM_SYSCLK14_CLKSEL SYSCLK14 clock mux select line
0x4818 0374 CM_SYSCLK16_CLKSEL SYSCLK16 clock mux select line
0x4818 0378 CM_SYSCLK18_CLKSEL SYSCLK18 clock mux select line
0x4818 037C CM_AUDIOCLK_MCASP0_CLKSEL McASP0 audio clock mux select line
0x4818 0380 CM_AUDIOCLK_MCASP1_CLKSEL McASP1 audio clock mux select line
0x4818 0384 CM_AUDIOCLK_MCASP2_CLKSEL McASP2 audio clock mux select line
0x4818 0388 CM_AUDIOCLK_MCBSP_CLKSEL McBSP audio clock mux select line
0x4818 0390 CM_TIMER1_CLKSEL Timer1 clock mux select line
0x4818 0394 CM_TIMER2_CLKSEL Timer2 clock mux select line
0x4818 0398 CM_TIMER3_CLKSEL Timer3 clock mux select line
0x4818 039C CM_TIMER4_CLKSEL Timer4 clock mux select line
0x4818 03A0 CM_TIMER5_CLKSEL Timer5 clock mux select line
0x4818 03A4 CM_TIMER6_CLKSEL Timer6 clock mux select line
0x4818 03A8 CM_TIMER7_CLKSEL Timer7 clock mux select line
0x4818 03B0 CM_SYSCLK23_CLKSEL SYSCLK23 clock divider value select
0x4818 03B4 CM_SYSCLK24_CLKSEL SYSCLK24 clock divider value select

Table 3-11 CM_ACTIVE Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 0404 CM_HDDSS_CLKSTCTRL HDVPSS clock domain power state transition
0x4818 0408 CM_HDMI_CLKSTCTRL HDMI clock domain power state transition
0x4818 0424 CM_ACTIVE_HDDSS_CLKCTRL HDVPSS clock management control
0x4818 0428 CM_ACTIVE_HDMI_CLKCTRL HDMI clock management control

Table 3-12 CM_DEFAULT Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 0504 CM_DEFAULT_L3_MED_CLKSTCTRL L3 clock domain power state transition
0x4818 0508 CM_DEFAULT_L3_FAST_CLKSTCTRL L3 clock domain power state transition
0x4818 0510 CM_DEFAULT_PCI_CLKSTCTRL PCI clock domain power state transition
0x4818 0514 CM_DEFAULT_L3_SLOW_CLKSTCTRL L3 clock domain power state transition
0x4818 0520 CM_DEFAULT_EMIF_0_CLKCTRL EMIF0 clock management control
0x4818 0524 CM_DEFAULT_EMIF_1_CLKCTRL EMIF1 clock management control
0x4818 0528 CM_DEFAULT_DMM_CLKCTRL DMM clock management control
0x4818 052C CM_DEFAULT_FW_CLKCTRL EMIF FW clock management control
0x4818 0558 CM_DEFAULT_USB_CLKCTRL USB clock management control
0x4818 0560 CM_DEFAULT_SATA_CLKCTRL SATA clock management control
0x4818 0578 CM_DEFAULT_PCI_CLKCTRL PCI clock management control

Table 3-13 CM_SGX Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 0900 CM_SGX_CLKSTCTRL SGX530 clock domain power state transition
0x4818 0920 CM_SGX_SGX_CLKCTRL SGX530 clock management control

Table 3-14 PRM_ACTIVE Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 0A00 PM_ACTIVE_PWRSTCTRL Active power state control
0x4818 0A04 PM_ACTIVE_PWRSTST Active power domain state status
0x4818 0A10 RM_ACTIVE_RSTCTRL Active domain reset control release
0x4818 0A14 RM_ACTIVE_RSTST Active domain reset source log

Table 3-15 PRM_DEFAULT Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 0B00 PM_DEFAULT_PWRSTCTRL Default power state
0x4818 0B04 PM_DEFAULT_PWRSTST Default power domain state 0 status
0x4818 0B10 RM_DEFAULT_RSTCTRL Default subsystem reset control release
0x4818 0B14 RM_DEFAULT_RSTST Default domain reset source log

Table 3-16 PRM_SGX Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 0F00 PM_SGX_PWRSTCTRL SGX530 power state control
0x4818 0F04 RM_SGX_RSTCTRL SGX530 domain reset control release
0x4818 0F10 PM_SGX_PWRSTST SGX530 power domain state status
0x4818 0F14 RM_SGX_RSTST SGX530 domain reset source log

Table 3-17 CM_ALWON Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 1400 CM_ALWON_L3_SLOW_CLKSTCTRL L3 clock domain power state transition
0x4818 1404 CM_ETHERNET_CLKSTCTRL EMAC clock domain power state transition
0x4818 1408 CM_ALWON_L3_MED_CLKSTCTRL L3 clock domain power state transition
0x4818 1414 CM_ALWON_OCMC_0_CLKSTCTRL OCMC 0 clock domain power state transition
0x4818 1418 CM_ALWON_OCMC_1_CLKSTCTRL OCMC 1 clock domain power state transition
0x4818 141C CM_ALWON_MPU_CLKSTCTRL Processor clock domain power state transition
0x4818 1420 CM_ALWON_SYSCLK4_CLKSTCTRL SYSCLK4 clock domain power state transition
0x4818 1424 CM_ALWON_SYSCLK5_CLKSTCTRL SYSCLK5 clock domain power state transition
0x4818 1428 CM_ALWON_SYSCLK6_CLKSTCTRL SYSCLK6 clock domain power state transition
0x4818 142C CM_ALWON_RTC_CLKSTCTRL RTC clock domain power state transition
0x4818 1430 CM_ALWON_L3_FAST_CLKSTCTRL L3 clock domain power state transition
0x4818 1540 CM_ALWON_MCASP0_CLKCTRL McASP 0 clock management control
0x4818 1544 CM_ALWON_MCASP1_CLKCTRL McASP 1 clock management control
0x4818 1548 CM_ALWON_MCASP2_CLKCTRL McASP 2 clock management control
0x4818 154C CM_ALWON_MCBSP_CLKCTRL McBSP clock management control
0x4818 1550 CM_ALWON_UART_0_CLKCTRL UART 0 clock management control
0x4818 1554 CM_ALWON_UART_1_CLKCTRL UART 1 clock management control
0x4818 1558 CM_ALWON_UART_2_CLKCTRL UART 2 clock management control
0x4818 155C CM_ALWON_GPIO_0_CLKCTRL GPIO 0 clock management control
0x4818 1560 CM_ALWON_GPIO_1_CLKCTRL GPIO 1 clock management control
0x4818 1564 CM_ALWON_I2C_0_CLKCTRL I2C 0 clock management control
0x4818 1568 CM_ALWON_I2C_1_CLKCTRL I2C 1 clock management control
0x4818 1570 CM_ALWON_TIMER_1_CLKCTRL Timer1 clock management control
0x4818 1574 CM_ALWON_TIMER_2_CLKCTRL Timer2 clock management control
0x4818 1578 CM_ALWON_TIMER_3_CLKCTRL Timer3 clock management control
0x4818 157C CM_ALWON_TIMER_4_CLKCTRL Timer4 clock management control
0x4818 1580 CM_ALWON_TIMER_5_CLKCTRL Timer5 clock management control
0x4818 1584 CM_ALWON_TIMER_6_CLKCTRL Timer6 clock management control
0x4818 1588 CM_ALWON_TIMER_7_CLKCTRL Timer7 clock management control
0x4818 158C CM_ALWON_WDTIMER_CLKCTRL WDTIMER clock management control
0x4818 1590 CM_ALWON_SPI_CLKCTRL SPI clock management control
0x4818 1594 CM_ALWON_MAILBOX_CLKCTRL MAILBOX clock management control
0x4818 1598 CM_ALWON_SPINBOX_CLKCTRL SPINBOX clock management control
0x4818 15B0 CM_ALWON_SDIO_CLKCTRL SDIO clock management control
0x4818 15B4 CM_ALWON_OCMC_0_CLKCTRL OCMC 0 clock management control
0x4818 15B8 CM_ALWON_OCMC_1_CLKCTRL OCMC 1 clock management control
0x4818 15C4 CM_ALWON_CONTROL_CLKCTRL Control clock management control
0x4818 15D0 CM_ALWON_GPMC_CLKCTRL GPMC clock management control
0x4818 15D4 CM_ALWON_ETHERNET_0_CLKCTRL Ethernet 0 clock management control
0x4818 15D8 CM_ALWON_ETHERNET_1_CLKCTRL Ethernet 1 clock management control
0x4818 15DC CM_ALWON_MPU_CLKCTRL Processor clock management control
0x4818 15E0 CM_ALWON_DEBUGSS_CLKCTRL Debug clock management control
0x4818 15E4 CM_ALWON_L3_CLKCTRL L3 clock management control
0x4818 15E8 CM_ALWON_L4HS_CLKCTRL L4 high-speed clock management control
0x4818 15EC CM_ALWON_L4LS_CLKCTRL L4 standard-speed clock management control
0x4818 15F0 CM_ALWON_RTC_CLKCTRL RTC clock management control
0x4818 15F4 CM_ALWON_TPCC_CLKCTRL TPCC clock management control
0x4818 15F8 CM_ALWON_TPTC0_CLKCTRL TPTC0 clock management control
0x4818 15FC CM_ALWON_TPTC1_CLKCTRL TPTC1 clock management control
0x4818 1600 CM_ALWON_TPTC2_CLKCTRL TPTC2 clock management control
0x4818 1604 CM_ALWON_TPTC3_CLKCTRL TPTC3 clock management control
0x4818 1608 CM_ALWON_SR_0_CLKCTRL SmartReflex 0 clock management control
0x4818 160C CM_ALWON_SR_1_CLKCTRL SmartReflex 1 clock management control
0x4818 1628 CM_ALWON_CUST_EFUSE_CLKCTRL Customer e-Fuse clock management control

Table 3-18 PRM_ALWON Register Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4818 1810 RM_ALWON_RSTCTRL ALWAYS ON domain resets control
0x4818 1814 RM_ALWON_RSTST ALWAYS ON reset sources

3.6 SGX530 (AM3894 only)

The SGX530 is a vector and 3D graphics accelerator for vector and 3-dimensional (3D) graphics applications. The SGX530 graphics accelerator efficiently processes a number of various multimedia data types concurrently:

  • Pixel data
  • Vertex data
  • Video data.

This is achieved using a multi-threaded architecture using two levels of scheduling and data partitioning enabling zero overhead task switching.

The SGX530 has the following major features:

  • Vector graphics and 3D graphics.
  • Tile-based architecture.
  • Universal Scalable Shader Engine (USSE) - multi-threaded engine incorporating pixel and vertex shader functionality.
  • Advanced shader feature set - in excess of Microsoft VS3.0, PS3.0, and OpenGL 2.0.
  • Industry standard API support - OpenGL ES 1.1 and 2.0, OpenVG v1.1.
  • Fine-grained task switching, load balancing, and power management.
  • Advanced geometry direct memory access (DMA) driven operation for minimum CPU interaction.
  • Programmable high-quality image anti-aliasing.
  • PowerVR® SGX core MMU for address translation from the core virtual address to the external physical address (up to 4GB address range).
  • Fully-virtualized memory addressing for OS operation in a unified memory architecture.
  • Advanced and standard 2D operations [for example, vector graphics, block level transfers (BLTs), raster operations (ROPs)].

3.7 Memory Map Summary

The device has multiple on-chip memories associated with its processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters.

The device system memory mapping is broken into four 1-GB quadrants for target address spaces allocation. The four quadrants are labeled Q0, Q1, Q2 and Q3 for a total of 4-GB 32-bit address space. (HDVPSS includes a thirty-third address bit for an additional 4GB of address range; this is for virtual addressing and not physical memory addressing.) Inside each quadrant, system targets are mapped on 4-MB boundary (except EDMA targets which are decreased to 1-MB regions).

3.7.1 L3 Memory Map

The L3 high-performance interconnect is based on a Network-on-Chip (NoC) interconnect infrastructure. The NoC uses an internal packet-based protocol for forward (read command, write command with data payload) and backward (read response with data payload, write response) transactions. All exposed interfaces of this NoC interconnect, both for targets and initiators, comply with the OCPIP2.2 reference standard.

Table 3-19 shows the general device level-3 (L3) memory map. The table represents the physical addresses used by the L3 infrastructure. Some processors within the device (such as Cortex™-A8 ARM) may re-map these targets to different virtual addresses through an internal or external MMU. Processors without MMUs and other bus masters use these physical addresses to access L3 regions. Note that not all masters have access to all L3 regions, but only those with defined connectivity, as shown in Table 7-1. For a list of the specific peripherals attached to each of the Level-4 (L4) peripheral ports see Section 7.2. The L3 interconnect returns an address-hole error if any initiator attempts to access a target to which it has no connection.

Table 3-19 L3 Memory Map

QUAD BLOCK NAME START ADDRESS (HEX) END ADDRESS (HEX) SIZE DESCRIPTION
Q0 GPMC 0x0100 0000 0x1FFF FFFF 496MB GPMC(1)
Q0 PCIe Gen2 0x2000 0000 0x2FFF FFFF 256MB PCIe Gen2 Targets
Q0 Reserved 0x3000 0000 0x3FFF FFFF 256MB Reserved
Q1 Reserved 0x4000 0000 0x402F FFFF 3MB Reserved
Q1 L3 OCMC0 0x4030 0000 0x4033 FFFF 256KB OCMC SRAM
Q1 Reserved 0x4034 0000 0x403F FFFF 768KB Reserved (OCMC RAM0)
Q1 L3 OCMC1 0x4040 0000 0x4043 FFFF 256KB OCMC SRAM
Q1 Reserved 0x4044 0000 0x404F FFFF 768KB Reserved (OCMC RAM1)
Q1 Reserved 0x4050 0000 0x407F FFFF 3MB Reserved
Q1 Reserved 0x4080 0000 0x4083 FFFF 256KB Reserved
Q1 Reserved 0x4084 0000 0x40DF FFFF 5888KB Reserved
Q1 Reserved 0x40E0 0000 0x40E0 7FFF 32KB Reserved
Q1 Reserved 0x40E0 8000 0x40EF FFFF 992KB Reserved
Q1 Reserved 0x40F0 0000 0x40F0 7FFF 32KB Reserved
Q1 Reserved 0x40F0 8000 0x40FF FFFF 992KB Reserved
Q1 Reserved 0x4100 0000 0x41FF FFFF 16MB Reserved
Q1 Reserved 0x4200 0000 0x43FF FFFF 32MB Reserved
Q1 L3 CFG Regs 0x4400 0000 0x44BF FFFF 12MB L3 configuration registers
Q1 Reserved 0x44C0 0000 0x45FF FFFF 20MB Reserved
Q1 McASP0 0x4600 0000 0x463F FFFF 4MB McASP0 DAT Port Access(2)
Q1 McASP1 0x4640 0000 0x467F FFFF 4MB McASP1 DAT Port Access(2)
Q1 McASP2 0x4680 0000 0x46BF FFFF 4MB McASP2 DAT Port Access(2)
Q1 HDMI 1.3 Tx 0x46C0 0000 0x46FF FFFF 4MB HDMI 1.3 Tx
Q1 McBSP 0x4700 0000 0x473F FFFF 4MB McBSP
Q1 USB2.0 0x4740 0000 0x477F FFFF 4MB USB2.0 Registers and CPPI
Q1 Reserved 0x4780 0000 0x47BF FFFF 4MB Reserved
Q1 Reserved 0x47C0 0000 0x47FF FFFF 4MB Reserved
Q1 L4 Standard domain 0x4800 0000 0x48FF FFFF 16MB Standard Peripheral domain
(see notes-list-normal)
Q1 EDMA TPCC 0x4900 0000 0x490F FFFF 1MB EDMA TPCC Registers
Q1 Reserved 0x4910 0000 0x497F FFFF 7MB Reserved
Q1 EDMA TPTC0 0x4980 0000 0x498F FFFF 1MB EDMA TPTC0 Registers
Q1 EDMA TPTC1 0x4990 0000 0x499F FFFF 1MB EDMA TPTC1 Registers
Q1 EDMA TPTC2 0x49A0 0000 0x49AF FFFF 1MB EDMA TPTC2 Registers
Q1 EDMA TPTC3 0x49B0 0000 0x49BF FFFF 1MB EDMA TPTC3 Registers
Q1 Reserved 0x49C0 0000 0x49FF FFFF 4MB Reserved
Q1 L4 High-Speed Domain 0x4A00 0000 0x4AFF FFFF 16MB High-Speed Peripheral domain
(see notes-list-normal)
Q1 Instrumentation 0x4B00 0000 0x4BFF FFFF 16MB EMU Subsystem region
Q1 DDR EMIF0 registers(3) 0x4C00 0000 0x4CFF FFFF 16MB Configuration registers
Q1 DDR EMIF1 registers(3) 0x4D00 0000 0x4DFF FFFF 16MB Configuration registers
Q1 DDR DMM Registers(3) 0x4E00 0000 0x4FFF FFFF 32MB Configuration registers
Q1 GPMC Registers 0x5000 0000 0x50FF FFFF 16MB Configuration registers
Q1 PCIe Gen2 Registers 0x5100 0000 0x51FF FFFF 16MB Configuration registers
Q1 Reserved 0x5200 0000 0x54FF FFFF 48MB Reserved
Q1 Reserved 0x5500 0000 0x55FF FFFF 16MB Reserved
Q1 SGX530
AM3894 only)		 0x5600 0000 0x56FF FFFF 16MB SGX530 Slave Port
Q1 Reserved
(AM3892 only)		 0x5600 0000 0x56FF FFFF 16MB Reserved
Q1 Reserved 0x5700 0000 0x57FF FFFF 16MB Reserved
Q1 Reserved 0x5800 0000 0x5BFF FFFF 64MB Reserved
Q1 Reserved 0x5C00 0000 0x5DFF FFFF 32MB Reserved
Q1 Reserved 0x5E00 0000 0x5FFF FFFF 32MB Reserved
Q1 Tiler 0x6000 0000 0x7FFF FFFF 512MB Virtual Tiled Address Space
Q2 DDR EMIF0 and EMIF1 SDRAM(4) 0x8000 0000 0xBFFF FFFF 1GB DDR
Q3 DDR EMIF0 and EMIF1 SDRAM(4) 0xC000 0000 0xFFFF FFFF 1GB DDR
Q4-7 DDR DMM 0x1 0000 0000 0x1 FFFF FFFF 4GB DDR DMM Tiler Extended address map – Virtual Views (HDVPSS only)
  1. The first section of GPMC memory (0x0 - 0x00FF_FFFF) is reserved for BOOTROM. Accessible memory starts at location 0x0100_0000.
  2. For more information about McASP registers accessed through the DAT port, see notes-list-normal.
  3. These accesses occur through the DDR DMM Tiler Ports. The DMM will split address ranges internally to address DDR EMIF and DDR DMM control registers.
  4. DDR EMIF0 and DDR EMIF1 addresses may be contiguous or bank interleaved depending on configuration of the DDR DMM; for more details, see the DDR DMM documentation.

3.7.2 L4 Memory Map

3.7.2.1 L4 Standard Peripheral

The L4 standard peripheral bus accesses standard peripherals and IP configuration registers. The memory map is shown in Table 3-20.

Table 3-20 L4 Standard Peripheral Memory Map

DEVICE NAME START ADDRESS (HEX) END ADDRESS (HEX) SIZE DESCRIPTION
L4 Standard Configuration 0x4800 0000 0x4800 07FF 2KB Address and Protection (AP)
0x4800 0800 0x4800 0FFF 2KB Link Agent (LA)
0x4800 1000 0x4800 13FF 1KB Initiator Port (IP0)
0x4800 1400 0x4800 17FF 1KB Initiator Port (IP1)
0x4800 1800 0x4800 1FFF 2KB Reserved (IP2 – IP3)
Reserved 0x4800 2000 0x4800 7FFF 24KB Reserved
e-Fuse Controller 0x4800 8000 0x4800 8FFF 4KB Peripheral Registers
0x4800 9000 0x4800 9FFF 4KB Support Registers
Reserved 0x4800 A000 0x4800 FFFF 24KB Reserved
Reserved 0x4801 2000 0x4801 FFFF 56KB Reserved
UART0 0x4802 0000 0x4802 0FFF 4KB Peripheral Registers
0x4802 1000 0x4802 1FFF 4KB Support Registers
UART1 0x4802 2000 0x4802 2FFF 4KB Peripheral Registers
0x4802 3000 0x4802 3FFF 4KB Support Registers
UART2 0x4802 4000 0x4802 4FFF 4KB Peripheral Registers
0x4802 5000 0x4802 5FFF 4KB Support Registers
Reserved 0x4802 6000 0x4802 7FFF 8KB Reserved
I2C0 0x4802 8000 0x4802 8FFF 4KB Peripheral Registers
0x4802 9000 0x4802 9FFF 4KB Support Registers
I2C1 0x4802 A000 0x4802 AFFF 4KB Peripheral Registers
0x4802 B000 0x4802 BFFF 4KB Support Registers
Reserved 0x4802 C000 0x4802 DFFF 8KB Reserved
TIMER1 0x4802 E000 0x4802 EFFF 4KB Peripheral Registers
0x4802 F000 0x4802 FFFF 4KB Support Registers
SPIOCP 0x4803 0000 0x4803 0FFF 4KB Peripheral Registers
0x4803 1000 0x4803 1FFF 4KB Support Registers
GPIO0 0x4803 2000 0x4803 2FFF 4KB Peripheral Registers
0x4803 3000 0x4803 3FFF 4KB Support Registers
Reserved 0x4803 4000 0x4803 7FFF 16KB Reserved
McASP0 CFG 0x4803 8000 0x4803 9FFF 8KB Peripheral Registers
0x4803 A000 0x4803 AFFF 4KB Support Registers
Reserved 0x4803 B000 0x4803 BFFF 4KB Reserved
McASP1 CFG 0x4803 C000 0x4803 DFFF 8KB Peripheral Registers
0x4803 E000 0x4803 EFFF 4KB Support Registers
Reserved 0x4803 F000 0x4803 FFFF 4KB Reserved
TIMER2 0x4804 0000 0x4804 0FFF 4KB Peripheral Registers
0x4804 1000 0x4804 1FFF 4KB Support Registers
TIMER3 0x4804 2000 0x4804 2FFF 4KB Peripheral Registers
0x4804 3000 0x4804 3FFF 4KB Support Registers
TIMER4 0x4804 4000 0x4804 4FFF 4KB Peripheral Registers
0x4804 5000 0x4804 5FFF 4KB Support Registers
TIMER5 0x4804 6000 0x4804 6FFF 4KB Peripheral Registers
0x4804 7000 0x4804 7FFF 4KB Support Registers
TIMER6 0x4804 8000 0x4804 8FFF 4KB Peripheral Registers
0x4804 9000 0x4804 9FFF 4KB Support Registers
TIMER7 0x4804 A000 0x4804 AFFF 4KB Peripheral Registers
0x4804 B000 0x4804 BFFF 4KB Support Registers
GPIO1 0x4804 C000 0x4804 CFFF 4KB Peripheral Registers
0x4804 D000 0x4804 DFFF 4KB Support Registers
Reserved 0x4804 E000 0x4804 FFFF 8KB Reserved
McASP2 CFG 0x4805 0000 0x4805 1FFF 8KB Peripheral Registers
0x4805 2000 0x4805 2FFF 4KB Support Registers
Reserved 0x4805 3000 0x4805 FFFF 52KB Reserved
SD and SDIO 0x4806 0000 0x4806 FFFF 64KB Registers
0x4807 0000 0x4807 0FFF 4KB Support Registers
Reserved 0x4807 1000 0x4807 FFFF 60KB Reserved
ELM 0x4808 0000 0x4808 FFFF 64KB Error Location Module
0x4809 0000 0x4809 0FFF 4KB Support Registers
Reserved 0x4809 1000 0x480B FFFF 188KB Reserved
RTC 0x480C 0000 0x480C 0FFF 4KB Peripheral Registers
0x480C 1000 0x480C 1FFF 4KB Support Registers
WDT1 0x480C 2000 0x480C 2FFF 4KB Peripheral Registers
0x480C 3000 0x480C 3FFF 4KB Support Registers
Reserved 0x480C 4000 0x480C 7FFF 16KB Reserved
Mailbox 0x480C 8000 0x480C 8FFF 4KB Peripheral Registers
0x480C 9000 0x480C 9FFF 4KB Support Registers
Spinlock 0x480C A000 0x480C AFFF 4KB Peripheral Registers
0x480C B000 0x480C BFFF 4KB Support Registers
Reserved 0x480C C000 0x480F FFFF 208KB Reserved
HDVPSS 0x4810 0000 0x4811 FFFF 128KB Peripheral Registers
0x4812 0000 0x4812 0FFF 4KB Support Registers
Reserved 0x4812 1000 0x4812 1FFF 4KB Reserved
HDMI 1.3 Tx 0x4812 2000 0x4812 2FFF 4KB Peripheral Registers
0x4812 3000 0x4812 3FFF 4KB Support Registers
Reserved 0x4812 4000 0x4813 FFFF 112KB Reserved
Control Module 0x4814 0000 0x4815 FFFF 128KB Peripheral Registers
0x4816 0000 0x4816 0FFF 4KB Support Registers
Reserved 0x4816 1000 0x4817 FFFF 124KB Reserved
PRCM 0x4818 0000 0x4818 2FFF 12KB Peripheral Registers
0x4818 3000 0x4818 3FFF 4KB Support Registers
Reserved 0x4818 4000 0x4818 7FFF 16KB Reserved
SmartReflex0 0x4818 8000 0x4818 8FFF 4KB Peripheral Registers
0x4818 9000 0x4818 9FFF 4KB Support Registers
SmartReflex1 0x4818 A000 0x4818 AFFF 4KB Peripheral Registers
0x4818 B000 0x4818 BFFF 4KB Support Registers
OCP Watchpoint 0x4818 C000 0x4818 CFFF 4KB Peripheral Registers
0x4818 D000 0x4818 DFFF 4KB Support Registers
Reserved 0x4818 E000 0x4818 EFFF 4KB Reserved
0x4818 F000 0x4818 FFFF 4KB Reserved
Reserved 0x4819 0000 0x4819 0FFF 4KB Reserved
0x4819 1000 0x4819 1FFF 4KB Reserved
Reserved 0x4819 2000 0x4819 2FFF 4KB Reserved
0x4819 3000 0x4819 3FFF 4KB Reserved
Reserved 0x4819 4000 0x4819 4FFF 4KB Reserved
0x4819 5000 0x4819 5FFF 4KB Reserved
Reserved 0x4819 6000 0x4819 6FFF 4KB Reserved
0x4819 7000 0x4819 7FFF 4KB Reserved
DDR0 Phy Ctrl Regs 0x4819 8000 0x4819 8FFF 4KB Peripheral Registers
0x4819 9000 0x4819 9FFF 4KB Support Registers
DDR1 Phy Ctrl Regs 0x4819 A000 0x4819 AFFF 4KB Peripheral Registers
0x4819 B000 0x4819 BFFF 4KB Support Registers
Reserved 0x4819 C000 0x481F FFFF 400KB Reserved
Interrupt controller(1) 0x4820 0000 0x4820 0FFF 4KB Cortex™-A8 Accessible Only
Reserved(1) 0x4820 1000 0x4823 FFFF 252KB Cortex™-A8 Accessible Only
MPUSS config register(1) 0x4824 0000 0x4824 0FFF 4KB Cortex™-A8 Accessible Only
Reserved(1) 0x4824 1000 0x4827 FFFF 252KB Cortex™-A8 Accessible Only
Reserved(1) 0x4828 1000 0x482F FFFF 508KB Cortex™-A8 Accessible Only
Reserved 0x4830 0000 0x48FF FFFF 13MB Reserved
(1) These regions are decoded internally by the Cortex™-A8 Subsystem and are not physically part of the L4 standard. They are included here only for reference when considering the Cortex™-A8 memory map. For masters other than the Cortex™-A8, these regions are reserved.

3.7.2.2 L4 High-Speed Peripheral

The L4 high-speed peripheral bus accesses the IP configuration registers of high-speed peripherals in L3. The memory map is shown in Table 3-21.

Table 3-21 L4 High-Speed Peripheral Memory Map

DEVICE NAME START ADDRESS (HEX) END ADDRESS (HEX) SIZE DESCRIPTION
L4 High Speed configuration 0x4A00 0000 0x4A00 07FF 2KB Address and Protection (AP)
0x4A00 0800 0x4A00 0FFF 2KB Link Agent (LA)
0x4A00 1000 0x4A00 13FF 1KB Initiator Port (IP0)
0x4A00 1400 0x4A00 17FF 1KB Initiator Port (IP1)
0x4A00 1800 0x4A00 1FFF 2KB Reserved (IP2 – IP3)
Reserved 0x4A00 2000 0x4A07 FFFF 504KB Reserved
Reserved 0x4A08 0000 0x4A0A 0FFF 132KB Reserved
Reserved 0x4A0A 1000 0x4A0F FFFF 380KB Reserved
EMAC0 0x4A10 0000 0x4A10 3FFF 16KB Peripheral Registers
0x4A10 4000 0x4A10 4FFF 4KB Support Registers
Reserved 0x4A10 5000 0x4A11 FFFF 108KB Reserved
EMAC1 0x4A12 0000 0x4A12 3FFF 16KB Peripheral Registers
0x4A12 4000 0x4A12 4FFF 4KB Support Registers
Reserved 0x4A12 5000 0x4A13 FFFF 108KB Reserved
SATA 0x4A14 0000 0x4A14 FFFF 64KB Peripheral Registers
0x4A15 0000 0x4A15 0FFF 4KB Support Registers
Reserved 0x4A15 1000 0x4A17 FFFF 188KB Reserved
Reserved 0x4A18 0000 0x4A19 FFFF 128KB Reserved
0x4A1A 0000 0x4A1A 0FFF 4KB Reserved
Reserved 0x4A1A 1000 0x4AFF FFFF 14716KB Reserved

3.7.3 TILER Extended Addressing Map

The Tiling and Isometric Lightweight Engines for Rotation (TILER) ports are mainly used for optimized 2-D block accesses. The TILER also supports rotation of the image buffer at 0º, 90º, 180º, and 270º, with vertical and horizontal mirroring.

The TILER includes an additional 4-GB addressing range to access the frame buffer in these rotated and mirrored views. This range requires a thirty-third bit of address and is only accessible to peripherals that require access to the multiple views. On the device, this is limited to the HD Video Processing Subsystem (HDVPSS). (Other peripherals, based on ConnID, may access any one single view through the 512-MB TILER window region located in the base 4-GB range.)

The HDVPSS may use the virtual address space of 4GB (0x1:0000:0000 – 0x1:FFFF:FFFF) since various VPDMA clients of the HDVPSS may need to simultaneously access multiple 2-D images with different orientations of the image buffers.

The top 4-GB address space is divided into eight sections of 512MB each. These eight sections correspond to the eight different orientations as shown in Table 3-22.

Table 3-22 TILER Extended Address Memory Map

BLOCK NAME START ADDRESS (HEX) END ADDRESS (HEX) SIZE DESCRIPTION
Tiler View 0 0x1 0000 0000 0x1 1FFF FFFF 512MB Natural 0° View
Tiler View 1 0x1 2000 0000 0x1 3FFF FFFF 512MB 0° with Vertical Mirror View
Tiler View 2 0x1 4000 0000 0x1 5FFF FFFF 512MB 0° with Horizontal Mirror View
Tiler View 3 0x1 6000 0000 0x1 7FFF FFFF 512MB 180° View
Tiler View 4 0x1 8000 0000 0x1 9FFF FFFF 512MB 90° with Vertical Mirror View
Tiler View 5 0x1 A000 0000 0x1 BFFF FFFF 512MB 270° View
Tiler View 6 0x1 C000 0000 0x1 DFFF FFFF 512MB 90° View
Tiler View 7 0x1 E000 0000 0x1 FFFF FFFF 512MB 90° with Horizontal Mirror View

3.7.4 Cortex™-A8 Memory Map

The Cortex™-A8 includes an memory management unit (MMU) to translate virtual addresses to physical addresses which are then decoded within the Host ARM Subsystem. The subsystem includes its own ROM and RAM, as well as configuration registers for its interrupt controller. These addresses are hard-coded within the subsystem. In addition, the upper 2GB of address space is routed to a special port (Master 0) intended for low-latency access to DDR memory. All other physical addresses are routed to the L3 port (Master 1) where they are decoded by the device infrastructure. The Cortex™-A8 memory map is shown in Table 3-23.

Table 3-23 Cortex™-A8 Memory Map

REGION NAME START ADDRESS (HEX) END ADDRESS (HEX) SIZE DESCRIPTION
Boot Space 0x0000 0000 0x000F FFFF 1MB Boot Space
L3 Target Space 0x0000 0000 0x1FFF FFFF 512MB GPMC
0x2000 0000 0x2FFF FFFF 256MB PCIe Gen2 Targets
0x3000 0000 0x3FFF FFFF 256MB Reserved
ROM internal(1) 0x4000 0000 0x4001 FFFF 128KB Reserved
0x4002 0000 0x4002 BFFF 48KB Public
0x4002 C000 0x400F FFFF 848KB Reserved
Reserved(1) 0x4010 0000 0x401F FFFF 1MB Reserved
Reserved(1) 0x4020 0000 0x402E FFFF 960KB Reserved
Reserved 0x402F 0000 0x402F FFFF 64KB Reserved
L3 Target Space 0x4030 0000 0x4033 FFFF 256KB OCMC SRAM
0x4034 0000 0x403F FFFF 768KB Reserved
0x4040 0000 0x4043 FFFF 256KB OCMC SRAM
0x4044 0000 0x404F FFFF 768KB Reserved
0x4050 0000 0x407F FFFF 3MB Reserved
0x4080 0000 0x4083 FFFF 256KB Reserved
0x4084 0000 0x40DF FFFF 5888KB Reserved
0x40E0 0000 0x40E0 7FFF 32KB Reserved
0x40E0 8000 0x40EF FFFF 992KB Reserved
0x40F0 0000 0x40F0 7FFF 32KB Reserved
0x40F0 8000 0x40FF FFFF 992KB Reserved
0x4100 0000 0x41FF FFFF 16MB Reserved
0x4200 0000 0x43FF FFFF 32MB Reserved
0x4400 0000 0x44BF FFFF 12MB L3 configuration registers
0x44C0 0000 0x45FF FFFF 20MB Reserved
0x4600 0000 0x463F FFFF 4MB McASP0
0x4640 0000 0x467F FFFF 4MB McASP1
0x4680 0000 0x46BF FFFF 4MB McASP2
0x46C0 0000 0x46FF FFFF 4MB HDMI 1.3 Tx
0x4700 0000 0x473F FFFF 4MB McBSP
0x4740 0000 0x477F FFFF 4MB USB2.0 Registers and CPPI
0x4780 0000 0x47BF FFFF 4MB Reserved
0x47C0 0000 0x47FF FFFF 4MB Reserved
0x4800 0000 0x481F FFFF 2MB Standard Peripheral domain (see Table 3-20)
ARM Subsystem INTC(1) 0x4820 0000 0x4820 0FFF 4KB Cortex™-A8 Interrupt Controller
Reserved(1) 0x4820 1000 0x4823 FFFF 252KB Reserved
Reserved(1) 0x4824 1000 0x4827 FFFF 252KB Reserved
L3 Target Space 0x4830 0000 0x48FF FFFF 13MB Standard Peripheral domain (see Table 3-20)
0x4900 0000 0x490F FFFF 1MB EDMA TPCC Registers
0x4910 0000 0x497F FFFF 7MB Reserved
0x4980 0000 0x498F FFFF 1MB EDMA TPTC0 Registers
0x4990 0000 0x499F FFFF 1MB EDMA TPTC1 Registers
0x49A0 0000 0x49AF FFFF 1MB EDMA TPTC2 Registers
0x49B0 0000 0x49BF FFFF 1MB EDMA TPTC3 Registers
0x49C0 0000 0x49FF FFFF 4MB Reserved
0x4A00 0000 0x4AFF FFFF 16MB High Speed Peripheral domain (see Table 3-21)
0x4B00 0000 0x4BFF FFFF 16MB EMU Subsystem region
0x4C00 0000 0x4CFF FFFF 16MB DDR EMIF0(2) Configuration registers
0x4D00 0000 0x4DFF FFFF 16MB DDR EMIF1(2) Configuration registers
0x4E00 0000 0x4FFF FFFF 32MB DDR DMM(2) Configuration registers
0x5000 0000 0x50FF FFFF 16MB GPMC Configuration registers
0x5100 0000 0x51FF FFFF 16MB PCIE Configuration registers
0x5200 0000 0x55FF FFFF 64MB Reserved
0x5600 0000 0x56FF FFFF 16MB SGX530 Slave Port
(AM3894 only)
0x5600 0000 0x56FF FFFF 16MB Reserved
(AM3892 only)
0x5700 0000 0x57FF FFFF 16MB Reserved
0x5800 0000 0x5FFF FFFF 128MB Reserved
0x6000 0000 0x7FFF FFFF 512MB TILER Window
DDR EMIF0 and EMIF1 SDRAM(3)(4) 0x8000 0000 0xBFFF FFFF 1GB DDR
DDR EMIF0 and EMIF1 SDRAM(3)(4) 0xC000 0000 0xFFFF FFFF 1GB DDR
  1. These addresses are decoded within the Cortex™-A8 subsystem.
  2. These accesses occur through the DDR DMM TILER ports. The DDR DMM splits address ranges internally to address DDR EMIF and DDR DMM control registers based on DDR DMM tie-offs.
  3. These addresses are routed to the Master 0 port for direct connection to the DDR DMM ELLA port.
  4. DDR EMIF0 and DDR EMIF1 addresses may be contiguous or bank interleaved, depending on configuration of the DDR DMM.