JAJSEZ3E June 2014 – January 2019 AM4372 , AM4376 , AM4377 , AM4378 , AM4379
PRODUCTION DATA.
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TI only supports board designs using DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory interface are shown in Table 5-48 and Figure 5-48.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | tc(DDR_CK)
tc(DDR_CKn) |
Cycle time, DDR_CK and DDR_CKn | 2.5 | 3.3(1) | ns |