JAJSEZ3E June 2014 – January 2019 AM4372 , AM4376 , AM4377 , AM4378 , AM4379
PRODUCTION DATA.
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SIGNAL NAME [1] | DESCRIPTION [2] | TYPE [3] | ZDN [4] |
---|---|---|---|
mdio_clk | MDIO Clk | O | B17 |
mdio_data | MDIO Data | IO | A17 |
SIGNAL NAME [1] | DESCRIPTION [2] | TYPE [3] | ZDN [4] |
---|---|---|---|
gmii1_col | MII Colision | I | D16 |
gmii1_crs | MII Carrier Sense | I | B14 |
gmii1_rxclk | MII Receive Clock | I | D13 |
gmii1_rxdv | MII Receive Data Valid | I | A15 |
gmii1_rxer | MII Receive Data Error | I | B13 |
gmii1_txclk | MII Transmit Clock | I | D14 |
gmii1_txen | MII Transmit Enable | O | A13 |
gmii1_rxd0 | MII Receive Data bit 0 | I | F17 |
gmii1_rxd1 | MII Receive Data bit 1 | I | B16 |
gmii1_rxd2 | MII Receive Data bit 2 | I | E16 |
gmii1_rxd3 | MII Receive Data bit 3 | I | C14 |
gmii1_txd0 | MII Transmit Data bit 0 | O | B15 |
gmii1_txd1 | MII Transmit Data bit 1 | O | A14 |
gmii1_txd2 | MII Transmit Data bit 2 | O | C13 |
gmii1_txd3 | MII Transmit Data bit 3 | O | C16 |
SIGNAL NAME [1] | DESCRIPTION [2] | TYPE [3] | ZDN [4] |
---|---|---|---|
gmii2_col | MII Colision | I | A3 |
gmii2_crs | MII Carrier Sense | I | A2, B12, F10 |
gmii2_rxclk | MII Receive Clock | I | F6 |
gmii2_rxdv | MII Receive Data Valid | I | C5 |
gmii2_rxer | MII Receive Data Error | I | B3 |
gmii2_txclk | MII Transmit Clock | I | E8 |
gmii2_txen | MII Transmit Enable | O | C3 |
gmii2_rxd0 | MII Receive Data bit 0 | I | D8 |
gmii2_rxd1 | MII Receive Data bit 1 | I | G8 |
gmii2_rxd2 | MII Receive Data bit 2 | I | B4 |
gmii2_rxd3 | MII Receive Data bit 3 | I | F7 |
gmii2_txd0 | MII Transmit Data bit 0 | O | E7 |
gmii2_txd1 | MII Transmit Data bit 1 | O | D7 |
gmii2_txd2 | MII Transmit Data bit 2 | O | A4 |
gmii2_txd3 | MII Transmit Data bit 3 | O | C6 |
SIGNAL NAME [1] | DESCRIPTION [2] | TYPE [3] | ZDN [4] |
---|---|---|---|
rgmii1_rclk | RGMII Receive Clock | I | D13 |
rgmii1_rctl | RGMII Receive Control | I | A15 |
rgmii1_tclk | RGMII Transmit Clock | O | D14 |
rgmii1_tctl | RGMII Transmit Control | O | A13 |
rgmii1_rd0 | RGMII Receive Data bit 0 | I | F17 |
rgmii1_rd1 | RGMII Receive Data bit 1 | I | B16 |
rgmii1_rd2 | RGMII Receive Data bit 2 | I | E16 |
rgmii1_rd3 | RGMII Receive Data bit 3 | I | C14 |
rgmii1_td0 | RGMII Transmit Data bit 0 | O | B15 |
rgmii1_td1 | RGMII Transmit Data bit 1 | O | A14 |
rgmii1_td2 | RGMII Transmit Data bit 2 | O | C13 |
rgmii1_td3 | RGMII Transmit Data bit 3 | O | C16 |
SIGNAL NAME [1] | DESCRIPTION [2] | TYPE [3] | ZDN [4] |
---|---|---|---|
rgmii2_rclk | RGMII Receive Clock | I | F6 |
rgmii2_rctl | RGMII Receive Control | I | C5 |
rgmii2_tclk | RGMII Transmit Clock | O | E8 |
rgmii2_tctl | RGMII Transmit Control | O | C3 |
rgmii2_rd0 | RGMII Receive Data bit 0 | I | D8 |
rgmii2_rd1 | RGMII Receive Data bit 1 | I | G8 |
rgmii2_rd2 | RGMII Receive Data bit 2 | I | B4 |
rgmii2_rd3 | RGMII Receive Data bit 3 | I | F7 |
rgmii2_td0 | RGMII Transmit Data bit 0 | O | E7 |
rgmii2_td1 | RGMII Transmit Data bit 1 | O | D7 |
rgmii2_td2 | RGMII Transmit Data bit 2 | O | A4 |
rgmii2_td3 | RGMII Transmit Data bit 3 | O | C6 |
SIGNAL NAME [1] | DESCRIPTION [2] | TYPE [3] | ZDN [4] |
---|---|---|---|
rmii1_crs_dv | RMII Carrier Sense / Data Valid | I | B14 |
rmii1_refclk | RMII Reference Clock | IO | A16 |
rmii1_rxer | RMII Receive Data Error | I | B13 |
rmii1_txen | RMII Transmit Enable | O | A13 |
rmii1_rxd0 | RMII Receive Data bit 0 | I | F17 |
rmii1_rxd1 | RMII Receive Data bit 1 | I | B16 |
rmii1_txd0 | RMII Transmit Data bit 0 | O | B15 |
rmii1_txd1 | RMII Transmit Data bit 1 | O | A14 |
SIGNAL NAME [1] | DESCRIPTION [2] | TYPE [3] | ZDN [4] |
---|---|---|---|
rmii2_crs_dv | RMII Carrier Sense / Data Valid | I | A2, B12, B4, F10 |
rmii2_refclk | RMII Reference Clock | IO | D16 |
rmii2_rxer | RMII Receive Data Error | I | B3 |
rmii2_txen | RMII Transmit Enable | O | C3 |
rmii2_rxd0 | RMII Receive Data bit 0 | I | D8 |
rmii2_rxd1 | RMII Receive Data bit 1 | I | G8 |
rmii2_txd0 | RMII Transmit Data bit 0 | O | E7 |
rmii2_txd1 | RMII Transmit Data bit 1 | O | D7 |