JAJSEZ3E June 2014 – January 2019 AM4372 , AM4376 , AM4377 , AM4378 , AM4379
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The Remote Frame Buffer Interface (RFBI) module can provide also the necessary control signals and data to interface to the Pico DLP driver of the Pico DLP panel. Table 5-77 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-98).
TIMING CONDITION PARAMETER | VALUE | UNIT | ||
---|---|---|---|---|
MIN | MAX | |||
Output Condition | ||||
CLOAD | Output load capacitance | 5 | pF |
To use Pico DLP application, RFBI register must be configured as shown in Table 5-78:
DESCRIPTION | REGISTER AND BIT FIELD(1) | BIT | VALUES |
---|---|---|---|
Selection parallel mode | RFBI_CONFIGi and ParallelMode | [1:0] | 0b11: 16-bit parallel output interface selected |
Time Granularity (multiplies signal timing latencies by 2). | RFBI_CONFIGi andTimeGranularity | [4] | 0b0: x2 latency disable |
CS signal assertion time from Start Access Time | RFBI_ONOFF_TIMEi and CSOnTime | [3:0] | 0b0000 |
CS signal deassertion time from Start Access Time | RFBI_ONOFF_TIMEi and CSOffTime | [9:4] | 0b000100: 4 cycles |
WE signal assertion time from Start Access Time | RFBI_ONOFF_TIMEi and WEOnTime | [13:10] | 0b0000 |
WE signal deassertion time from Start Access Time | RFBI_ONOFF_TIMEi and WEOffTime | [19:14] | 0b000010: 2 cycles |
RE signal assertion time from Start Access Time | RFBI_ONOFF_TIMEi and REOnTime | [23:20] | 0b0000 |
RE signal deassertion time from Start Access Time | RFBI_ONOFF_TIMEi and REOffTime | [29:24] | 0b0000 |
Write cycle time | RFBI_CYCLE_TIMEi and WECycleTime | [5:0] | 0b000100: 4 cycles |
Read cycle time | RFBI_CYCLE_TIMEi and ReCycleTime | [11:6] | 0b000000 |
CS pulse width | RFBI_CYCLE_TIMEi and CSPulseWidth | [17:12] | 0b000000 |
Read to Write CS pulse width enable | RFBI_CYCLE_TIMEi and RWEnable | [18] | 0b0 |
Read to Read CS pulse width enable | RFBI_CYCLE_TIMEi and RREnable | [19] | 0b0 |
Write to Write CS pulse width enable | RFBI_CYCLE_TIMEi and WWEnable | [20] | 0b0 |
Write to Read CS pulse width enable | RFBI_CYCLE_TIMEi and WREnable | [21] | 0b0 |
From Start Access Time to CLK rising edge used for the first data capture | RFBI_CYCLE_TIMEi and AccessTime | [27:22] | 0b000000 |
PARAMETER | OPP100 | OPP50 | UNIT | |||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
tw(wrH) | Pulse duration, output write enable rfbi_wr high | A(4) | A(4) | ns | ||
tw(wrL) | Pulse duration, output write enable rfbi_wr low | B(5) | B(5) | ns | ||
td(a0-wrL) | Delay time, output command/data control rfbi_a0 transition to output write enable rfbi_wr low | C(6) | C(6) | ns | ||
td(wrH-a0) | Delay time, output write enable rfbi_wr high to output command/data control rfbi_a0 transition | D(7) | D(7) | ns | ||
td(csx-wrL) | Delay time, output chip select rfbi_csx(8) low to output write enable rfbi_wr low | E(9) | E(9) | ns | ||
td(wrH-csxH) | Delay time, output write enable rfbi_wr high to output chip select rfbi_csx(8) high | F(10) | F(10) | ns | ||
td(dataV) | Output data rfbi_da[15:0](11) valid | G(12) | G(12) | ns | ||
td(Skew) | Skew between output write enable falling rfbi_wr and output data rfbi_da[15:0](11) high or low | 15.5 | 15.5 | ns | ||
td(a0H-rdL) | Delay time, output command/data control rfbi_a0 high to output read enable rfbi_rd low | H(13) | H(13) | ns | ||
td(rdlH-a0) | Delay time, output read enable rfbi_rd high to output command/data control rfbi_a0 transition | I(14) | I(14) | ns | ||
tw(rdH) | Pulse duration, output read enable rfbi_rd high | J(15) | J(15) | ns | ||
tw(rdL) | Pulse duration, output read enable rfbi_rd low | K(16) | K(16) | ns | ||
td(rdL-csxL) | Delay time, output read enable rfbi_rd low to output chip select rfbi_csx(8) low | L(17) | L(17) | ns | ||
td(rdL-csxH) | Delay time, output read enable rfbi_rd low to output chip select rfbi_csx(8) high | M(18) | M(18) | ns | ||
CsOnTime | CS signal assertion time from Start Access Time – RFBI_ONOFF_TIMEi Register | 0(19) | ns | |||
CsOffTime | CS signal deassertion time from Start Access Time – RFBI_ONOFF_TIMEi Register | 40(19) | ns | |||
WeOnTime | WE signal assertion time from Start Access Time – RFBI_ONOFF_TIMEi Register | 0(19) | ns | |||
WeOffTime | WE signal deassertion time from Start Access Time – RFBI_ONOFF_TIMEi Register | 20(19) | ns | |||
ReOnTime | RE signal assertion time from Start Access Time – RFBI_ONOFF_TIMEi Register | - | ns | |||
ReOffTime | RE signal deassertion time from Start Access Time – RFBI_ONOFF_TIMEi Register | - | ns | |||
WeCycleTime | Write cycle time – RFBI_CYCLE_TIMEi Register | 40(19) | ns | |||
ReCycleTime | Read cycle time – RFBI_CYCLE_TIMEi Register | - | ns | |||
CsPulseWidth | CS pulse width – RFBI_CYCLE_TIMEi Register | 0(19) | ns |