JAJSE20F August   2016  – November 2019 AM5706 , AM5708

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 Emulation and Debug Subsystem
      25. 4.3.25 System and Miscellaneous
        1. 4.3.25.1 Sysboot
        2. 4.3.25.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.25.3 System Direct Memory Access (SDMA)
        4. 4.3.25.4 Interrupt Controllers (INTC)
      26. 4.3.26 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
        1. Table 5-4 Voltage Domains Operating Performance Points
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-7  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-8  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-9  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-11 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-12 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-13 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-14 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-15 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-57 Timing Requirements for I2C Input Timings
          2. Table 5-58 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-59 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-64 Timing Requirements for UART
          2. Table 5-65 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-72 Timing Requirements for McASP1
          2. Table 5-73 Timing Requirements for McASP2
          3. Table 5-74 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-89 Timing Requirements for DCANx Receive
          2. Table 5-90 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-91 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-92 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-93 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-94 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-99  Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-100 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-101 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-102 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-106 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-107 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-108 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-109 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 eMMC/SD/SDIO
          1. 5.10.6.20.1 MMC1—SD Card Interface
            1. 5.10.6.20.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.20.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.20.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.20.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.20.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.20.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.20.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.20.2 MMC2 — eMMC
            1. 5.10.6.20.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.20.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.20.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.20.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-134 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.20.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.20.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.20.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.20.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.20.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.20.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        21. 5.10.6.21 GPIO
        22. 5.10.6.22 PRU-ICSS
          1. 5.10.6.22.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.22.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-156 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-157 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.22.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-158 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.22.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-159 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-160 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.22.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-161 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-162 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-163 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.22.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.22.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-164 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-165 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-166 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-167 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-168 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.22.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.22.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-169 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-170 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-171 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.22.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-173 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-174 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-175 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.22.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-176 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-177 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.22.5 PRU-ICSS IOSETs
          6. 5.10.6.22.6 PRU-ICSS Manual Functional Mapping
        23. 5.10.6.23 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-194 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-195 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-196 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-197 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  PRU-ICSS
    6. 6.6  Memory Subsystem
      1. 6.6.1 EMIF
      2. 6.6.2 GPMC
      3. 6.6.3 ELM
      4. 6.6.4 OCMC
    7. 6.7  Interprocessor Communication
      1. 6.7.1 MailBox
      2. 6.7.2 Spinlock
    8. 6.8  Interrupt Controller
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  VIP
      2. 6.10.2  DSS
      3. 6.10.3  Timers
        1. 6.10.3.1 General-Purpose Timers
        2. 6.10.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.10.3.3 Watchdog Timer
      4. 6.10.4  I2C
      5. 6.10.5  UART
        1. 6.10.5.1 UART Features
        2. 6.10.5.2 IrDA Features
        3. 6.10.5.3 CIR Features
      6. 6.10.6  McSPI
      7. 6.10.7  QSPI
      8. 6.10.8  McASP
      9. 6.10.9  USB
      10. 6.10.10 PCIe
      11. 6.10.11 DCAN
      12. 6.10.12 GMAC_SW
      13. 6.10.13 eMMC/SD/SDIO
      14. 6.10.14 GPIO
      15. 6.10.15 ePWM
      16. 6.10.16 eCAP
      17. 6.10.17 eQEP
    11. 6.11 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Power Supply Mapping
    2. 7.2 DDR3 Board Design and Layout Guidelines
      1. 7.2.1 DDR3 General Board Layout Guidelines
      2. 7.2.2 DDR3 Board Design and Layout Guidelines
        1. 7.2.2.1  Board Designs
        2. 7.2.2.2  DDR3 EMIF
        3. 7.2.2.3  DDR3 Device Combinations
        4. 7.2.2.4  DDR3 Interface Schematic
          1. 7.2.2.4.1 32-Bit DDR3 Interface
          2. 7.2.2.4.2 16-Bit DDR3 Interface
        5. 7.2.2.5  Compatible JEDEC DDR3 Devices
        6. 7.2.2.6  PCB Stackup
        7. 7.2.2.7  Placement
        8. 7.2.2.8  DDR3 Keepout Region
        9. 7.2.2.9  Bulk Bypass Capacitors
        10. 7.2.2.10 High-Speed Bypass Capacitors
          1. 7.2.2.10.1 Return Current Bypass Capacitors
        11. 7.2.2.11 Net Classes
        12. 7.2.2.12 DDR3 Signal Termination
        13. 7.2.2.13 VREF_DDR Routing
        14. 7.2.2.14 VTT
        15. 7.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.2.2.15.1 Four DDR3 Devices
            1. 7.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.2.2.15.2 Two DDR3 Devices
            1. 7.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.2.2.15.3 One DDR3 Device
            1. 7.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.2.2.16 Data Topologies and Routing Definition
          1. 7.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.2.2.17 Routing Specification
          1. 7.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.2.2.17.2 DQS and DQ Routing Specification
    3. 7.3 High Speed Differential Signal Routing Guidance
    4. 7.4 Power Distribution Network Implementation Guidance
    5. 7.5 Thermal Solution Guidance
    6. 7.6 Single-Ended Interfaces
      1. 7.6.1 General Routing Guidelines
      2. 7.6.2 QSPI Board Design and Layout Guidelines
    7. 7.7 LJCB_REFN/P Connections
    8. 7.8 Clock Routing Guidelines
      1. 7.8.1 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • CBD|538
サーマルパッド・メカニカル・データ
発注情報

4.3.6 GPMC

NOTE

For more information, see the Memory Subsystem / General-Purpose Memory Controller section of the Device TRM.

Table 4-7 GPMC Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
gpmc_ad0 GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1 in A/D multiplexed mode IO F1
gpmc_ad1 GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2 in A/D multiplexed mode IO E2
gpmc_ad2 GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3 in A/D multiplexed mode IO E1
gpmc_ad3 GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4 in A/D multiplexed mode IO C1
gpmc_ad4 GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5 in A/D multiplexed mode IO D1
gpmc_ad5 GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6 in A/D multiplexed mode IO D2
gpmc_ad6 GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7 in A/D multiplexed mode IO B1
gpmc_ad7 GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8 in A/D multiplexed mode IO B2
gpmc_ad8 GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9 in A/D multiplexed mode IO C2
gpmc_ad9 GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10 in A/D multiplexed mode IO D3
gpmc_ad10 GPMC Data 10 in A/D nonmultiplexed mode and additionally Address 11 in A/D multiplexed mode IO A2
gpmc_ad11 GPMC Data 11 in A/D nonmultiplexed mode and additionally Address 12 in A/D multiplexed mode IO B3
gpmc_ad12 GPMC Data 12 in A/D nonmultiplexed mode and additionally Address 13 in A/D multiplexed mode IO C3
gpmc_ad13 GPMC Data 13 in A/D nonmultiplexed mode and additionally Address 14 in A/D multiplexed mode IO C4
gpmc_ad14 GPMC Data 14 in A/D nonmultiplexed mode and additionally Address 15 in A/D multiplexed mode IO A3
gpmc_ad15 GPMC Data 15 in A/D nonmultiplexed mode and additionally Address 16 in A/D multiplexed mode IO B4
gpmc_a0 GPMC Address 0. Only used to effectively address 8-bit data nonmultiplexed memories O G1, M1
gpmc_a1 GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D multiplexed mode O G3, M2
gpmc_a2 GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D multiplexed mode O H5, L2
gpmc_a3 GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D multiplexed mode O H6, L1
gpmc_a4 GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D multiplexed mode O K3
gpmc_a5 GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D multiplexed mode O K2
gpmc_a6 GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D multiplexed mode O J1
gpmc_a7 GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D multiplexed mode O K1
gpmc_a8 GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D multiplexed mode O K4
gpmc_a9 GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D multiplexed mode O H1
gpmc_a10 GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D multiplexed mode O J2
gpmc_a11 GPMC address 11 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O L3
gpmc_a12 GPMC address 12 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O G1
gpmc_a13 GPMC address 13 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O A4, H3, G4
gpmc_a14 GPMC address 14 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O E7, H4, G3
gpmc_a15 GPMC address 15 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O D6, K6, F6
gpmc_a16 GPMC address 16 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O C5, K5, M1
gpmc_a17 GPMC address 17 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O B5, G2, D8
gpmc_a18 GPMC address 18 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O D7, F2, C7
gpmc_a19 GPMC address 19 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O A4(3), C6, H5
gpmc_a20 GPMC address 20 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O A5, E7(3), L4
gpmc_a21 GPMC address 21 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O B6, D6(3), H2
gpmc_a22 GPMC address 22 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O A6, C5(3), H6
gpmc_a23 GPMC address 23 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O B5, H5, C10, G4
gpmc_a24 GPMC address 24 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O D7(3), D10, G3
gpmc_a25 GPMC address 25 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O C6(3), F6, E10
gpmc_a26 GPMC address 26 in A/D nonmultiplexed mode and unused in A/D multiplexed mode O A5(3), M1, B10
gpmc_a27 GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D multiplexed mode O B6(3), D8, C7, E8
gpmc_cs0 GPMC Chip Select 0 (active low) O F3
gpmc_cs1 GPMC Chip Select 1 (active low) O A6
gpmc_cs2 GPMC Chip Select 2 (active low) O G4
gpmc_cs3 GPMC Chip Select 3 (active low) O G3
gpmc_cs4 GPMC Chip Select 4 (active low) O H2
gpmc_cs5 GPMC Chip Select 5 (active low) O H6
gpmc_cs6 GPMC Chip Select 6 (active low) O H5
gpmc_cs7 GPMC Chip Select 7 (active low) O L4
gpmc_clk(1)(2) GPMC Clock output IO L4
gpmc_advn_ale GPMC address valid active low or address latch enable O H5
gpmc_oen_ren GPMC output enable active low or read enable O G5
gpmc_wen GPMC write enable active low O G6
gpmc_ben0 GPMC lower-byte enable active low O H2
gpmc_ben1 GPMC upper-byte enable active low O H6
gpmc_wait0 GPMC external indication of wait 0 I F6
gpmc_wait1 GPMC external indication of wait 1 I H5, L4

  1. This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
  2. The gpio6_16.clkout1 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the associated timing. See Table 5-49, GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and Table 5-51GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate for timing information.
  3. The internal pull resistors for balls A4, E7, D6, C5, D7, C6, A5, B6 are permanently disabled when sysboot15 is set to 0 as described in the section Sysboot Configuration of the Device TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 1. If gpmc boot mode is used with SYSBOOT15=0 (not recommended) then external pull-downs should be implemented to keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot.