JAJSC85G March   2016  – May 2018 AM5716 , AM5718

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2 改訂履歴
  3. 3 Device Comparison
    1. 3.1 Device Comparison Table
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.4.5  External Memory Interface (EMIF)
      6. 4.4.6  General-Purpose Memory Controller (GPMC)
      7. 4.4.7  Timers
      8. 4.4.8  Inter-Integrated Circuit Interface (I2C)
      9. 4.4.9  HDQ / 1-Wire Interface (HDQ1W)
      10. 4.4.10 Universal Asynchronous Receiver Transmitter (UART)
      11. 4.4.11 Multichannel Serial Peripheral Interface (McSPI)
      12. 4.4.12 Quad Serial Peripheral Interface (QSPI)
      13. 4.4.13 Multichannel Audio Serial Port (McASP)
      14. 4.4.14 Universal Serial Bus (USB)
      15. 4.4.15 SATA
      16. 4.4.16 Peripheral Component Interconnect Express (PCIe)
      17. 4.4.17 Controller Area Network Interface (DCAN)
      18. 4.4.18 Ethernet Interface (GMAC_SW)
      19. 4.4.19 Media Local Bus (MLB) Interface
      20. 4.4.20 eMMC/SD/SDIO
      21. 4.4.21 General-Purpose Interface (GPIO)
      22. 4.4.22 Keyboard controller (KBD)
      23. 4.4.23 Pulse Width Modulation (PWM) Interface
      24. 4.4.24 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      25. 4.4.25 Test Interfaces
      26. 4.4.26 System and Miscellaneous
        1. 4.4.26.1 Sysboot
        2. 4.4.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.26.3 Real-Time Clock (RTC) Interface
        4. 4.4.26.4 System Direct Memory Access (SDMA)
        5. 4.4.26.5 Interrupt Controllers (INTC)
        6. 4.4.26.6 Observability
      27. 4.4.27 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hours (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  LVCMOS CSI2 DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 SERDES DC Electrical Characteristics
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
        3. 6.1.4.3 RC On-die Oscillator Clock
    2. 6.2 DPLLs, DLLs Specifications
      1. 6.2.1 DPLL Characteristics
      2. 6.2.2 DLL Characteristics
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem - Video Output Ports
    8. 7.8  Display Subsystem - High-Definition Multimedia Interface (HDMI)
    9. 7.9  Camera Serial Interface 2 CAL bridge (CSI2)
      1. 7.9.1 CSI-2 MIPI D-PHY
    10. 7.10 External Memory Interface (EMIF)
    11. 7.11 General-Purpose Memory Controller (GPMC)
      1. 7.11.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.11.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.11.3 GPMC/NAND Flash Interface Asynchronous Timing
    12. 7.12 Timers
    13. 7.13 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-33 Timing Requirements for I2C Input Timings
      2. Table 7-34 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-35 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    14. 7.14 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.14.1 HDQ / 1-Wire - HDQ Mode
      2. 7.14.2 HDQ/1-Wire-1-Wire Mode
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-40 Timing Requirements for UART
      2. Table 7-41 Switching Characteristics Over Recommended Operating Conditions for UART
    16. 7.16 Multichannel Serial Peripheral Interface (McSPI)
    17. 7.17 Quad Serial Peripheral Interface (QSPI)
    18. 7.18 Multichannel Audio Serial Port (McASP)
      1. Table 7-48 Timing Requirements for McASP1
      2. Table 7-49 Timing Requirements for McASP2
      3. Table 7-50 Timing Requirements for McASP3/4/5/6/7/8
    19. 7.19 Universal Serial Bus (USB)
      1. 7.19.1 USB1 DRD PHY
      2. 7.19.2 USB2 PHY
    20. 7.20 Serial Advanced Technology Attachment (SATA)
    21. 7.21 Peripheral Component Interconnect Express (PCIe)
    22. 7.22 Controller Area Network Interface (DCAN)
      1. Table 7-65 Timing Requirements for DCANx Receive
      2. Table 7-66 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    23. 7.23 Ethernet Interface (GMAC_SW)
      1. 7.23.1 GMAC MII Timings
        1. Table 7-67 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-68 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-69 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-70 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.23.2 GMAC MDIO Interface Timings
      3. 7.23.3 GMAC RMII Timings
        1. Table 7-75 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-76 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-77 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-78 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.23.4 GMAC RGMII Timings
        1. Table 7-82 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-83 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-84 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-85 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    24. 7.24 eMMC/SD/SDIO
      1. 7.24.1 MMC1-SD Card Interface
        1. 7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3 SDR12, 4-bit data, half-cycle
        4. 7.24.1.4 SDR25, 4-bit data, half-cycle
        5. 7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7 UHS-I DDR50, 4-bit data
      2. 7.24.2 MMC2 - eMMC
        1. 7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3 High-speed HS200 JEDS84, 8-bit data, half cycle
        4. 7.24.2.4 High-speed JC64 DDR, 8-bit data
          1. Table 7-110 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
      3. 7.24.3 MMC3 and MMC4-SDIO/SD
        1. 7.24.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2 MMC3 and MMC4, SD High Speed
        3. 7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25 General-Purpose Interface (GPIO)
    26. 7.26 PRU-ICSS Interfaces
      1. 7.26.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. 7.26.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
          1. Table 7-132 PRU-ICSS PRU Timing Requirements - Direct Input Mode
          2. Table 7-133 PRU-ICSS PRU Switching Requirements - Direct Output Mode
        2. 7.26.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
          1. Table 7-134 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
        3. 7.26.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
          1. Table 7-135 PRU-ICSS PRU Timing Requirements - Shift In Mode
          2. Table 7-136 PRU-ICSS PRU Switching Requirements - Shift Out Mode
        4. 7.26.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
          1. Table 7-137 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
          2. Table 7-138 PRU-ICSS PRU Timing Requirements - EnDAT Mode
          3. Table 7-139 PRU-ICSS PRU Switching Requirements - EnDAT Mode
      2. 7.26.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. 7.26.2.1 PRU-ICSS ECAT Electrical Data and Timing
          1. Table 7-140 PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
          2. Table 7-141 PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
          3. Table 7-142 PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
          4. Table 7-143 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
          5. Table 7-144 PRU-ICSS ECAT Switching Requirements - Digital IOs
      3. 7.26.3 PRU-ICSS MII_RT and Switch
        1. 7.26.3.1 PRU-ICSS MDIO Electrical Data and Timing
          1. Table 7-145 PRU-ICSS MDIO Timing Requirements - MDIO_DATA
          2. Table 7-146 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
          3. Table 7-147 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
        2. 7.26.3.2 PRU-ICSS MII_RT Electrical Data and Timing
          1. Table 7-148 PRU-ICSS MII_RT Timing Requirements - MII[x]_RXCLK
          2. Table 7-149 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
          3. Table 7-150 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
          4. Table 7-151 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
      4. 7.26.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
        1. Table 7-152 Timing Requirements for PRU-ICSS UART Receive
        2. Table 7-153 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      5. 7.26.5 PRU-ICSS Manual Functional Mapping
    27. 7.27 System and Miscellaneous interfaces
    28. 7.28 Test Interfaces
      1. 7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1 JTAG Electrical Data/Timing
          1. Table 7-173 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-174 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-175 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-176 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.28.2 Trace Port Interface Unit (TPIU)
        1. 7.28.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Power Supply Mapping
    2. 8.2 DDR3 Board Design and Layout Guidelines
      1. 8.2.1 DDR3 General Board Layout Guidelines
      2. 8.2.2 DDR3 Board Design and Layout Guidelines
        1. 8.2.2.1  Board Designs
        2. 8.2.2.2  DDR3 EMIF
        3. 8.2.2.3  DDR3 Device Combinations
        4. 8.2.2.4  DDR3 Interface Schematic
          1. 8.2.2.4.1 32-Bit DDR3 Interface
          2. 8.2.2.4.2 16-Bit DDR3 Interface
        5. 8.2.2.5  Compatible JEDEC DDR3 Devices
        6. 8.2.2.6  PCB Stackup
        7. 8.2.2.7  Placement
        8. 8.2.2.8  DDR3 Keepout Region
        9. 8.2.2.9  Bulk Bypass Capacitors
        10. 8.2.2.10 High-Speed Bypass Capacitors
          1. 8.2.2.10.1 Return Current Bypass Capacitors
        11. 8.2.2.11 Net Classes
        12. 8.2.2.12 DDR3 Signal Termination
        13. 8.2.2.13 VREF_DDR Routing
        14. 8.2.2.14 VTT
        15. 8.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.2.2.15.1 Four DDR3 Devices
            1. 8.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.2.2.15.2 Two DDR3 Devices
            1. 8.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.2.2.15.3 One DDR3 Device
            1. 8.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.2.2.16 Data Topologies and Routing Definition
          1. 8.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.2.2.17 Routing Specification
          1. 8.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.2.2.17.2 DQS and DQ Routing Specification
    3. 8.3 High Speed Differential Signal Routing Guidance
    4. 8.4 Power Distribution Network Implementation Guidance
    5. 8.5 Thermal Solution Guidance
    6. 8.6 Single-Ended Interfaces
      1. 8.6.1 General Routing Guidelines
      2. 8.6.2 QSPI Board Design and Layout Guidelines
    7. 8.7 LJCB_REFN/P Connections
    8. 8.8 Clock Routing Guidelines
      1. 8.8.1 32-kHz Oscillator Routing
      2. 8.8.2 Oscillator Ground Connection
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Related Links
    6. 9.6 Community Resources
    7. 9.7 Trademarks
    8. 9.8 静電気放電に関する注意事項
    9. 9.9 Glossary
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.2 Ball Characteristics

Table 4-2 describes the terminal characteristics and the signals multiplexed on each ball. The following list describes the table column headers:

  1. BALL NUMBER: Ball number(s) on the bottom side associated with each signal on the bottom.
  2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
  3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).

    4. NOTE

    Table 4-2 does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.4, Signal Descriptions.

    NOTE

    In the Driver off mode, the buffer is configured in high-impedance.

    NOTE

    In some cases Table 4-2 may present more than one signal name per muxmode for the same ball. First signal in the list is the dominant function as selected via CTRL_CORE_PAD_* register.

    All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

  4. PN:This column shows if the functionality is applicable for AM5716 device. Note that the Ball Characteristics table presents a functionality of AM5718. If the cell is empty it means that the signal is available in all devices.
    - Yes - Functionality is presented in AM5716
    - No - Functionality is not presented in AM5716
    An empty box means Yes.
  5. MUXMODE: Multiplexing mode number:
    1. MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily the default muxmode.

      2. NOTE

      The default mode is the mode at the release of the reset; also see the RESET REL. MUXMODE column.
    2. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
    3. An empty box means Not Applicable.
  6. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • IO = Input or Output
    • D = Open drain
    • DS = Differential Signaling
    • A = Analog
    • PWR = Power
    • GND = Ground
    • CAP = LDO Capacitor
  7. BALL RESET STATE: The state of the terminal at power-on reset:
    • drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
    • drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable
  8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
    • drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
    • drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated).
    • drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable

    9. NOTE

    For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see the Power, Reset, and Clock Management / PRCM Reset Management Functional Description section of the Device TRM.
  9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
    An empty box means Not Applicable.
  10. IO VOLTAGE VALUE: This column describes the IO voltage value (VDDS supply).
    An empty box means Not Applicable.
  11. POWER: The voltage supply that powers the terminal IO buffers.
    An empty box means Not Applicable.

    12. NOTE

    VOUT1, VOUT2 and VOUT3 are only supported at 1.8V and not at 3.3V. This must be considered in the pin mux programming and VDDSHVx supply connections.
  12. HYS: Indicates if the input buffer is with hysteresis:
    • Yes: With hysteresis
    • No: Without hysteresis
    • An empty box: Not Applicable

    13. NOTE

    For more information, see the hysteresis values in Section 5.7, Electrical Characteristics.
  13. BUFFER TYPE: Drive strength of the associated output buffer.
    An empty box means Not Applicable.

    14. NOTE

    For programmable buffer strength:

    • The default value is given in Table 4-2.
    • A note describes all possible values according to the selected muxmode.
  14. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
    • PU: Internal pullup
    • PD: Internal pulldown
    • PU/PD: Internal pullup and pulldown
    • PUx/PDy: Programmable internal pullup and pulldown
    • PDy: Programmable internal pulldown
    • An empty box means No pull

  15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers.
    • 0: Logic 0 driven on the peripheral's input signal port.
    • 1: Logic 1 driven on the peripheral's input signal port.
    • blank: Pin state driven on the peripheral's input signal port.

    16. NOTE

    Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (Hi-Z mode is not an input signal).

    NOTE

    When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

    NOTE

    Some of the EMIF1 signals have an additional state change at the release of porz. The state that the signals change to at the release of porz is as follows:

    drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_ba[2:0], ddr1_a[15:0].

    OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0].

    NOTE

    Dual rank support is not available on this device, but signal names are retained for consistency with the AM57xx family of devices.

Table 4-2 Ball Characteristics(1)

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET REL. MUXMODE [9] I/O VOLTAGE VALUE [10] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14]
K9 cap_vbbldo_dsp cap_vbbldo_dsp CAP
Y14 cap_vbbldo_gpu cap_vbbldo_gpu CAP
J10 cap_vbbldo_iva cap_vbbldo_iva CAP
J16 cap_vbbldo_mpu cap_vbbldo_mpu CAP
T20 cap_vddram_core1 cap_vddram_core1 CAP
L9 cap_vddram_core3 cap_vddram_core3 CAP
J19 cap_vddram_core4 cap_vddram_core4 CAP
J9 cap_vddram_dsp cap_vddram_dsp CAP
Y13 cap_vddram_gpu cap_vddram_gpu CAP
K16 cap_vddram_iva cap_vddram_iva CAP
K19 cap_vddram_mpu cap_vddram_mpu CAP
AE1 csi2_0_dx0 csi2_0_dx0 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AF1 csi2_0_dx1 csi2_0_dx1 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AF2 csi2_0_dx2 csi2_0_dx2 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AH4 csi2_0_dx3 csi2_0_dx3 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AH3 csi2_0_dx4 csi2_0_dx4 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AD2 csi2_0_dy0 csi2_0_dy0 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AE2 csi2_0_dy1 csi2_0_dy1 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AF3 csi2_0_dy2 csi2_0_dy2 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AG4 csi2_0_dy3 csi2_0_dy3 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AG3 csi2_0_dy4 csi2_0_dy4 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AG5 csi2_1_dx0 csi2_1_dx0 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AG6 csi2_1_dx1 csi2_1_dx1 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AH7 csi2_1_dx2 csi2_1_dx2 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AH5 csi2_1_dy0 csi2_1_dy0 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AH6 csi2_1_dy1 csi2_1_dy1 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
AG7 csi2_1_dy2 csi2_1_dy2 0 I 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
G19 dcan1_rx dcan1_rx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart8_txd 2 O
mmc2_sdwp 3 I
sata1_led 4 O
hdmi1_cec No 6 IO
gpio1_15 14 IO
Driver off 15 I
G20 dcan1_tx dcan1_tx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart8_rxd 2 I
mmc2_sdcd 3 I
hdmi1_hpd No 6 IO
gpio1_14 14 IO
Driver off 15 I
AD20 ddr1_a0 ddr1_a0 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC19 ddr1_a1 ddr1_a1 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC20 ddr1_a2 ddr1_a2 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB19 ddr1_a3 ddr1_a3 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF21 ddr1_a4 ddr1_a4 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AH22 ddr1_a5 ddr1_a5 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG23 ddr1_a6 ddr1_a6 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE21 ddr1_a7 ddr1_a7 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF22 ddr1_a8 ddr1_a8 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE22 ddr1_a9 ddr1_a9 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD21 ddr1_a10 ddr1_a10 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD22 ddr1_a11 ddr1_a11 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC21 ddr1_a12 ddr1_a12 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF18 ddr1_a13 ddr1_a13 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE17 ddr1_a14 ddr1_a14 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD18 ddr1_a15 ddr1_a15 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF17 ddr1_ba0 ddr1_ba0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE18 ddr1_ba1 ddr1_ba1 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB18 ddr1_ba2 ddr1_ba2 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC18 ddr1_casn ddr1_casn 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG24 ddr1_ck ddr1_ck 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG22 ddr1_cke ddr1_cke 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AH23 ddr1_csn0 ddr1_csn0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB16 ddr1_csn1 ddr1_csn1 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF25 ddr1_d0 ddr1_d0 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF26 ddr1_d1 ddr1_d1 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG26 ddr1_d2 ddr1_d2 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AH26 ddr1_d3 ddr1_d3 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF24 ddr1_d4 ddr1_d4 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE24 ddr1_d5 ddr1_d5 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF23 ddr1_d6 ddr1_d6 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE23 ddr1_d7 ddr1_d7 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC23 ddr1_d8 ddr1_d8 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF27 ddr1_d9 ddr1_d9 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG27 ddr1_d10 ddr1_d10 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF28 ddr1_d11 ddr1_d11 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE26 ddr1_d12 ddr1_d12 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC25 ddr1_d13 ddr1_d13 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC24 ddr1_d14 ddr1_d14 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD25 ddr1_d15 ddr1_d15 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
V20 ddr1_d16 ddr1_d16 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
W20 ddr1_d17 ddr1_d17 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB28 ddr1_d18 ddr1_d18 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC28 ddr1_d19 ddr1_d19 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC27 ddr1_d20 ddr1_d20 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y19 ddr1_d21 ddr1_d21 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB27 ddr1_d22 ddr1_d22 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y20 ddr1_d23 ddr1_d23 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA23 ddr1_d24 ddr1_d24 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y22 ddr1_d25 ddr1_d25 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y23 ddr1_d26 ddr1_d26 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA24 ddr1_d27 ddr1_d27 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y24 ddr1_d28 ddr1_d28 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA26 ddr1_d29 ddr1_d29 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA25 ddr1_d30 ddr1_d30 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA28 ddr1_d31 ddr1_d31 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD23 ddr1_dqm0 ddr1_dqm0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB23 ddr1_dqm1 ddr1_dqm1 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC26 ddr1_dqm2 ddr1_dqm2 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA27 ddr1_dqm3 ddr1_dqm3 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
V26 ddr1_dqm_ecc ddr1_dqm_ecc 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AH25 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
AE27 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
AD27 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
Y28 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
AG25 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
AE28 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
AD28 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
Y27 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
V28 ddr1_dqsn_ecc ddr1_dqsn_ecc 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
V27 ddr1_dqs_ecc ddr1_dqs_ecc 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
W22 ddr1_ecc_d0 ddr1_ecc_d0 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
V23 ddr1_ecc_d1 ddr1_ecc_d1 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
W19 ddr1_ecc_d2 ddr1_ecc_d2 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
W23 ddr1_ecc_d3 ddr1_ecc_d3 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y25 ddr1_ecc_d4 ddr1_ecc_d4 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
V24 ddr1_ecc_d5 ddr1_ecc_d5 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
V25 ddr1_ecc_d6 ddr1_ecc_d6 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y26 ddr1_ecc_d7 ddr1_ecc_d7 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AH24 ddr1_nck ddr1_nck 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE20 ddr1_odt0 ddr1_odt0 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC17 ddr1_odt1 ddr1_odt1 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AF20 ddr1_rasn ddr1_rasn 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AG21 ddr1_rst ddr1_rst 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y18 ddr1_vref0 ddr1_vref0 0 PWR OFF drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR
AH21 ddr1_wen ddr1_wen 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
G21 emu0 emu0 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_30 14 IO
D24 emu1 emu1 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_31 14 IO
AC5 gpio6_10 gpio6_10 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mdio_mclk 1 O
i2c3_sda 2 IO
vin2b_hsync1 4 I
vin1a_clk0 9 I
ehrpwm2A 10 O
pr2_mii_mt1_clk 11 I
pr2_pru0_gpi0 12 I
pr2_pru0_gpo0 13 O
gpio6_10 14 IO
Driver off 15 I
AB4 gpio6_11 gpio6_11 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mdio_d 1 IO
i2c3_scl 2 IO
vin2b_vsync1 4 I
vin1a_de0 9 I
ehrpwm2B 10 O
pr2_mii1_txen 11 O
pr2_pru0_gpi1 12 I
pr2_pru0_gpo1 13 O
gpio6_11 14 IO
Driver off 15 I
E21 gpio6_14 gpio6_14 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr8 1 IO
dcan2_tx 2 IO
uart10_rxd 3 I
vout2_hsync No 6 O
vin2a_hsync0
vin1a_hsync0 		8 I
i2c3_sda 9 IO
timer1 10 IO
gpio6_14 14 IO
Driver off 15 I
F20 gpio6_15 gpio6_15 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr9 1 IO
dcan2_rx 2 IO
uart10_txd 3 O
vout2_vsync No 6 O
vin2a_vsync0
vin1a_vsync0 		8 I
i2c3_scl 9 IO
timer2 10 IO
gpio6_15 14 IO
Driver off 15 I
F21 gpio6_16 gpio6_16 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr10 1 IO
vout2_fld No 6 O
vin2a_fld0
vin1a_fld0 		8 I
clkout1 9 O
timer3 10 IO
gpio6_16 14 IO
Driver off 15 I
R6 gpmc_a0 gpmc_a0 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d16 2 I
vout3_d16 No 3 O
vin2a_d0
vin1a_d0 		4 I
vin1b_d0 6 I
i2c4_scl 7 IO
uart5_rxd 8 I
gpio7_3
gpmc_a26
gpmc_a16 		14 IO
Driver off 15 I
T9 gpmc_a1 gpmc_a1 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d17 2 I
vout3_d17 No 3 O
vin2a_d1
vin1a_d1 		4 I
vin1b_d1 6 I
i2c4_sda 7 IO
uart5_txd 8 O
gpio7_4 14 IO
Driver off 15 I
T6 gpmc_a2 gpmc_a2 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d18 2 I
vout3_d18 No 3 O
vin2a_d2
vin1a_d2 		4 I
vin1b_d2 6 I
uart7_rxd 7 I
uart5_ctsn 8 I
gpio7_5 14 IO
Driver off 15 I
T7 gpmc_a3 gpmc_a3 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs2 1 O
vin1a_d19 2 I
vout3_d19 No 3 O
vin2a_d3
vin1a_d3 		4 I
vin1b_d3 6 I
uart7_txd 7 O
uart5_rtsn 8 O
gpio7_6 14 IO
Driver off 15 I
P6 gpmc_a4 gpmc_a4 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs3 1 O
vin1a_d20 2 I
vout3_d20 No 3 O
vin2a_d4
vin1a_d4 		4 I
vin1b_d4 6 I
i2c5_scl 7 IO
uart6_rxd 8 I
gpio1_26 14 IO
Driver off 15 I
R9 gpmc_a5 gpmc_a5 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d21 2 I
vout3_d21 No 3 O
vin2a_d5
vin1a_d5 		4 I
vin1b_d5 6 I
i2c5_sda 7 IO
uart6_txd 8 O
gpio1_27 14 IO
Driver off 15 I
R5 gpmc_a6 gpmc_a6 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d22 2 I
vout3_d22 No 3 O
vin2a_d6
vin1a_d6 		4 I
vin1b_d6 6 I
uart8_rxd 7 I
uart6_ctsn 8 I
gpio1_28 14 IO
Driver off 15 I
P5 gpmc_a7 gpmc_a7 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d23 2 I
vout3_d23 No 3 O
vin2a_d7
vin1a_d7 		4 I
vin1b_d7 6 I
uart8_txd 7 O
uart6_rtsn 8 O
gpio1_29 14 IO
Driver off 15 I
N7 gpmc_a8 gpmc_a8 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_hsync0 2 I
vout3_hsync No 3 O
vin1b_hsync1 6 I
timer12 7 IO
spi4_sclk 8 IO
gpio1_30 14 IO
Driver off 15 I
R4 gpmc_a9 gpmc_a9 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_vsync0 2 I
vout3_vsync No 3 O
vin1b_vsync1 6 I
timer11 7 IO
spi4_d1 8 IO
gpio1_31 14 IO
Driver off 15 I
N9 gpmc_a10 gpmc_a10 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_de0 2 I
vout3_de No 3 O
vin1b_clk1 6 I
timer10 7 IO
spi4_d0 8 IO
gpio2_0 14 IO
Driver off 15 I
P9 gpmc_a11 gpmc_a11 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_fld0 2 I
vout3_fld No 3 O
vin2a_fld0
vin1a_fld0 		4 I
vin1b_de1 6 I
timer9 7 IO
spi4_cs0 8 IO
gpio2_1 14 IO
Driver off 15 I
P4 gpmc_a12 gpmc_a12 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin2a_clk0
vin1a_clk0 		4 I
gpmc_a0 5 O
vin1b_fld1 6 I
timer8 7 IO
spi4_cs1 8 IO
dma_evt1 9 I
gpio2_2 14 IO
Driver off 15 I
R3 gpmc_a13 gpmc_a13 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_rtclk 1 I
vin2a_hsync0
vin1a_hsync0 		4 I
timer7 7 IO
spi4_cs2 8 IO
dma_evt2 9 I
gpio2_3 14 IO
Driver off 15 I
T2 gpmc_a14 gpmc_a14 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d3 1 IO
vin2a_vsync0
vin1a_vsync0 		4 I
timer6 7 IO
spi4_cs3 8 IO
gpio2_4 14 IO
Driver off 15 I
U2 gpmc_a15 gpmc_a15 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d2 1 IO
vin2a_d8
vin1a_d8 		4 I
timer5 7 IO
gpio2_5 14 IO
Driver off 15 I
U1 gpmc_a16 gpmc_a16 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d0 1 IO
vin2a_d9
vin1a_d9 		4 I
gpio2_6 14 IO
Driver off 15 I
P3 gpmc_a17 gpmc_a17 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d1 1 IO
vin2a_d10
vin1a_d10 		4 I
gpio2_7 14 IO
Driver off 15 I
R2 gpmc_a18 gpmc_a18 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_sclk 1 IO
vin2a_d11
vin1a_d11 		4 I
gpio2_8 14 IO
Driver off 15 I
K7(9) gpmc_a19 gpmc_a19 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat4 1 IO
gpmc_a13 2 O
vin2a_d12
vin1a_d12 		4 I
vin2b_d0
vin1b_d0 		6 I
gpio2_9 14 IO
Driver off 15 I
M7(9) gpmc_a20 gpmc_a20 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat5 1 IO
gpmc_a14 2 O
vin2a_d13
vin1a_d13 		4 I
vin2b_d1
vin1b_d1 		6 I
gpio2_10 14 IO
Driver off 15 I
J5(9) gpmc_a21 gpmc_a21 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat6 1 IO
gpmc_a15 2 O
vin2a_d14
vin1a_d14 		4 I
vin2b_d2
vin1b_d2 		6 I
gpio2_11 14 IO
Driver off 15 I
K6(9) gpmc_a22 gpmc_a22 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat7 1 IO
gpmc_a16 2 O
vin2a_d15
vin1a_d15 		4 I
vin2b_d3
vin1b_d3 		6 I
gpio2_12 14 IO
Driver off 15 I
J7 gpmc_a23 gpmc_a23 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_clk 1 IO
gpmc_a17 2 O
vin2a_fld0
vin1a_fld0 		4 I
vin2b_d4
vin1b_d4 		6 I
gpio2_13 14 IO
Driver off 15 I
J4(9) gpmc_a24 gpmc_a24 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat0 1 IO
gpmc_a18 2 O
vin2b_d5
vin1b_d5 		6 I
gpio2_14 14 IO
Driver off 15 I
J6(9) gpmc_a25 gpmc_a25 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat1 1 IO
gpmc_a19 2 O
vin2b_d6
vin1b_d6 		6 I
gpio2_15 14 IO
Driver off 15 I
H4(9) gpmc_a26 gpmc_a26 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat2 1 IO
gpmc_a20 2 O
vin2b_d7
vin1b_d7 		6 I
gpio2_16 14 IO
Driver off 15 I
H5(9) gpmc_a27 gpmc_a27 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat3 1 IO
gpmc_a21 2 O
vin2b_hsync1
vin1b_hsync1 		6 I
gpio2_17 14 IO
Driver off 15 I
M6 gpmc_ad0 gpmc_ad0 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d0 2 I
vout3_d0 No 3 O
gpio1_6 14 IO
sysboot0 15 I
M2 gpmc_ad1 gpmc_ad1 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d1 2 I
vout3_d1 No 3 O
gpio1_7 14 IO
sysboot1 15 I
L5 gpmc_ad2 gpmc_ad2 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d2 2 I
vout3_d2 No 3 O
gpio1_8 14 IO
sysboot2 15 I
M1 gpmc_ad3 gpmc_ad3 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d3 2 I
vout3_d3 No 3 O
gpio1_9 14 IO
sysboot3 15 I
L6 gpmc_ad4 gpmc_ad4 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d4 2 I
vout3_d4 No 3 O
gpio1_10 14 IO
sysboot4 15 I
L4 gpmc_ad5 gpmc_ad5 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d5 2 I
vout3_d5 No 3 O
gpio1_11 14 IO
sysboot5 15 I
L3 gpmc_ad6 gpmc_ad6 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d6 2 I
vout3_d6 No 3 O
gpio1_12 14 IO
sysboot6 15 I
L2 gpmc_ad7 gpmc_ad7 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d7 2 I
vout3_d7 No 3 O
gpio1_13 14 IO
sysboot7 15 I
L1 gpmc_ad8 gpmc_ad8 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d8 2 I
vout3_d8 No 3 O
gpio7_18 14 IO
sysboot8 15 I
K2 gpmc_ad9 gpmc_ad9 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d9 2 I
vout3_d9 No 3 O
gpio7_19 14 IO
sysboot9 15 I
J1 gpmc_ad10 gpmc_ad10 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d10 2 I
vout3_d10 No 3 O
gpio7_28 14 IO
sysboot10 15 I
J2 gpmc_ad11 gpmc_ad11 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d11 2 I
vout3_d11 No 3 O
gpio7_29 14 IO
sysboot11 15 I
H1 gpmc_ad12 gpmc_ad12 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d12 2 I
vout3_d12 No 3 O
gpio1_18 14 IO
sysboot12 15 I
J3 gpmc_ad13 gpmc_ad13 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d13 2 I
vout3_d13 No 3 O
gpio1_19 14 IO
sysboot13 15 I
H2 gpmc_ad14 gpmc_ad14 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d14 2 I
vout3_d14 No 3 O
gpio1_20 14 IO
sysboot14 15 I
H3 gpmc_ad15 gpmc_ad15 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d15 2 I
vout3_d15 No 3 O
gpio1_21 14 IO
sysboot15 15 I
N1 gpmc_advn_ale gpmc_advn_ale 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs6 1 O
clkout2 2 O
gpmc_wait1 3 I
vin2a_vsync0
vin1a_vsync0 		4 I
gpmc_a2 5 O
gpmc_a23 6 O
timer3 7 IO
i2c3_sda 8 IO
dma_evt2 9 I
gpio2_23
gpmc_a19 		14 IO
Driver off 15 I
N6 gpmc_ben0 gpmc_ben0 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs4 1 O
vin2b_de1
vin1b_de1 		6 I
timer2 7 IO
dma_evt3 9 I
gpio2_26
gpmc_a21 		14 IO
Driver off 15 I
M4 gpmc_ben1 gpmc_ben1 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs5 1 O
vin2b_clk1
vin1b_clk1 		4 I
gpmc_a3 5 O
vin2b_fld1
vin1b_fld1 		6 I
timer1 7 IO
dma_evt4 9 I
gpio2_27
gpmc_a22 		14 IO
Driver off 15 I
P7 gpmc_clk gpmc_clk 0 IO PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs7 1 O
clkout1 2 O
gpmc_wait1 3 I
vin2a_hsync0
vin1a_hsync0 		4 I
vin2a_de0
vin1a_de0 		5 I
vin2b_clk1
vin1b_clk1 		6 I
timer4 7 IO
i2c3_scl 8 IO
dma_evt1 9 I
gpio2_22
gpmc_a20 		14 IO
Driver off 15 I
T1 gpmc_cs0 gpmc_cs0 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_19 14 IO
Driver off 15 I
H6 gpmc_cs1 gpmc_cs1 0 O PU PU 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_cmd 1 IO
gpmc_a22 2 O
vin2a_de0
vin1a_de0 		4 I
vin2b_vsync1
vin1b_vsync1 		6 I
gpio2_18 14 IO
Driver off 15 I
P2 gpmc_cs2 gpmc_cs2 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs0 1 IO
gpio2_20
gpmc_a23
gpmc_a13 		14 IO
Driver off 15 I
P1 gpmc_cs3 gpmc_cs3 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs1 1 O
vin1a_clk0 2 I
vout3_clk No 3 O
gpmc_a1 5 O
gpio2_21
gpmc_a24
gpmc_a14 		14 IO
Driver off 15 I
M5 gpmc_oen_ren gpmc_oen_ren 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_24 14 IO
Driver off 15 I
N2 gpmc_wait0 gpmc_wait0 0 I PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_28
gpmc_a25
gpmc_a15 		14 IO
Driver off 15 I
M3 gpmc_wen gpmc_wen 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_25 14 IO
Driver off 15 I
AG16 hdmi1_clockx hdmi1_clockx No 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AH16 hdmi1_clocky hdmi1_clocky No 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AG17 hdmi1_data0x hdmi1_data0x No 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AH17 hdmi1_data0y hdmi1_data0y No 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AG18 hdmi1_data1x hdmi1_data1x No 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AH18 hdmi1_data1y hdmi1_data1y No 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AG19 hdmi1_data2x hdmi1_data2x No 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AH19 hdmi1_data2y hdmi1_data2y No 0 O 1.8 vdda_hdmi HDMIPHY Pdy
C20 i2c1_scl i2c1_scl 0 IO 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
Driver off 15 I
C21 i2c1_sda i2c1_sda 0 IO 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
Driver off 15 I
F17 i2c2_scl i2c2_scl 0 IO 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
hdmi1_ddc_sda No 1 IO
Driver off 15 I
C25 i2c2_sda i2c2_sda 0 IO 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
hdmi1_ddc_scl No 1 IO
Driver off 15 I
AH15 ljcb_clkn ljcb_clkn 0 IO 1.8 vdda_pcie LJCB
AG15 ljcb_clkp ljcb_clkp 0 IO 1.8 vdda_pcie LJCB
B14 mcasp1_aclkr mcasp1_aclkr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_axr2 1 IO
vout2_d0 No 6 O
vin2a_d0
vin1a_d0 		8 I
i2c4_sda 10 IO
gpio5_0 14 IO
Driver off 15 I
C14 mcasp1_aclkx mcasp1_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vin1a_fld0 7 I
i2c3_sda 10 IO
pr2_mdio_mdclk 11 O
pr2_pru1_gpi7 12 I
pr2_pru1_gpo7 13 O
gpio7_31 14 IO
Driver off 15 I
G12 mcasp1_axr0 mcasp1_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart6_rxd 3 I
vin1a_vsync0 7 I
i2c5_sda 10 IO
pr2_mii0_rxer 11 I
pr2_pru1_gpi8 12 I
pr2_pru1_gpo8 13 O
gpio5_2 14 IO
Driver off 15 I
F12 mcasp1_axr1 mcasp1_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart6_txd 3 O
vin1a_hsync0 7 I
i2c5_scl 10 IO
pr2_mii_mt0_clk 11 I
pr2_pru1_gpi9 12 I
pr2_pru1_gpo9 13 O
gpio5_3 14 IO
Driver off 15 I
G13 mcasp1_axr2 mcasp1_axr2 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_axr2 1 IO
uart6_ctsn 3 I
vout2_d2 No 6 O
vin2a_d2
vin1a_d2 		8 I
gpio5_4 14 IO
Driver off 15 I
J11 mcasp1_axr3 mcasp1_axr3 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_axr3 1 IO
uart6_rtsn 3 O
vout2_d3 No 6 O
vin2a_d3
vin1a_d3 		8 I
gpio5_5 14 IO
Driver off 15 I
E12 mcasp1_axr4 mcasp1_axr4 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp4_axr2 1 IO
vout2_d4 No 6 O
vin2a_d4
vin1a_d4 		8 I
gpio5_6 14 IO
Driver off 15 I
F13 mcasp1_axr5 mcasp1_axr5 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp4_axr3 1 IO
vout2_d5 No 6 O
vin2a_d5
vin1a_d5 		8 I
gpio5_7 14 IO
Driver off 15 I
C12 mcasp1_axr6 mcasp1_axr6 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp5_axr2 1 IO
vout2_d6 No 6 O
vin2a_d6
vin1a_d6 		8 I
gpio5_8 14 IO
Driver off 15 I
D12 mcasp1_axr7 mcasp1_axr7 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp5_axr3 1 IO
vout2_d7 No 6 O
vin2a_d7
vin1a_d7 		8 I
timer4 10 IO
gpio5_9 14 IO
Driver off 15 I
B12 mcasp1_axr8 mcasp1_axr8 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_axr0 1 IO
spi3_sclk 3 IO
vin1a_d15 7 I
timer5 10 IO
pr2_mii0_txen 11 O
pr2_pru1_gpi10 12 I
pr2_pru1_gpo10 13 O
gpio5_10 14 IO
Driver off 15 I
A11 mcasp1_axr9 mcasp1_axr9 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_axr1 1 IO
spi3_d1 3 IO
vin1a_d14 7 I
timer6 10 IO
pr2_mii0_txd3 11 O
pr2_pru1_gpi11 12 I
pr2_pru1_gpo11 13 O
gpio5_11 14 IO
Driver off 15 I
B13 mcasp1_axr10 mcasp1_axr10 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_aclkx 1 IO
mcasp6_aclkr 2 IO
spi3_d0 3 IO
vin1a_d13 7 I
timer7 10 IO
pr2_mii0_txd2 11 O
pr2_pru1_gpi12 12 I
pr2_pru1_gpo12 13 O
gpio5_12 14 IO
Driver off 15 I
A12 mcasp1_axr11 mcasp1_axr11 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp6_fsx 1 IO
mcasp6_fsr 2 IO
spi3_cs0 3 IO
vin1a_d12 7 I
timer8 10 IO
pr2_mii0_txd1 11 O
pr2_pru1_gpi13 12 I
pr2_pru1_gpo13 13 O
gpio4_17 14 IO
Driver off 15 I
E14 mcasp1_axr12 mcasp1_axr12 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_axr0 1 IO
spi3_cs1 3 IO
vin1a_d11 7 I
timer9 10 IO
pr2_mii0_txd0 11 O
pr2_pru1_gpi14 12 I
pr2_pru1_gpo14 13 O
gpio4_18 14 IO
Driver off 15 I
A13 mcasp1_axr13 mcasp1_axr13 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_axr1 1 IO
vin1a_d10 7 I
timer10 10 IO
pr2_mii_mr0_clk 11 I
pr2_pru1_gpi15 12 I
pr2_pru1_gpo15 13 O
gpio6_4 14 IO
Driver off 15 I
G14 mcasp1_axr14 mcasp1_axr14 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_aclkx 1 IO
mcasp7_aclkr 2 IO
vin1a_d9 7 I
timer11 10 IO
pr2_mii0_rxdv 11 I
pr2_pru1_gpi16 12 I
pr2_pru1_gpo16 13 O
gpio6_5 14 IO
Driver off 15 I
F14 mcasp1_axr15 mcasp1_axr15 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_fsx 1 IO
mcasp7_fsr 2 IO
vin1a_d8 7 I
timer12 10 IO
pr2_mii0_rxd3 11 I
pr2_pru0_gpi20 12 I
pr2_pru0_gpo20 13 O
gpio6_6 14 IO
Driver off 15 I
J14 mcasp1_fsr mcasp1_fsr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp7_axr3 1 IO
vout2_d1 No 6 O
vin2a_d1
vin1a_d1 		8 I
i2c4_scl 10 IO
gpio5_1 14 IO
Driver off 15 I
D14 mcasp1_fsx mcasp1_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vin1a_de0 7 I
i2c3_scl 10 IO
pr2_mdio_data 11 IO
gpio7_30 14 IO
Driver off 15 I
E15 mcasp2_aclkr mcasp2_aclkr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_axr2 1 IO
vout2_d8 No 6 O
vin2a_d8
vin1a_d8 		8 I
Driver off 15 I
A19 mcasp2_aclkx mcasp2_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vin1a_d7 7 I
pr2_mii0_rxd2 11 I
pr2_pru0_gpi18 12 I
pr2_pru0_gpo18 13 O
Driver off 15 I
B15 mcasp2_axr0 mcasp2_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vout2_d10 No 6 O
vin2a_d10
vin1a_d10 		8 I
Driver off 15 I
A15 mcasp2_axr1 mcasp2_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vout2_d11 No 6 O
vin2a_d11
vin1a_d11 		8 I
Driver off 15 I
C15 mcasp2_axr2 mcasp2_axr2 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp3_axr2 1 IO
vin1a_d5 7 I
pr2_mii0_rxd0 11 I
pr2_pru0_gpi16 12 I
pr2_pru0_gpo16 13 O
gpio6_8 14 IO
Driver off 15 I
A16 mcasp2_axr3 mcasp2_axr3 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp3_axr3 1 IO
vin1a_d4 7 I
pr2_mii0_rxlink 11 I
pr2_pru0_gpi17 12 I
pr2_pru0_gpo17 13 O
gpio6_9 14 IO
Driver off 15 I
D15 mcasp2_axr4 mcasp2_axr4 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_axr0 1 IO
vout2_d12 No 6 O
vin2a_d12
vin1a_d12 		8 I
gpio1_4 14 IO
Driver off 15 I
B16 mcasp2_axr5 mcasp2_axr5 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_axr1 1 IO
vout2_d13 No 6 O
vin2a_d13
vin1a_d13 		8 I
gpio6_7 14 IO
Driver off 15 I
B17 mcasp2_axr6 mcasp2_axr6 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_aclkx 1 IO
mcasp8_aclkr 2 IO
vout2_d14 No 6 O
vin2a_d14
vin1a_d14 		8 I
gpio2_29 14 IO
Driver off 15 I
A17 mcasp2_axr7 mcasp2_axr7 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_fsx 1 IO
mcasp8_fsr 2 IO
vout2_d15 No 6 O
vin2a_d15
vin1a_d15 		8 I
gpio1_5 14 IO
Driver off 15 I
A20 mcasp2_fsr mcasp2_fsr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp8_axr3 1 IO
vout2_d9 No 6 O
vin2a_d9
vin1a_d9 		8 I
Driver off 15 I
A18 mcasp2_fsx mcasp2_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
vin1a_d6 7 I
pr2_mii0_rxd1 11 I
pr2_pru0_gpi19 12 I
pr2_pru0_gpo19 13 O
Driver off 15 I
B18 mcasp3_aclkx mcasp3_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp3_aclkr 1 IO
mcasp2_axr12 2 IO
uart7_rxd 3 I
vin1a_d3 7 I
pr2_mii0_crs 11 I
pr2_pru0_gpi12 12 I
pr2_pru0_gpo12 13 O
gpio5_13 14 IO
Driver off 15 I
B19 mcasp3_axr0 mcasp3_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr14 2 IO
uart7_ctsn 3 I
uart5_rxd 4 I
vin1a_d1 7 I
pr2_mii1_rxer 11 I
pr2_pru0_gpi14 12 I
pr2_pru0_gpo14 13 O
Driver off 15 I
C17 mcasp3_axr1 mcasp3_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr15 2 IO
uart7_rtsn 3 O
uart5_txd 4 O
vin1a_d0 7 I
vin1a_fld0 9 I
pr2_mii1_rxlink 11 I
pr2_pru0_gpi15 12 I
pr2_pru0_gpo15 13 O
Driver off 15 I
F15 mcasp3_fsx mcasp3_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp3_fsr 1 IO
mcasp2_axr13 2 IO
uart7_txd 3 O
vin1a_d2 7 I
pr2_mii0_col 11 I
pr2_pru0_gpi13 12 I
pr2_pru0_gpo13 13 O
gpio5_14 14 IO
Driver off 15 I
C18 mcasp4_aclkx mcasp4_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp4_aclkr 1 IO
spi3_sclk 2 IO
uart8_rxd 3 I
i2c4_sda 4 IO
vout2_d16 No 6 O
vin2a_d16
vin1a_d16 		8 I
vin1a_d15 9 I
Driver off 15 I
G16 mcasp4_axr0 mcasp4_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
spi3_d0 2 IO
uart8_ctsn 3 I
uart4_rxd 4 I
vout2_d18 No 6 O
vin2a_d18
vin1a_d18 		8 I
vin1a_d13 9 I
Driver off 15 I
D17 mcasp4_axr1 mcasp4_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
spi3_cs0 2 IO
uart8_rtsn 3 O
uart4_txd 4 O
vout2_d19 No 6 O
vin2a_d19
vin1a_d19 		8 I
vin1a_d12 9 I
pr2_pru1_gpi0 12 I
pr2_pru1_gpo0 13 O
Driver off 15 I
A21 mcasp4_fsx mcasp4_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp4_fsr 1 IO
spi3_d1 2 IO
uart8_txd 3 O
i2c4_scl 4 IO
vout2_d17 No 6 O
vin2a_d17
vin1a_d17 		8 I
vin1a_d14 9 I
Driver off 15 I
AA3 mcasp5_aclkx mcasp5_aclkx 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mcasp5_aclkr 1 IO
spi4_sclk 2 IO
uart9_rxd 3 I
i2c5_sda 4 IO
vout2_d20 No 6 O
vin2a_d20
vin1a_d20 		8 I
vin1a_d11 9 I
pr2_pru1_gpi1 12 I
pr2_pru1_gpo1 13 O
Driver off 15 I
AB3 mcasp5_axr0 mcasp5_axr0 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_d0 2 IO
uart9_ctsn 3 I
uart3_rxd 4 I
vout2_d22 No 6 O
vin2a_d22
vin1a_d22 		8 I
vin1a_d9 9 I
pr2_mdio_mdclk 11 O
pr2_pru1_gpi3 12 I
pr2_pru1_gpo3 13 O
Driver off 15 I
AA4 mcasp5_axr1 mcasp5_axr1 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_cs0 2 IO
uart9_rtsn 3 O
uart3_txd 4 O
vout2_d23 No 6 O
vin2a_d23
vin1a_d23 		8 I
vin1a_d8 9 I
pr2_mdio_data 11 IO
pr2_pru1_gpi4 12 I
pr2_pru1_gpo4 13 O
Driver off 15 I
AB9 mcasp5_fsx mcasp5_fsx 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mcasp5_fsr 1 IO
spi4_d1 2 IO
uart9_txd 3 O
i2c5_scl 4 IO
vout2_d21 No 6 O
vin2a_d21
vin1a_d21 		8 I
vin1a_d10 9 I
pr2_pru1_gpi2 12 I
pr2_pru1_gpo2 13 O
Driver off 15 I
U4 mdio_d mdio_d 0 IO PU PU 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_ctsn 1 I
mii0_txer 3 O
vin2a_d0 4 I
vin1b_d0 5 I
pr1_mii0_rxlink 11 I
pr2_pru1_gpi1 12 I
pr2_pru1_gpo1 13 O
gpio5_16 14 IO
Driver off 15 I
V1 mdio_mclk mdio_mclk 0 O PU PU 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
mii0_col 3 I
vin2a_clk0 4 I
vin1b_clk1 5 I
pr1_mii0_col 11 I
pr2_pru1_gpi0 12 I
pr2_pru1_gpo0 13 O
gpio5_15 14 IO
Driver off 15 I
AB2 mlbp_clk_n mlbp_clk_n 0 I vdds_mlbp No BMLB18
AB1 mlbp_clk_p mlbp_clk_p 0 I vdds_mlbp No BMLB18
AA2 mlbp_dat_n mlbp_dat_n 0 IO OFF OFF vdds_mlbp No BMLB18
AA1 mlbp_dat_p mlbp_dat_p 0 IO OFF OFF vdds_mlbp No BMLB18
AC2 mlbp_sig_n mlbp_sig_n 0 IO OFF OFF vdds_mlbp No BMLB18
AC1 mlbp_sig_p mlbp_sig_p 0 IO OFF OFF vdds_mlbp No BMLB18
W6 mmc1_clk mmc1_clk 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_21 14 IO
Driver off 15 I
Y6 mmc1_cmd mmc1_cmd 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_22 14 IO
Driver off 15 I
AA6 mmc1_dat0 mmc1_dat0 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_23 14 IO
Driver off 15 I
Y4 mmc1_dat1 mmc1_dat1 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_24 14 IO
Driver off 15 I
AA5 mmc1_dat2 mmc1_dat2 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_25 14 IO
Driver off 15 I
Y3 mmc1_dat3 mmc1_dat3 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy
gpio6_26 14 IO
Driver off 15 I
W7 mmc1_sdcd mmc1_sdcd 0 I PU PU 15 1.8/3.3 vddshv8 Yes Dual Voltage LVCMOS PU/PD
uart6_rxd 3 I
i2c4_sda 4 IO
gpio6_27 14 IO
Driver off 15 I
Y9 mmc1_sdwp mmc1_sdwp 0 I PD PD 15 1.8/3.3 vddshv8 Yes Dual Voltage LVCMOS PU/PD
uart6_txd 3 O
i2c4_scl 4 IO
gpio6_28 14 IO
Driver off 15 I
AD4 mmc3_clk mmc3_clk 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
vin2b_d7 4 I
vin1a_d7 9 I
ehrpwm2_tripzone_input 10 IO
pr2_mii1_txd3 11 O
pr2_pru0_gpi2 12 I
pr2_pru0_gpo2 13 O
gpio6_29 14 IO
Driver off 15 I
AC4 mmc3_cmd mmc3_cmd 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi3_sclk 1 IO
vin2b_d6 4 I
vin1a_d6 9 I
eCAP2_in_PWM2_out 10 IO
pr2_mii1_txd2 11 O
pr2_pru0_gpi3 12 I
pr2_pru0_gpo3 13 O
gpio6_30 14 IO
Driver off 15 I
AC7 mmc3_dat0 mmc3_dat0 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi3_d1 1 IO
uart5_rxd 2 I
vin2b_d5 4 I
vin1a_d5 9 I
eQEP3A_in 10 I
pr2_mii1_txd1 11 O
pr2_pru0_gpi4 12 I
pr2_pru0_gpo4 13 O
gpio6_31 14 IO
Driver off 15 I
AC6 mmc3_dat1 mmc3_dat1 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi3_d0 1 IO
uart5_txd 2 O
vin2b_d4 4 I
vin1a_d4 9 I
eQEP3B_in 10 I
pr2_mii1_txd0 11 O
pr2_pru0_gpi5 12 I
pr2_pru0_gpo5 13 O
gpio7_0 14 IO
Driver off 15 I
AC9 mmc3_dat2 mmc3_dat2 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi3_cs0 1 IO
uart5_ctsn 2 I
vin2b_d3 4 I
vin1a_d3 9 I
eQEP3_index 10 IO
pr2_mii_mr1_clk 11 I
pr2_pru0_gpi6 12 I
pr2_pru0_gpo6 13 O
gpio7_1 14 IO
Driver off 15 I
AC3 mmc3_dat3 mmc3_dat3 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi3_cs1 1 IO
uart5_rtsn 2 O
vin2b_d2 4 I
vin1a_d2 9 I
eQEP3_strobe 10 IO
pr2_mii1_rxdv 11 I
pr2_pru0_gpi7 12 I
pr2_pru0_gpo7 13 O
gpio7_2 14 IO
Driver off 15 I
AC8 mmc3_dat4 mmc3_dat4 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_sclk 1 IO
uart10_rxd 2 I
vin2b_d1 4 I
vin1a_d1 9 I
ehrpwm3A 10 O
pr2_mii1_rxd3 11 I
pr2_pru0_gpi8 12 I
pr2_pru0_gpo8 13 O
gpio1_22 14 IO
Driver off 15 I
AD6 mmc3_dat5 mmc3_dat5 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_d1 1 IO
uart10_txd 2 O
vin2b_d0 4 I
vin1a_d0 9 I
ehrpwm3B 10 O
pr2_mii1_rxd2 11 I
pr2_pru0_gpi9 12 I
pr2_pru0_gpo9 13 O
gpio1_23 14 IO
Driver off 15 I
AB8 mmc3_dat6 mmc3_dat6 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_d0 1 IO
uart10_ctsn 2 I
vin2b_de1 4 I
vin1a_hsync0 9 I
ehrpwm3_tripzone_input 10 IO
pr2_mii1_rxd1 11 I
pr2_pru0_gpi10 12 I
pr2_pru0_gpo10 13 O
gpio1_24 14 IO
Driver off 15 I
AB5 mmc3_dat7 mmc3_dat7 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
spi4_cs0 1 IO
uart10_rtsn 2 O
vin2b_clk1 4 I
vin1a_vsync0 9 I
eCAP3_in_PWM3_out 10 IO
pr2_mii1_rxd0 11 I
pr2_pru0_gpi11 12 I
pr2_pru0_gpo11 13 O
gpio1_25 14 IO
Driver off 15 I
D21 nmin_dsp nmin_dsp 0 I PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
Y11 on_off on_off 0 O PU drive 1 (OFF) 1.8/3.3 vddshv5 Yes BC1833IHHV PU/PD
AG13 pcie_rxn0 pcie_rxn0 0 I OFF OFF 1.8 vdda_pcie0 SERDES
AH13 pcie_rxp0 pcie_rxp0 0 I OFF OFF 1.8 vdda_pcie0 SERDES
AG14 pcie_txn0 pcie_txn0 0 O 1.8 vdda_pcie0 SERDES
AH14 pcie_txp0 pcie_txp0 0 O 1.8 vdda_pcie0 SERDES
F22 porz porz 0 I 1.8/3.3 vddshv3 Yes IHHV1833 PU/PD
E23 resetn resetn 0 I PU PU 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
U5 rgmii0_rxc rgmii0_rxc 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_txen 2 O
mii0_txclk 3 I
vin2a_d5 4 I
vin1b_d5 5 I
pr1_mii_mt0_clk 11 I
pr2_pru1_gpi11 12 I
pr2_pru1_gpo11 13 O
gpio5_26 14 IO
Driver off 15 I
V5 rgmii0_rxctl rgmii0_rxctl 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_txd1 2 O
mii0_txd3 3 O
vin2a_d6 4 I
vin1b_d6 5 I
pr1_mii0_txd3 11 O
pr2_pru1_gpi12 12 I
pr2_pru1_gpo12 13 O
gpio5_27 14 IO
Driver off 15 I
W2 rgmii0_rxd0 rgmii0_rxd0 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_txd0 1 O
mii0_txd0 3 O
vin2a_fld0 4 I
vin1b_fld1 5 I
pr1_mii0_txd0 11 O
pr2_pru1_gpi16 12 I
pr2_pru1_gpo16 13 O
gpio5_31 14 IO
Driver off 15 I
Y2 rgmii0_rxd1 rgmii0_rxd1 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_txd1 1 O
mii0_txd1 3 O
vin2a_d9 4 I
pr1_mii0_txd1 11 O
pr2_pru1_gpi15 12 I
pr2_pru1_gpo15 13 O
gpio5_30 14 IO
Driver off 15 I
V3 rgmii0_rxd2 rgmii0_rxd2 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_txen 1 O
mii0_txen 3 O
vin2a_d8 4 I
pr1_mii0_txen 11 O
pr2_pru1_gpi14 12 I
pr2_pru1_gpo14 13 O
gpio5_29 14 IO
Driver off 15 I
V4 rgmii0_rxd3 rgmii0_rxd3 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_txd0 2 O
mii0_txd2 3 O
vin2a_d7 4 I
vin1b_d7 5 I
pr1_mii0_txd2 11 O
pr2_pru1_gpi13 12 I
pr2_pru1_gpo13 13 O
gpio5_28 14 IO
Driver off 15 I
W9 rgmii0_txc rgmii0_txc 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_ctsn 1 I
rmii1_rxd1 2 I
mii0_rxd3 3 I
vin2a_d3 4 I
vin1b_d3 5 I
spi3_d0 7 IO
spi4_cs2 8 IO
pr1_mii0_rxd3 11 I
pr2_pru1_gpi5 12 I
pr2_pru1_gpo5 13 O
gpio5_20 14 IO
Driver off 15 I
V9 rgmii0_txctl rgmii0_txctl 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
rmii1_rxd0 2 I
mii0_rxd2 3 I
vin2a_d4 4 I
vin1b_d4 5 I
spi3_cs0 7 IO
spi4_cs3 8 IO
pr1_mii0_rxd2 11 I
pr2_pru1_gpi6 12 I
pr2_pru1_gpo6 13 O
gpio5_21 14 IO
Driver off 15 I
U6 rgmii0_txd0 rgmii0_txd0 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxd0 1 I
mii0_rxd0 3 I
vin2a_d10 4 I
spi4_cs0 7 IO
uart4_rtsn 8 O
pr1_mii0_rxd0 11 I
pr2_pru1_gpi10 12 I
pr2_pru1_gpo10 13 O
gpio5_25 14 IO
Driver off 15 I
V6 rgmii0_txd1 rgmii0_txd1 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxd1 1 I
mii0_rxd1 3 I
vin2a_vsync0 4 I
vin1b_vsync1 5 I
spi4_d0 7 IO
uart4_ctsn 8 IO
pr1_mii0_rxd1 11 I
pr2_pru1_gpi9 12 I
pr2_pru1_gpo9 13 O
gpio5_24 14 IO
Driver off 15 I
U7 rgmii0_txd2 rgmii0_txd2 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxer 1 I
mii0_rxer 3 I
vin2a_hsync0 4 I
vin1b_hsync1 5 I
spi4_d1 7 IO
uart4_txd 8 O
pr1_mii0_rxer 11 I
pr2_pru1_gpi8 12 I
pr2_pru1_gpo8 13 O
gpio5_23 14 IO
Driver off 15 I
V7 rgmii0_txd3 rgmii0_txd3 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_crs 1 I
mii0_crs 3 I
vin2a_de0 4 I
vin1b_de1 5 I
spi4_sclk 7 IO
uart4_rxd 8 I
pr1_mii0_crs 11 I
pr2_pru1_gpi7 12 I
pr2_pru1_gpo7 13 O
gpio5_22 14 IO
Driver off 15 I
U3 RMII_MHZ_50_CLK RMII_MHZ_50_CLK 0 IO PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
vin2a_d11 4 I
pr2_pru1_gpi2 12 I
pr2_pru1_gpo2 13 O
gpio5_17 14 IO
Driver off 15 I
F23 rstoutn rstoutn 0 O PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
E18 rtck rtck 0 O PU OFF 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_29 14 IO
AF14 rtc_iso rtc_iso 0 I 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
AE14 rtc_osc_xi_clkin32 rtc_osc_xi_clkin32 0 I 1.8 vdda_rtc No LVCMOS OSC
AD14 rtc_osc_xo rtc_osc_xo 0 O 1.8 vdda_rtc No LVCMOS OSC
AB17 rtc_porz rtc_porz 0 I 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
AH9 sata1_rxn0 sata1_rxn0 0 I OFF OFF 1.8 vdda_sata SATAPHY
AG9 sata1_rxp0 sata1_rxp0 0 I OFF OFF 1.8 vdda_sata SATAPHY
AG10 sata1_txn0 sata1_txn0 0 O 1.8 vdda_sata SATAPHY
AH10 sata1_txp0 sata1_txp0 0 O 1.8 vdda_sata SATAPHY
A24 spi1_cs0 spi1_cs0 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio7_10 14 IO
Driver off 15 I
A22 spi1_cs1 spi1_cs1 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
sata1_led 2 O
spi2_cs1 3 IO
gpio7_11 14 IO
Driver off 15 I
B21 spi1_cs2 spi1_cs2 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart4_rxd 1 I
mmc3_sdcd 2 I
spi2_cs2 3 IO
dcan2_tx 4 IO
mdio_mclk 5 O
hdmi1_hpd No 6 IO
gpio7_12 14 IO
Driver off 15 I
B20 spi1_cs3 spi1_cs3 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart4_txd 1 O
mmc3_sdwp 2 I
spi2_cs3 3 IO
dcan2_rx 4 IO
mdio_d 5 IO
hdmi1_cec No 6 IO
gpio7_13 14 IO
Driver off 15 I
B25 spi1_d0 spi1_d0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio7_9 14 IO
Driver off 15 I
F16 spi1_d1 spi1_d1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio7_8 14 IO
Driver off 15 I
A25 spi1_sclk spi1_sclk 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio7_7 14 IO
Driver off 15 I
B24 spi2_cs0 spi2_cs0 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
uart5_txd 2 O
gpio7_17 14 IO
Driver off 15 I
G17 spi2_d0 spi2_d0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart3_ctsn 1 I
uart5_rxd 2 I
gpio7_16 14 IO
Driver off 15 I
B22 spi2_d1 spi2_d1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart3_txd 1 O
gpio7_15 14 IO
Driver off 15 I
A26 spi2_sclk spi2_sclk 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart3_rxd 1 I
gpio7_14 14 IO
Driver off 15 I
E20 tclk tclk 0 I PU PU 0 1.8/3.3 vddshv3 Yes IQ1833 PU/PD
D23 tdi tdi 0 I PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_27 14 I
F19 tdo tdo 0 O PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_28 14 IO
F18 tms tms 0 I PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
D20 trstn trstn 0 I PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
E25 uart1_ctsn uart1_ctsn 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart9_rxd 2 I
mmc4_clk 3 IO
gpio7_24 14 IO
Driver off 15 I
C27 uart1_rtsn uart1_rtsn 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart9_txd 2 O
mmc4_cmd 3 IO
gpio7_25 14 IO
Driver off 15 I
B27 uart1_rxd uart1_rxd 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
mmc4_sdcd 3 I
gpio7_22 14 IO
Driver off 15 I
C26 uart1_txd uart1_txd 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
mmc4_sdwp 3 I
gpio7_23 14 IO
Driver off 15 I
D27 uart2_ctsn uart2_ctsn 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_rxd 2 I
mmc4_dat2 3 IO
uart10_rxd 4 I
uart1_dtrn 5 O
gpio1_16 14 IO
Driver off 15 I
C28 uart2_rtsn uart2_rtsn 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_txd 1 O
uart3_irtx 2 O
mmc4_dat3 3 IO
uart10_txd 4 O
uart1_rin 5 I
gpio1_17 14 IO
Driver off 15 I
D28 uart2_rxd uart2_rxd 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_ctsn 1 I
uart3_rctx 2 O
mmc4_dat0 3 IO
uart2_rxd 4 I
uart1_dcdn 5 I
gpio7_26 14 IO
Driver off 15 I
D26 uart2_txd uart2_txd 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
uart3_sd 2 O
mmc4_dat1 3 IO
uart2_txd 4 O
uart1_dsrn 5 I
gpio7_27 14 IO
Driver off 15 I
V2 uart3_rxd uart3_rxd 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_crs 2 I
mii0_rxdv 3 I
vin2a_d1 4 I
vin1b_d1 5 I
spi3_sclk 7 IO
pr1_mii0_rxdv 11 I
pr2_pru1_gpi3 12 I
pr2_pru1_gpo3 13 O
gpio5_18 14 IO
Driver off 15 I
Y1 uart3_txd uart3_txd 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_rxer 2 I
mii0_rxclk 3 I
vin2a_d2 4 I
vin1b_d2 5 I
spi3_d1 7 IO
spi4_cs1 8 IO
pr1_mii_mr0_clk 11 I
pr2_pru1_gpi4 12 I
pr2_pru1_gpo4 13 O
gpio5_19 14 IO
Driver off 15 I
AC12 usb1_dm usb1_dm 0 IO OFF OFF 3.3 vdda33v_usb1 USBPHY
AD12 usb1_dp usb1_dp 0 IO OFF OFF 3.3 vdda33v_usb1 USBPHY
AB10 usb1_drvvbus usb1_drvvbus 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
timer16 7 IO
gpio6_12 14 IO
Driver off 15 I
AF11 usb2_dm usb2_dm 0 IO 3.3 vdda33v_usb2 No USBPHY
AE11 usb2_dp usb2_dp 0 IO 3.3 vdda33v_usb2 No USBPHY
AC10 usb2_drvvbus usb2_drvvbus 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
timer15 7 IO
gpio6_13 14 IO
Driver off 15 I
AF12 usb_rxn0 usb_rxn0 0 I OFF OFF 1.8 vdda_usb1 SERDES
pcie_rxn1 1 I
AE12 usb_rxp0 usb_rxp0 0 I OFF OFF 1.8 vdda_usb1 SERDES
pcie_rxp1 1 I
AC11 usb_txn0 usb_txn0 0 O 1.8 vdda_usb1 SERDES
pcie_txn1 1 O
AD11 usb_txp0 usb_txp0 0 O 1.8 vdda_usb1 SERDES
pcie_txp1 1 O
H13, H14, J17, J18, L7, L8, N10, N13, P11, P12, P13, R11, R16, R19, T13, T16, T19, U13, U16, U8, U9, V16, V8 vdd vdd PWR
AA12 vdda33v_usb1 vdda33v_usb1 PWR
Y12 vdda33v_usb2 vdda33v_usb2 PWR
P14 vdda_core_gmac vdda_core_gmac PWR
W12 vdda_csi vdda_csi PWR
R17 vdda_ddr vdda_ddr PWR
N11 vdda_debug vdda_debug PWR
N12 vdda_dsp_iva vdda_dsp_iva PWR
R14 vdda_gpu vdda_gpu PWR
Y17 vdda_hdmi vdda_hdmi PWR
N16 vdda_mpu_abe vdda_mpu_abe PWR
AD16, AE16 vdda_osc vdda_osc PWR
AA17 vdda_pcie vdda_pcie PWR
AA16 vdda_pcie0 vdda_pcie0 PWR
M14 vdda_per vdda_per PWR
P15 vdda_pll_spare vdda_pll_spare PWR
AB13 vdda_rtc vdda_rtc PWR
V13 vdda_sata vdda_sata PWR
AA13 vdda_usb1 vdda_usb1 PWR
AB12 vdda_usb2 vdda_usb2 PWR
W14 vdda_usb3 vdda_usb3 PWR
P16 vdda_video vdda_video PWR
G18, H17, M8, M9, N8, P8, R8, T8, V21, V22, W17, W18 vdds18v vdds18v PWR
AA18, AA19, N21, P20, P21, W21, Y21 vdds18v_ddr1 vdds18v_ddr1 PWR
E3, E5, G4, G5, H8, H9 vddshv1 vddshv1 PWR
B6, D10, E10, H10, H11 vddshv2 vddshv2 PWR
B23, D16, D22, E16, E22, G15, H15, H16, H18, H19 vddshv3 vddshv3 PWR
C24 vddshv4 vddshv4 PWR
V12 vddshv5 vddshv5 PWR
AD5, AD7, AE7, AF5 vddshv6 vddshv6 PWR
AB6, AB7 vddshv7 vddshv7 PWR
W8, Y8 vddshv8 vddshv8 PWR
U10, W4, W5 vddshv9 vddshv9 PWR
N4, N5, P10, R10, R7, T4, T5 vddshv10 vddshv10 PWR
J8, K8 vddshv11 vddshv11 PWR
AA21, AA22, AB21, AB22, AB24, AB25, AC22, AD26, AG20, AG28, AH27, T24, T25, W16, W27 vdds_ddr1 vdds_ddr1 PWR
AA7, Y7 vdds_mlbp vdds_mlbp PWR
K10, K11, L10, L11, M10, M11 vdd_dsp vdd_dsp PWR
U11, U12, V10, V11, V14, W10, W11, W13 vdd_gpu vdd_gpu PWR
J13, K12, K13, L12, M12, M13 vdd_iva vdd_iva PWR
K17, K18, L15, L16, L17, L18, L19, M15, M16, M17, M18, N17, N18, P17, P18, R18 vdd_mpu vdd_mpu PWR
AB15 vdd_rtc vdd_rtc PWR
E1 vin2a_clk0 vin2a_clk0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_fld No 4 O
emu5 5 O
kbd_row0 9 I
eQEP1A_in 10 I
pr1_edio_data_in0 12 I
pr1_edio_data_out0 13 O
gpio3_28
gpmc_a27
gpmc_a17 		14 IO
Driver off 15 I
F2 vin2a_d0 vin2a_d0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d23 No 4 O
emu10 5 O
uart9_ctsn 7 I
spi4_d0 8 IO
kbd_row4 9 I
ehrpwm1B 10 O
pr1_uart0_rxd 11 I
pr1_edio_data_in5 12 I
pr1_edio_data_out5 13 O
gpio4_1 14 IO
Driver off 15 I
F3 vin2a_d1 vin2a_d1 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d22 No 4 O
emu11 5 O
uart9_rtsn 7 O
spi4_cs0 8 IO
kbd_row5 9 I
ehrpwm1_tripzone_input 10 IO
pr1_uart0_txd 11 O
pr1_edio_data_in6 12 I
pr1_edio_data_out6 13 O
gpio4_2 14 IO
Driver off 15 I
D1 vin2a_d2 vin2a_d2 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d21 No 4 O
emu12 5 O
uart10_rxd 8 I
kbd_row6 9 I
eCAP1_in_PWM1_out 10 IO
pr1_ecap0_ecap_capin_apwm_o 11 IO
pr1_edio_data_in7 12 I
pr1_edio_data_out7 13 O
gpio4_3 14 IO
Driver off 15 I
E2 vin2a_d3 vin2a_d3 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d20 No 4 O
emu13 5 O
uart10_txd 8 O
kbd_col0 9 O
ehrpwm1_synci 10 I
pr1_edc_latch0_in 11 I
pr1_pru1_gpi0 12 I
pr1_pru1_gpo0 13 O
gpio4_4 14 IO
Driver off 15 I
D2 vin2a_d4 vin2a_d4 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d19 No 4 O
emu14 5 O
uart10_ctsn 8 I
kbd_col1 9 O
ehrpwm1_synco 10 O
pr1_edc_sync0_out 11 O
pr1_pru1_gpi1 12 I
pr1_pru1_gpo1 13 O
gpio4_5 14 IO
Driver off 15 I
F4 vin2a_d5 vin2a_d5 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d18 No 4 O
emu15 5 O
uart10_rtsn 8 O
kbd_col2 9 O
eQEP2A_in 10 I
pr1_edio_sof 11 O
pr1_pru1_gpi2 12 I
pr1_pru1_gpo2 13 O
gpio4_6 14 IO
Driver off 15 I
C1 vin2a_d6 vin2a_d6 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d17 No 4 O
emu16 5 O
mii1_rxd1 8 I
kbd_col3 9 O
eQEP2B_in 10 I
pr1_mii_mt1_clk 11 I
pr1_pru1_gpi3 12 I
pr1_pru1_gpo3 13 O
gpio4_7 14 IO
Driver off 15 I
E4 vin2a_d7 vin2a_d7 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d16 No 4 O
emu17 5 O
mii1_rxd2 8 I
kbd_col4 9 O
eQEP2_index 10 IO
pr1_mii1_txen 11 O
pr1_pru1_gpi4 12 I
pr1_pru1_gpo4 13 O
gpio4_8 14 IO
Driver off 15 I
F5 vin2a_d8 vin2a_d8 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d15 No 4 O
emu18 5 O
mii1_rxd3 8 I
kbd_col5 9 O
eQEP2_strobe 10 IO
pr1_mii1_txd3 11 O
pr1_pru1_gpi5 12 I
pr1_pru1_gpo5 13 O
gpio4_9
gpmc_a26 		14 IO
Driver off 15 I
E6 vin2a_d9 vin2a_d9 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_d14 No 4 O
emu19 5 O
mii1_rxd0 8 I
kbd_col6 9 O
ehrpwm2A 10 O
pr1_mii1_txd2 11 O
pr1_pru1_gpi6 12 I
pr1_pru1_gpo6 13 O
gpio4_10
gpmc_a25 		14 IO
Driver off 15 I
D3 vin2a_d10 vin2a_d10 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
mdio_mclk 3 O
vout2_d13 No 4 O
kbd_col7 9 O
ehrpwm2B 10 O
pr1_mdio_mdclk 11 O
pr1_pru1_gpi7 12 I
pr1_pru1_gpo7 13 O
gpio4_11
gpmc_a24 		14 IO
Driver off 15 I
F6 vin2a_d11 vin2a_d11 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
mdio_d 3 IO
vout2_d12 No 4 O
kbd_row7 9 I
ehrpwm2_tripzone_input 10 IO
pr1_mdio_data 11 IO
pr1_pru1_gpi8 12 I
pr1_pru1_gpo8 13 O
gpio4_12
gpmc_a23 		14 IO
Driver off 15 I
D5 vin2a_d12 vin2a_d12 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txc 3 O
vout2_d11 No 4 O
mii1_rxclk 8 I
kbd_col8 9 O
eCAP2_in_PWM2_out 10 IO
pr1_mii1_txd1 11 O
pr1_pru1_gpi9 12 I
pr1_pru1_gpo9 13 O
gpio4_13 14 IO
Driver off 15 I
C2 vin2a_d13 vin2a_d13 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txctl 3 O
vout2_d10 No 4 O
mii1_rxdv 8 I
kbd_row8 9 I
eQEP3A_in 10 I
pr1_mii1_txd0 11 O
pr1_pru1_gpi10 12 I
pr1_pru1_gpo10 13 O
gpio4_14 14 IO
Driver off 15 I
C3 vin2a_d14 vin2a_d14 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txd3 3 O
vout2_d9 No 4 O
mii1_txclk 8 I
eQEP3B_in 10 I
pr1_mii_mr1_clk 11 I
pr1_pru1_gpi11 12 I
pr1_pru1_gpo11 13 O
gpio4_15 14 IO
Driver off 15 I
C4 vin2a_d15 vin2a_d15 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txd2 3 O
vout2_d8 No 4 O
mii1_txd0 8 O
eQEP3_index 10 IO
pr1_mii1_rxdv 11 I
pr1_pru1_gpi12 12 I
pr1_pru1_gpo12 13 O
gpio4_16 14 IO
Driver off 15 I
B2 vin2a_d16 vin2a_d16 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d7 2 I
rgmii1_txd1 3 O
vout2_d7 No 4 O
mii1_txd1 8 O
eQEP3_strobe 10 IO
pr1_mii1_rxd3 11 I
pr1_pru1_gpi13 12 I
pr1_pru1_gpo13 13 O
gpio4_24 14 IO
Driver off 15 I
D6 vin2a_d17 vin2a_d17 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d6 2 I
rgmii1_txd0 3 O
vout2_d6 No 4 O
mii1_txd2 8 O
ehrpwm3A 10 O
pr1_mii1_rxd2 11 I
pr1_pru1_gpi14 12 I
pr1_pru1_gpo14 13 O
gpio4_25 14 IO
Driver off 15 I
C5 vin2a_d18 vin2a_d18 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d5 2 I
rgmii1_rxc 3 I
vout2_d5 No 4 O
mii1_txd3 8 O
ehrpwm3B 10 O
pr1_mii1_rxd1 11 I
pr1_pru1_gpi15 12 I
pr1_pru1_gpo15 13 O
gpio4_26 14 IO
Driver off 15 I
A3 vin2a_d19 vin2a_d19 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d4 2 I
rgmii1_rxctl 3 I
vout2_d4 No 4 O
mii1_txer 8 O
ehrpwm3_tripzone_input 10 IO
pr1_mii1_rxd0 11 I
pr1_pru1_gpi16 12 I
pr1_pru1_gpo16 13 O
gpio4_27 14 IO
Driver off 15 I
B3 vin2a_d20 vin2a_d20 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d3 2 I
rgmii1_rxd3 3 I
vout2_d3 No 4 O
mii1_rxer 8 I
eCAP3_in_PWM3_out 10 IO
pr1_mii1_rxer 11 I
pr1_pru1_gpi17 12 I
pr1_pru1_gpo17 13 O
gpio4_28 14 IO
Driver off 15 I
B4 vin2a_d21 vin2a_d21 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d2 2 I
rgmii1_rxd2 3 I
vout2_d2 No 4 O
mii1_col 8 I
pr1_mii1_rxlink 11 I
pr1_pru1_gpi18 12 I
pr1_pru1_gpo18 13 O
gpio4_29 14 IO
Driver off 15 I
B5 vin2a_d22 vin2a_d22 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d1 2 I
rgmii1_rxd1 3 I
vout2_d1 No 4 O
mii1_crs 8 I
pr1_mii1_col 11 I
pr1_pru1_gpi19 12 I
pr1_pru1_gpo19 13 O
gpio4_30 14 IO
Driver off 15 I
A4 vin2a_d23 vin2a_d23 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_d0 2 I
rgmii1_rxd0 3 I
vout2_d0 No 4 O
mii1_txen 8 O
pr1_mii1_crs 11 I
pr1_pru1_gpi20 12 I
pr1_pru1_gpo20 13 O
gpio4_31 14 IO
Driver off 15 I
G2 vin2a_de0 vin2a_de0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2a_fld0 1 I
vin2b_fld1 2 I
vin2b_de1 3 I
vout2_de No 4 O
emu6 5 O
kbd_row1 9 I
eQEP1B_in 10 I
pr1_edio_data_in1 12 I
pr1_edio_data_out1 13 O
gpio3_29 14 IO
Driver off 15 I
H7 vin2a_fld0 vin2a_fld0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_clk1 2 I
vout2_clk No 4 O
emu7 5 O
eQEP1_index 10 IO
pr1_edio_data_in2 12 I
pr1_edio_data_out2 13 O
gpio3_30
gpmc_a27
gpmc_a18 		14 IO
Driver off 15 I
G1 vin2a_hsync0 vin2a_hsync0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_hsync1 3 I
vout2_hsync No 4 O
emu8 5 O
uart9_rxd 7 I
spi4_sclk 8 IO
kbd_row2 9 I
eQEP1_strobe 10 IO
pr1_uart0_cts_n 11 I
pr1_edio_data_in3 12 I
pr1_edio_data_out3 13 O
gpio3_31
gpmc_a27 		14 IO
Driver off 15 I
G6 vin2a_vsync0 vin2a_vsync0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_vsync1 3 I
vout2_vsync No 4 O
emu9 5 O
uart9_txd 7 O
spi4_d1 8 IO
kbd_row3 9 I
ehrpwm1A 10 O
pr1_uart0_rts_n 11 O
pr1_edio_data_in4 12 I
pr1_edio_data_out4 13 O
gpio4_0 14 IO
Driver off 15 I
D11 vout1_clk vout1_clk No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin2a_fld0
vin1a_fld0 		3 I
vin1a_fld0 4 I
spi3_cs0 8 IO
gpio4_19 14 IO
Driver off 15 I
F11 vout1_d0 vout1_d0 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart5_rxd 2 I
vin2a_d16
vin1a_d16 		3 I
vin1a_d16 4 I
spi3_cs2 8 IO
pr1_uart0_cts_n 10 I
pr2_pru1_gpi18 12 I
pr2_pru1_gpo18 13 O
gpio8_0 14 IO
Driver off 15 I
G10 vout1_d1 vout1_d1 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart5_txd 2 O
vin2a_d17
vin1a_d17 		3 I
vin1a_d17 4 I
pr1_uart0_rts_n 10 O
pr2_pru1_gpi19 12 I
pr2_pru1_gpo19 13 O
gpio8_1 14 IO
Driver off 15 I
F10 vout1_d2 vout1_d2 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu2 2 O
vin2a_d18
vin1a_d18 		3 I
vin1a_d18 4 I
obs0 5 O
obs16 6 O
obs_irq1 7 O
pr1_uart0_rxd 10 I
pr2_pru1_gpi20 12 I
pr2_pru1_gpo20 13 O
gpio8_2 14 IO
Driver off 15 I
G11 vout1_d3 vout1_d3 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu5 2 O
vin2a_d19
vin1a_d19 		3 I
vin1a_d19 4 I
obs1 5 O
obs17 6 O
obs_dmarq1 7 O
pr1_uart0_txd 10 O
pr2_pru0_gpi0 12 I
pr2_pru0_gpo0 13 O
gpio8_3 14 IO
Driver off 15 I
E9 vout1_d4 vout1_d4 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu6 2 O
vin2a_d20
vin1a_d20 		3 I
vin1a_d20 4 I
obs2 5 O
obs18 6 O
pr1_ecap0_ecap_capin_apwm_o 10 IO
pr2_pru0_gpi1 12 I
pr2_pru0_gpo1 13 O
gpio8_4 14 IO
Driver off 15 I
F9 vout1_d5 vout1_d5 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu7 2 O
vin2a_d21
vin1a_d21 		3 I
vin1a_d21 4 I
obs3 5 O
obs19 6 O
pr2_edc_latch0_in 10 I
pr2_pru0_gpi2 12 I
pr2_pru0_gpo2 13 O
gpio8_5 14 IO
Driver off 15 I
F8 vout1_d6 vout1_d6 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu8 2 O
vin2a_d22
vin1a_d22 		3 I
vin1a_d22 4 I
obs4 5 O
obs20 6 O
pr2_edc_latch1_in 10 I
pr2_pru0_gpi3 12 I
pr2_pru0_gpo3 13 O
gpio8_6 14 IO
Driver off 15 I
E7 vout1_d7 vout1_d7 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu9 2 O
vin2a_d23
vin1a_d23 		3 I
vin1a_d23 4 I
pr2_edc_sync0_out 10 O
pr2_pru0_gpi4 12 I
pr2_pru0_gpo4 13 O
gpio8_7 14 IO
Driver off 15 I
E8 vout1_d8 vout1_d8 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart6_rxd 2 I
vin2a_d8
vin1a_d8 		3 I
vin1a_d8 4 I
pr2_edc_sync1_out 10 O
pr2_pru0_gpi5 12 I
pr2_pru0_gpo5 13 O
gpio8_8 14 IO
Driver off 15 I
D9 vout1_d9 vout1_d9 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart6_txd 2 O
vin2a_d9
vin1a_d9 		3 I
vin1a_d9 4 I
pr2_edio_latch_in 10 I
pr2_pru0_gpi6 12 I
pr2_pru0_gpo6 13 O
gpio8_9 14 IO
Driver off 15 I
D7 vout1_d10 vout1_d10 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu3 2 O
vin2a_d10
vin1a_d10 		3 I
vin1a_d10 4 I
obs5 5 O
obs21 6 O
obs_irq2 7 O
pr2_edio_sof 10 O
pr2_pru0_gpi7 12 I
pr2_pru0_gpo7 13 O
gpio8_10 14 IO
Driver off 15 I
D8 vout1_d11 vout1_d11 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu10 2 O
vin2a_d11
vin1a_d11 		3 I
vin1a_d11 4 I
obs6 5 O
obs22 6 O
obs_dmarq2 7 O
pr2_uart0_cts_n 10 I
pr2_pru0_gpi8 12 I
pr2_pru0_gpo8 13 O
gpio8_11 14 IO
Driver off 15 I
A5 vout1_d12 vout1_d12 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu11 2 O
vin2a_d12
vin1a_d12 		3 I
vin1a_d12 4 I
obs7 5 O
obs23 6 O
pr2_uart0_rts_n 10 O
pr2_pru0_gpi9 12 I
pr2_pru0_gpo9 13 O
gpio8_12 14 IO
Driver off 15 I
C6 vout1_d13 vout1_d13 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu12 2 O
vin2a_d13
vin1a_d13 		3 I
vin1a_d13 4 I
obs8 5 O
obs24 6 O
pr2_uart0_rxd 10 I
pr2_pru0_gpi10 12 I
pr2_pru0_gpo10 13 O
gpio8_13 14 IO
Driver off 15 I
C8 vout1_d14 vout1_d14 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu13 2 O
vin2a_d14
vin1a_d14 		3 I
vin1a_d14 4 I
obs9 5 O
obs25 6 O
pr2_uart0_txd 10 O
pr2_pru0_gpi11 12 I
pr2_pru0_gpo11 13 O
gpio8_14 14 IO
Driver off 15 I
C7 vout1_d15 vout1_d15 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu14 2 O
vin2a_d15
vin1a_d15 		3 I
vin1a_d15 4 I
obs10 5 O
obs26 6 O
pr2_ecap0_ecap_capin_apwm_o 10 IO
pr2_pru0_gpi12 12 I
pr2_pru0_gpo12 13 O
gpio8_15 14 IO
Driver off 15 I
B7 vout1_d16 vout1_d16 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart7_rxd 2 I
vin2a_d0
vin1a_d0 		3 I
vin1a_d0 4 I
pr2_edio_data_in0 10 I
pr2_edio_data_out0 11 O
pr2_pru0_gpi13 12 I
pr2_pru0_gpo13 13 O
gpio8_16 14 IO
Driver off 15 I
B8 vout1_d17 vout1_d17 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
uart7_txd 2 O
vin2a_d1
vin1a_d1 		3 I
vin1a_d1 4 I
pr2_edio_data_in1 10 I
pr2_edio_data_out1 11 O
pr2_pru0_gpi14 12 I
pr2_pru0_gpo14 13 O
gpio8_17 14 IO
Driver off 15 I
A7 vout1_d18 vout1_d18 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu4 2 O
vin2a_d2
vin1a_d2 		3 I
vin1a_d2 4 I
obs11 5 O
obs27 6 O
pr2_edio_data_in2 10 I
pr2_edio_data_out2 11 O
pr2_pru0_gpi15 12 I
pr2_pru0_gpo15 13 O
gpio8_18 14 IO
Driver off 15 I
A8 vout1_d19 vout1_d19 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu15 2 O
vin2a_d3
vin1a_d3 		3 I
vin1a_d3 4 I
obs12 5 O
obs28 6 O
pr2_edio_data_in3 10 I
pr2_edio_data_out3 11 O
pr2_pru0_gpi16 12 I
pr2_pru0_gpo16 13 O
gpio8_19 14 IO
Driver off 15 I
C9 vout1_d20 vout1_d20 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu16 2 O
vin2a_d4
vin1a_d4 		3 I
vin1a_d4 4 I
obs13 5 O
obs29 6 O
pr2_edio_data_in4 10 I
pr2_edio_data_out4 11 O
pr2_pru0_gpi17 12 I
pr2_pru0_gpo17 13 O
gpio8_20 14 IO
Driver off 15 I
A9 vout1_d21 vout1_d21 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu17 2 O
vin2a_d5
vin1a_d5 		3 I
vin1a_d5 4 I
obs14 5 O
obs30 6 O
pr2_edio_data_in5 10 I
pr2_edio_data_out5 11 O
pr2_pru0_gpi18 12 I
pr2_pru0_gpo18 13 O
gpio8_21 14 IO
Driver off 15 I
B9 vout1_d22 vout1_d22 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu18 2 O
vin2a_d6
vin1a_d6 		3 I
vin1a_d6 4 I
obs15 5 O
obs31 6 O
pr2_edio_data_in6 10 I
pr2_edio_data_out6 11 O
pr2_pru0_gpi19 12 I
pr2_pru0_gpo19 13 O
gpio8_22 14 IO
Driver off 15 I
A10 vout1_d23 vout1_d23 No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
emu19 2 O
vin2a_d7
vin1a_d7 		3 I
vin1a_d7 4 I
spi3_cs3 8 IO
pr2_edio_data_in7 10 I
pr2_edio_data_out7 11 O
pr2_pru0_gpi20 12 I
pr2_pru0_gpo20 13 O
gpio8_23 14 IO
Driver off 15 I
B10 vout1_de vout1_de No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin2a_de0
vin1a_de0 		3 I
vin1a_de0 4 I
spi3_d1 8 IO
gpio4_20 14 IO
Driver off 15 I
B11 vout1_fld vout1_fld No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin2a_clk0
vin1a_clk0 		3 I
vin1a_clk0 4 I
spi3_cs1 8 IO
gpio4_21 14 IO
Driver off 15 I
C11 vout1_hsync vout1_hsync No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin2a_hsync0
vin1a_hsync0 		3 I
vin1a_hsync0 4 I
spi3_d0 8 IO
gpio4_22 14 IO
Driver off 15 I
E11 vout1_vsync vout1_vsync No 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
vin2a_vsync0
vin1a_vsync0 		3 I
vin1a_vsync0 4 I
spi3_sclk 8 IO
pr2_pru1_gpi17 12 I
pr2_pru1_gpo17 13 O
gpio4_23 14 IO
Driver off 15 I
A1, A14, A2, A23, A28, A6, AA14, AA15, AA20, AA8, AA9, AB14, AB20, AD1, AD24, AG1, AH1, AH2, AH20, AH28, B1, D13, D19, E13, E19, F1, F7, G7, G8, G9, H12, J12, J15, J28, K1, K15, K24, K25, K4, K5, L13, L14, M19, N14, N15, N19, N24, N25, P28, R1, R12, R13, R21, T10, T11, T12, T14, T15, T17, T18, T21, U14, U15, U17, U20, U21, V15, V17, W1, W15, W24, W25, W28 vss vss GND
AA10, AH8 vssa_csi vssa_csi GND
AD19, AE19 vssa_hdmi vssa_hdmi GND
AF15 vssa_osc0 vssa_osc0 GND
AC14 vssa_osc1 vssa_osc1 GND
AD13, AE13 vssa_pcie vssa_pcie GND
AE10 vssa_sata vssa_sata GND
AA11, AB11 vssa_usb vssa_usb GND
AD10 vssa_usb3 vssa_usb3 GND
R15 vssa_video vssa_video GND
AD17 Wakeup0 Wakeup0 0 I 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
dcan1_rx 1 I
gpio1_0
sys_nirq2 		14 I
Driver off 15 I
AC16 Wakeup3 Wakeup3 0 I 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD
sys_nirq1 1 I
gpio1_3
dcan2_rx 		14 I
Driver off 15 I
AE15 xi_osc0 xi_osc0 0 I 1.8 vdda_osc No LVCMOS Analog
AC15 xi_osc1 xi_osc1 0 I 1.8 vdda_osc No LVCMOS Analog
AD15 xo_osc0 xo_osc0 0 O 1.8 vdda_osc No LVCMOS Analog
AC13 xo_osc1 xo_osc1 0 A 1.8 vdda_osc No LVCMOS Analog
D18 xref_clk0 xref_clk0 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr8 1 IO
mcasp1_axr4 2 IO
mcasp1_ahclkx 3 O
mcasp5_ahclkx 4 O
vin1a_d0 7 I
hdq0 8 IO
clkout2 9 O
timer13 10 IO
pr2_mii1_col 11 I
pr2_pru1_gpi5 12 I
pr2_pru1_gpo5 13 O
gpio6_17 14 IO
Driver off 15 I
E17 xref_clk1 xref_clk1 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr9 1 IO
mcasp1_axr5 2 IO
mcasp2_ahclkx 3 O
mcasp6_ahclkx 4 O
vin1a_clk0 7 I
timer14 10 IO
pr2_mii1_crs 11 I
pr2_pru1_gpi6 12 I
pr2_pru1_gpo6 13 O
gpio6_18 14 IO
Driver off 15 I
B26 xref_clk2 xref_clk2 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr10 1 IO
mcasp1_axr6 2 IO
mcasp3_ahclkx 3 O
mcasp7_ahclkx 4 O
vout2_clk No 6 O
vin2a_clk0
vin1a_clk0 		8 I
timer15 10 IO
gpio6_19 14 IO
Driver off 15 I
C23 xref_clk3 xref_clk3 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr11 1 IO
mcasp1_axr7 2 IO
mcasp4_ahclkx 3 O
mcasp8_ahclkx 4 O
vout2_de No 6 O
hdq0 7 IO
vin2a_de0
vin1a_de0 		8 I
clkout3 9 O
timer16 10 IO
gpio6_20 14 IO
Driver off 15 I
  1. NA in this table stands for Not Applicable.
  2. For more information on recommended operating conditions, see Table 5-5, Recommended Operating Conditions.
  3. The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
  4. The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the Device TRM.
  5. IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V).
  6. Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.
    For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification.
  7. This function will not be supported on some pin-compatible roadmap devices. Pin compatibility can be maintained in the future by not using these GPIO signals.
  8. In PUx / PDy, x and y = 60 to 200 μA.
    The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.
  9. The internal pull resistors for balls K7, M7, J5, K6, J4, J6, H4, H5 are permanently disabled when sysboot15 is set to 0 as described in the section Sysboot Configuration of the Device TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 1. If gpmc boot mode is used with SYSBOOT15=0 (not recommended) then external pull-downs should be implemented to keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot.