JAJSC85G March   2016  – May 2018 AM5716 , AM5718

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2 改訂履歴
  3. 3 Device Comparison
    1. 3.1 Device Comparison Table
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.4.5  External Memory Interface (EMIF)
      6. 4.4.6  General-Purpose Memory Controller (GPMC)
      7. 4.4.7  Timers
      8. 4.4.8  Inter-Integrated Circuit Interface (I2C)
      9. 4.4.9  HDQ / 1-Wire Interface (HDQ1W)
      10. 4.4.10 Universal Asynchronous Receiver Transmitter (UART)
      11. 4.4.11 Multichannel Serial Peripheral Interface (McSPI)
      12. 4.4.12 Quad Serial Peripheral Interface (QSPI)
      13. 4.4.13 Multichannel Audio Serial Port (McASP)
      14. 4.4.14 Universal Serial Bus (USB)
      15. 4.4.15 SATA
      16. 4.4.16 Peripheral Component Interconnect Express (PCIe)
      17. 4.4.17 Controller Area Network Interface (DCAN)
      18. 4.4.18 Ethernet Interface (GMAC_SW)
      19. 4.4.19 Media Local Bus (MLB) Interface
      20. 4.4.20 eMMC/SD/SDIO
      21. 4.4.21 General-Purpose Interface (GPIO)
      22. 4.4.22 Keyboard controller (KBD)
      23. 4.4.23 Pulse Width Modulation (PWM) Interface
      24. 4.4.24 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      25. 4.4.25 Test Interfaces
      26. 4.4.26 System and Miscellaneous
        1. 4.4.26.1 Sysboot
        2. 4.4.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.26.3 Real-Time Clock (RTC) Interface
        4. 4.4.26.4 System Direct Memory Access (SDMA)
        5. 4.4.26.5 Interrupt Controllers (INTC)
        6. 4.4.26.6 Observability
      27. 4.4.27 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hours (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  LVCMOS CSI2 DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 SERDES DC Electrical Characteristics
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
        3. 6.1.4.3 RC On-die Oscillator Clock
    2. 6.2 DPLLs, DLLs Specifications
      1. 6.2.1 DPLL Characteristics
      2. 6.2.2 DLL Characteristics
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem - Video Output Ports
    8. 7.8  Display Subsystem - High-Definition Multimedia Interface (HDMI)
    9. 7.9  Camera Serial Interface 2 CAL bridge (CSI2)
      1. 7.9.1 CSI-2 MIPI D-PHY
    10. 7.10 External Memory Interface (EMIF)
    11. 7.11 General-Purpose Memory Controller (GPMC)
      1. 7.11.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.11.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.11.3 GPMC/NAND Flash Interface Asynchronous Timing
    12. 7.12 Timers
    13. 7.13 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-33 Timing Requirements for I2C Input Timings
      2. Table 7-34 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-35 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    14. 7.14 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.14.1 HDQ / 1-Wire - HDQ Mode
      2. 7.14.2 HDQ/1-Wire-1-Wire Mode
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-40 Timing Requirements for UART
      2. Table 7-41 Switching Characteristics Over Recommended Operating Conditions for UART
    16. 7.16 Multichannel Serial Peripheral Interface (McSPI)
    17. 7.17 Quad Serial Peripheral Interface (QSPI)
    18. 7.18 Multichannel Audio Serial Port (McASP)
      1. Table 7-48 Timing Requirements for McASP1
      2. Table 7-49 Timing Requirements for McASP2
      3. Table 7-50 Timing Requirements for McASP3/4/5/6/7/8
    19. 7.19 Universal Serial Bus (USB)
      1. 7.19.1 USB1 DRD PHY
      2. 7.19.2 USB2 PHY
    20. 7.20 Serial Advanced Technology Attachment (SATA)
    21. 7.21 Peripheral Component Interconnect Express (PCIe)
    22. 7.22 Controller Area Network Interface (DCAN)
      1. Table 7-65 Timing Requirements for DCANx Receive
      2. Table 7-66 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    23. 7.23 Ethernet Interface (GMAC_SW)
      1. 7.23.1 GMAC MII Timings
        1. Table 7-67 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-68 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-69 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-70 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.23.2 GMAC MDIO Interface Timings
      3. 7.23.3 GMAC RMII Timings
        1. Table 7-75 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-76 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-77 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-78 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.23.4 GMAC RGMII Timings
        1. Table 7-82 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-83 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-84 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-85 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    24. 7.24 eMMC/SD/SDIO
      1. 7.24.1 MMC1-SD Card Interface
        1. 7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3 SDR12, 4-bit data, half-cycle
        4. 7.24.1.4 SDR25, 4-bit data, half-cycle
        5. 7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7 UHS-I DDR50, 4-bit data
      2. 7.24.2 MMC2 - eMMC
        1. 7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3 High-speed HS200 JEDS84, 8-bit data, half cycle
        4. 7.24.2.4 High-speed JC64 DDR, 8-bit data
          1. Table 7-110 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
      3. 7.24.3 MMC3 and MMC4-SDIO/SD
        1. 7.24.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2 MMC3 and MMC4, SD High Speed
        3. 7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25 General-Purpose Interface (GPIO)
    26. 7.26 PRU-ICSS Interfaces
      1. 7.26.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. 7.26.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
          1. Table 7-132 PRU-ICSS PRU Timing Requirements - Direct Input Mode
          2. Table 7-133 PRU-ICSS PRU Switching Requirements - Direct Output Mode
        2. 7.26.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
          1. Table 7-134 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
        3. 7.26.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
          1. Table 7-135 PRU-ICSS PRU Timing Requirements - Shift In Mode
          2. Table 7-136 PRU-ICSS PRU Switching Requirements - Shift Out Mode
        4. 7.26.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
          1. Table 7-137 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
          2. Table 7-138 PRU-ICSS PRU Timing Requirements - EnDAT Mode
          3. Table 7-139 PRU-ICSS PRU Switching Requirements - EnDAT Mode
      2. 7.26.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. 7.26.2.1 PRU-ICSS ECAT Electrical Data and Timing
          1. Table 7-140 PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
          2. Table 7-141 PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
          3. Table 7-142 PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
          4. Table 7-143 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
          5. Table 7-144 PRU-ICSS ECAT Switching Requirements - Digital IOs
      3. 7.26.3 PRU-ICSS MII_RT and Switch
        1. 7.26.3.1 PRU-ICSS MDIO Electrical Data and Timing
          1. Table 7-145 PRU-ICSS MDIO Timing Requirements - MDIO_DATA
          2. Table 7-146 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
          3. Table 7-147 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
        2. 7.26.3.2 PRU-ICSS MII_RT Electrical Data and Timing
          1. Table 7-148 PRU-ICSS MII_RT Timing Requirements - MII[x]_RXCLK
          2. Table 7-149 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
          3. Table 7-150 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
          4. Table 7-151 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
      4. 7.26.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
        1. Table 7-152 Timing Requirements for PRU-ICSS UART Receive
        2. Table 7-153 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      5. 7.26.5 PRU-ICSS Manual Functional Mapping
    27. 7.27 System and Miscellaneous interfaces
    28. 7.28 Test Interfaces
      1. 7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1 JTAG Electrical Data/Timing
          1. Table 7-173 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-174 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-175 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-176 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.28.2 Trace Port Interface Unit (TPIU)
        1. 7.28.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Power Supply Mapping
    2. 8.2 DDR3 Board Design and Layout Guidelines
      1. 8.2.1 DDR3 General Board Layout Guidelines
      2. 8.2.2 DDR3 Board Design and Layout Guidelines
        1. 8.2.2.1  Board Designs
        2. 8.2.2.2  DDR3 EMIF
        3. 8.2.2.3  DDR3 Device Combinations
        4. 8.2.2.4  DDR3 Interface Schematic
          1. 8.2.2.4.1 32-Bit DDR3 Interface
          2. 8.2.2.4.2 16-Bit DDR3 Interface
        5. 8.2.2.5  Compatible JEDEC DDR3 Devices
        6. 8.2.2.6  PCB Stackup
        7. 8.2.2.7  Placement
        8. 8.2.2.8  DDR3 Keepout Region
        9. 8.2.2.9  Bulk Bypass Capacitors
        10. 8.2.2.10 High-Speed Bypass Capacitors
          1. 8.2.2.10.1 Return Current Bypass Capacitors
        11. 8.2.2.11 Net Classes
        12. 8.2.2.12 DDR3 Signal Termination
        13. 8.2.2.13 VREF_DDR Routing
        14. 8.2.2.14 VTT
        15. 8.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.2.2.15.1 Four DDR3 Devices
            1. 8.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.2.2.15.2 Two DDR3 Devices
            1. 8.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.2.2.15.3 One DDR3 Device
            1. 8.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.2.2.16 Data Topologies and Routing Definition
          1. 8.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.2.2.17 Routing Specification
          1. 8.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.2.2.17.2 DQS and DQ Routing Specification
    3. 8.3 High Speed Differential Signal Routing Guidance
    4. 8.4 Power Distribution Network Implementation Guidance
    5. 8.5 Thermal Solution Guidance
    6. 8.6 Single-Ended Interfaces
      1. 8.6.1 General Routing Guidelines
      2. 8.6.2 QSPI Board Design and Layout Guidelines
    7. 8.7 LJCB_REFN/P Connections
    8. 8.8 Clock Routing Guidelines
      1. 8.8.1 32-kHz Oscillator Routing
      2. 8.8.2 Oscillator Ground Connection
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Related Links
    6. 9.6 Community Resources
    7. 9.7 Trademarks
    8. 9.8 静電気放電に関する注意事項
    9. 9.9 Glossary
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.26.5 PRU-ICSS Manual Functional Mapping

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS1 PRU1 Direct Input mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-158Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode for a definition of the Manual modes.

Table 7-158 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-158 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode

BALL BALL NAME PR1_PRU1_DIR_IN_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
D3 vin2a_d10 0 800 CFG_VIN2A_D10_IN pr1_pru1_gpi7
F6 vin2a_d11 0 0 CFG_VIN2A_D11_IN pr1_pru1_gpi8
D5 vin2a_d12 0 200 CFG_VIN2A_D12_IN pr1_pru1_gpi9
C2 vin2a_d13 0 0 CFG_VIN2A_D13_IN pr1_pru1_gpi10
C3 vin2a_d14 0 0 CFG_VIN2A_D14_IN pr1_pru1_gpi11
C4 vin2a_d15 0 400 CFG_VIN2A_D15_IN pr1_pru1_gpi12
B2 vin2a_d16 0 300 CFG_VIN2A_D16_IN pr1_pru1_gpi13
D6 vin2a_d17 0 400 CFG_VIN2A_D17_IN pr1_pru1_gpi14
C5 vin2a_d18 0 900 CFG_VIN2A_D18_IN pr1_pru1_gpi15
A3 vin2a_d19 0 1500 CFG_VIN2A_D19_IN pr1_pru1_gpi16
B3 vin2a_d20 0 100 CFG_VIN2A_D20_IN pr1_pru1_gpi17
B4 vin2a_d21 0 500 CFG_VIN2A_D21_IN pr1_pru1_gpi18
B5 vin2a_d22 0 500 CFG_VIN2A_D22_IN pr1_pru1_gpi19
A4 vin2a_d23 0 600 CFG_VIN2A_D23_IN pr1_pru1_gpi20
E2 vin2a_d3 0 900 CFG_VIN2A_D3_IN pr1_pru1_gpi0
D2 vin2a_d4 0 100 CFG_VIN2A_D4_IN pr1_pru1_gpi1
F4 vin2a_d5 0 600 CFG_VIN2A_D5_IN pr1_pru1_gpi2
C1 vin2a_d6 0 200 CFG_VIN2A_D6_IN pr1_pru1_gpi3
E4 vin2a_d7 0 400 CFG_VIN2A_D7_IN pr1_pru1_gpi4
F5 vin2a_d8 0 500 CFG_VIN2A_D8_IN pr1_pru1_gpi5
E6 vin2a_d9 0 600 CFG_VIN2A_D9_IN pr1_pru1_gpi6

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS1 PRU1 Direct Output mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-159Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode for a definition of the Manual modes.

Table 7-159 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-159 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode

BALL BALL NAME PR1_PRU1_DIR_OUT_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
D3 vin2a_d10 0 1000 CFG_VIN2A_D10_OUT pr1_pru1_gpo7
F6 vin2a_d11 0 1300 CFG_VIN2A_D11_OUT pr1_pru1_gpo8
D5 vin2a_d12 0 2300 CFG_VIN2A_D12_OUT pr1_pru1_gpo9
C2 vin2a_d13 0 2200 CFG_VIN2A_D13_OUT pr1_pru1_gpo10
C3 vin2a_d14 0 1800 CFG_VIN2A_D14_OUT pr1_pru1_gpo11
C4 vin2a_d15 0 1800 CFG_VIN2A_D15_OUT pr1_pru1_gpo12
B2 vin2a_d16 0 1600 CFG_VIN2A_D16_OUT pr1_pru1_gpo13
D6 vin2a_d17 0 2000 CFG_VIN2A_D17_OUT pr1_pru1_gpo14
C5 vin2a_d18 0 700 CFG_VIN2A_D18_OUT pr1_pru1_gpo15
A3 vin2a_d19 0 700 CFG_VIN2A_D19_OUT pr1_pru1_gpo16
B3 vin2a_d20 0 500 CFG_VIN2A_D20_OUT pr1_pru1_gpo17
B4 vin2a_d21 0 400 CFG_VIN2A_D21_OUT pr1_pru1_gpo18
B5 vin2a_d22 0 0 CFG_VIN2A_D22_OUT pr1_pru1_gpo19
A4 vin2a_d23 0 400 CFG_VIN2A_D23_OUT pr1_pru1_gpo20
E2 vin2a_d3 0 2200 CFG_VIN2A_D3_OUT pr1_pru1_gpo0
D2 vin2a_d4 540 2800 CFG_VIN2A_D4_OUT pr1_pru1_gpo1
F4 vin2a_d5 0 400 CFG_VIN2A_D5_OUT pr1_pru1_gpo2
C1 vin2a_d6 0 1500 CFG_VIN2A_D6_OUT pr1_pru1_gpo3
E4 vin2a_d7 0 2200 CFG_VIN2A_D7_OUT pr1_pru1_gpo4
F5 vin2a_d8 0 2600 CFG_VIN2A_D8_OUT pr1_pru1_gpo5
E6 vin2a_d9 0 2300 CFG_VIN2A_D9_OUT pr1_pru1_gpo6

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS1 PRU1 Parallel Capture Mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-160Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture Mode for a definition of the Manual modes.

Table 7-160 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-160 Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture Mode

BALL BALL NAME PR1_PRU1_PAR_CAP_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
D3 vin2a_d10 1535 0 CFG_VIN2A_D10_IN pr1_pru1_gpi7
F6 vin2a_d11 1151 0 CFG_VIN2A_D11_IN pr1_pru1_gpi8
D5 vin2a_d12 1173 0 CFG_VIN2A_D12_IN pr1_pru1_gpi9
C2 vin2a_d13 970 0 CFG_VIN2A_D13_IN pr1_pru1_gpi10
C3 vin2a_d14 1196 0 CFG_VIN2A_D14_IN pr1_pru1_gpi11
C4 vin2a_d15 1286 0 CFG_VIN2A_D15_IN pr1_pru1_gpi12
B2 vin2a_d16 1354 0 CFG_VIN2A_D16_IN pr1_pru1_gpi13
D6 vin2a_d17 1331 0 CFG_VIN2A_D17_IN pr1_pru1_gpi14
C5 vin2a_d18 2097 0 CFG_VIN2A_D18_IN pr1_pru1_gpi15
A3 vin2a_d19 0 453 CFG_VIN2A_D19_IN pr1_pru1_gpi16
E2 vin2a_d3 1566 0 CFG_VIN2A_D3_IN pr1_pru1_gpi0
D2 vin2a_d4 1012 0 CFG_VIN2A_D4_IN pr1_pru1_gpi1
F4 vin2a_d5 1337 0 CFG_VIN2A_D5_IN pr1_pru1_gpi2
C1 vin2a_d6 1130 0 CFG_VIN2A_D6_IN pr1_pru1_gpi3
E4 vin2a_d7 1202 0 CFG_VIN2A_D7_IN pr1_pru1_gpi4
F5 vin2a_d8 1395 0 CFG_VIN2A_D8_IN pr1_pru1_gpi5
E6 vin2a_d9 1338 0 CFG_VIN2A_D9_IN pr1_pru1_gpi6

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET1 Direct Input mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-161Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Input mode for a definition of the Manual modes.

Table 7-161 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-161 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Input mode

BALL BALL NAME PR2_PRU0_DIR_IN_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
D7 vout1_d10 0 0 CFG_VOUT1_D10_IN pr2_pru0_gpi7
D8 vout1_d11 0 0 CFG_VOUT1_D11_IN pr2_pru0_gpi8
A5 vout1_d12 0 0 CFG_VOUT1_D12_IN pr2_pru0_gpi9
C6 vout1_d13 0 0 CFG_VOUT1_D13_IN pr2_pru0_gpi10
C8 vout1_d14 0 0 CFG_VOUT1_D14_IN pr2_pru0_gpi11
C7 vout1_d15 0 0 CFG_VOUT1_D15_IN pr2_pru0_gpi12
B7 vout1_d16 0 0 CFG_VOUT1_D16_IN pr2_pru0_gpi13
B8 vout1_d17 0 0 CFG_VOUT1_D17_IN pr2_pru0_gpi14
A7 vout1_d18 0 0 CFG_VOUT1_D18_IN pr2_pru0_gpi15
A8 vout1_d19 0 0 CFG_VOUT1_D19_IN pr2_pru0_gpi16
C9 vout1_d20 0 0 CFG_VOUT1_D20_IN pr2_pru0_gpi17
A9 vout1_d21 0 0 CFG_VOUT1_D21_IN pr2_pru0_gpi18
B9 vout1_d22 0 0 CFG_VOUT1_D22_IN pr2_pru0_gpi19
A10 vout1_d23 0 0 CFG_VOUT1_D23_IN pr2_pru0_gpi20
G11 vout1_d3 0 0 CFG_VOUT1_D3_IN pr2_pru0_gpi0
E9 vout1_d4 0 0 CFG_VOUT1_D4_IN pr2_pru0_gpi1
F9 vout1_d5 0 0 CFG_VOUT1_D5_IN pr2_pru0_gpi2
F8 vout1_d6 0 0 CFG_VOUT1_D6_IN pr2_pru0_gpi3
E7 vout1_d7 0 0 CFG_VOUT1_D7_IN pr2_pru0_gpi4
E8 vout1_d8 0 0 CFG_VOUT1_D8_IN pr2_pru0_gpi5
D9 vout1_d9 0 0 CFG_VOUT1_D9_IN pr2_pru0_gpi6

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct Input mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-162Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode for a definition of the Manual modes.

Table 7-162 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-162 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode

BALL BALL NAME PR2_PRU0_DIR_IN_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
AC5 gpio6_10 1000 3300 CFG_GPIO6_10_IN pr2_pru0_gpi0
AB4 gpio6_11 1000 3400 CFG_GPIO6_11_IN pr2_pru0_gpi1
F14 mcasp1_axr15 0 1300 CFG_MCASP1_AXR15_IN pr2_pru0_gpi20
A19 mcasp2_aclkx 0 800 CFG_MCASP2_ACLKX_IN pr2_pru0_gpi18
C15 mcasp2_axr2 0 1900 CFG_MCASP2_AXR2_IN pr2_pru0_gpi16
A16 mcasp2_axr3 0 1400 CFG_MCASP2_AXR3_IN pr2_pru0_gpi17
A18 mcasp2_fsx 0 1400 CFG_MCASP2_FSX_IN pr2_pru0_gpi19
B19 mcasp3_axr0 0 1400 CFG_MCASP3_AXR0_IN pr2_pru0_gpi14
C17 mcasp3_axr1 0 1000 CFG_MCASP3_AXR1_IN pr2_pru0_gpi15
F15 mcasp3_fsx 0 1300 CFG_MCASP3_FSX_IN pr2_pru0_gpi13
AD4 mmc3_clk 1000 3700 CFG_MMC3_CLK_IN pr2_pru0_gpi2
AC4 mmc3_cmd 1000 3500 CFG_MMC3_CMD_IN pr2_pru0_gpi3
AC7 mmc3_dat0 1000 3500 CFG_MMC3_DAT0_IN pr2_pru0_gpi4
AC6 mmc3_dat1 1000 4000 CFG_MMC3_DAT1_IN pr2_pru0_gpi5
AC9 mmc3_dat2 1000 3300 CFG_MMC3_DAT2_IN pr2_pru0_gpi6
AC3 mmc3_dat3 1000 3900 CFG_MMC3_DAT3_IN pr2_pru0_gpi7
AC8 mmc3_dat4 1000 3500 CFG_MMC3_DAT4_IN pr2_pru0_gpi8
AD6 mmc3_dat5 1000 3600 CFG_MMC3_DAT5_IN pr2_pru0_gpi9
AB8 mmc3_dat6 1000 3500 CFG_MMC3_DAT6_IN pr2_pru0_gpi10
AB5 mmc3_dat7 1000 3100 CFG_MMC3_DAT7_IN pr2_pru0_gpi11
B18 mcasp3_aclkx 0 0 CFG_MCASP3_ACLKX_IN pr2_pru0_gpi12

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET1 Direct Output mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-163Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Output mode for a definition of the Manual modes.

Table 7-163 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-163 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Output mode

BALL BALL NAME PR2_PRU0_DIR_OUT_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
D7 vout1_d10 0 600 CFG_VOUT1_D10_OUT pr2_pru0_gpo7
D8 vout1_d11 0 700 CFG_VOUT1_D11_OUT pr2_pru0_gpo8
A5 vout1_d12 1200 200 CFG_VOUT1_D12_OUT pr2_pru0_gpo9
C6 vout1_d13 0 600 CFG_VOUT1_D13_OUT pr2_pru0_gpo10
C8 vout1_d14 200 300 CFG_VOUT1_D14_OUT pr2_pru0_gpo11
C7 vout1_d15 400 0 CFG_VOUT1_D15_OUT pr2_pru0_gpo12
B7 vout1_d16 0 0 CFG_VOUT1_D16_OUT pr2_pru0_gpo13
B8 vout1_d17 0 300 CFG_VOUT1_D17_OUT pr2_pru0_gpo14
A7 vout1_d18 120 300 CFG_VOUT1_D18_OUT pr2_pru0_gpo15
A8 vout1_d19 0 0 CFG_VOUT1_D19_OUT pr2_pru0_gpo16
C9 vout1_d20 250 200 CFG_VOUT1_D20_OUT pr2_pru0_gpo17
A9 vout1_d21 300 200 CFG_VOUT1_D21_OUT pr2_pru0_gpo18
B9 vout1_d22 0 0 CFG_VOUT1_D22_OUT pr2_pru0_gpo19
A10 vout1_d23 0 0 CFG_VOUT1_D23_OUT pr2_pru0_gpo20
G11 vout1_d3 920 0 CFG_VOUT1_D3_OUT pr2_pru0_gpo0
E9 vout1_d4 1500 300 CFG_VOUT1_D4_OUT pr2_pru0_gpo1
F9 vout1_d5 460 100 CFG_VOUT1_D5_OUT pr2_pru0_gpo2
F8 vout1_d6 300 300 CFG_VOUT1_D6_OUT pr2_pru0_gpo3
E7 vout1_d7 160 0 CFG_VOUT1_D7_OUT pr2_pru0_gpo4
E8 vout1_d8 0 0 CFG_VOUT1_D8_OUT pr2_pru0_gpo5
D9 vout1_d9 0 1200 CFG_VOUT1_D9_OUT pr2_pru0_gpo6

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct Output mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-164Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode for a definition of the Manual modes.

Table 7-164 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-164 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode

BALL BALL NAME PR2_PRU0_DIR_OUT_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
AC5 gpio6_10 1800 1900 CFG_GPIO6_10_OUT pr2_pru0_gpo0
AB4 gpio6_11 2500 2100 CFG_GPIO6_11_OUT pr2_pru0_gpo1
F14 mcasp1_axr15 0 400 CFG_MCASP1_AXR15_OUT pr2_pru0_gpo20
A19 mcasp2_aclkx 0 400 CFG_MCASP2_ACLKX_OUT pr2_pru0_gpo18
C15 mcasp2_axr2 0 500 CFG_MCASP2_AXR2_OUT pr2_pru0_gpo16
A16 mcasp2_axr3 0 500 CFG_MCASP2_AXR3_OUT pr2_pru0_gpo17
A18 mcasp2_fsx 0 0 CFG_MCASP2_FSX_OUT pr2_pru0_gpo19
B18 mcasp3_aclkx 0 500 CFG_MCASP3_ACLKX_OUT pr2_pru0_gpo12
B19 mcasp3_axr0 0 0 CFG_MCASP3_AXR0_OUT pr2_pru0_gpo14
C17 mcasp3_axr1 0 200 CFG_MCASP3_AXR1_OUT pr2_pru0_gpo15
F15 mcasp3_fsx 0 300 CFG_MCASP3_FSX_OUT pr2_pru0_gpo13
AD4 mmc3_clk 2100 2200 CFG_MMC3_CLK_OUT pr2_pru0_gpo2
AC4 mmc3_cmd 2300 2300 CFG_MMC3_CMD_OUT pr2_pru0_gpo3
AC7 mmc3_dat0 2000 1600 CFG_MMC3_DAT0_OUT pr2_pru0_gpo4
AC6 mmc3_dat1 2000 1700 CFG_MMC3_DAT1_OUT pr2_pru0_gpo5
AC9 mmc3_dat2 2050 2200 CFG_MMC3_DAT2_OUT pr2_pru0_gpo6
AC3 mmc3_dat3 2000 2000 CFG_MMC3_DAT3_OUT pr2_pru0_gpo7
AC8 mmc3_dat4 2150 2600 CFG_MMC3_DAT4_OUT pr2_pru0_gpo8
AD6 mmc3_dat5 2400 2600 CFG_MMC3_DAT5_OUT pr2_pru0_gpo9
AB8 mmc3_dat6 2200 2300 CFG_MMC3_DAT6_OUT pr2_pru0_gpo10
AB5 mmc3_dat7 1800 2400 CFG_MMC3_DAT7_OUT pr2_pru0_gpo11

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct Input mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-165Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode for a definition of the Manual modes.

Table 7-165 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-165 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode

BALL BALL NAME PR2_PRU1_DIR_IN_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
U3 RMII_MHZ_50_CLK 1400 1200 CFG_RMII_MHZ_50_CLK_IN pr2_pru1_gpi2
U4 mdio_d 1300 1600 CFG_MDIO_D_IN pr2_pru1_gpi1
V1 mdio_mclk 1400 800 CFG_MDIO_MCLK_IN pr2_pru1_gpi0
U5 rgmii0_rxc 1400 500 CFG_RGMII0_RXC_IN pr2_pru1_gpi11
V5 rgmii0_rxctl 1400 1800 CFG_RGMII0_RXCTL_IN pr2_pru1_gpi12
W2 rgmii0_rxd0 1400 1300 CFG_RGMII0_RXD0_IN pr2_pru1_gpi16
Y2 rgmii0_rxd1 1400 1650 CFG_RGMII0_RXD1_IN pr2_pru1_gpi15
V3 rgmii0_rxd2 1400 1400 CFG_RGMII0_RXD2_IN pr2_pru1_gpi14
V4 rgmii0_rxd3 1400 1650 CFG_RGMII0_RXD3_IN pr2_pru1_gpi13
W9 rgmii0_txc 1400 900 CFG_RGMII0_TXC_IN pr2_pru1_gpi5
V9 rgmii0_txctl 1400 1300 CFG_RGMII0_TXCTL_IN pr2_pru1_gpi6
U6 rgmii0_txd0 1400 900 CFG_RGMII0_TXD0_IN pr2_pru1_gpi10
V6 rgmii0_txd1 1300 1400 CFG_RGMII0_TXD1_IN pr2_pru1_gpi9
U7 rgmii0_txd2 1300 1100 CFG_RGMII0_TXD2_IN pr2_pru1_gpi8
V7 rgmii0_txd3 1300 1300 CFG_RGMII0_TXD3_IN pr2_pru1_gpi7
V2 uart3_rxd 1300 1000 CFG_UART3_RXD_IN pr2_pru1_gpi3
Y1 uart3_txd 1300 800 CFG_UART3_TXD_IN pr2_pru1_gpi4
E11 vout1_vsync 0 0 CFG_VOUT1_VSYNC_IN pr2_pru1_gpi17
F11 vout1_d0 0 0 CFG_VOUT1_D0_IN pr2_pru1_gpi18
G10 vout1_d1 0 0 CFG_VOUT1_D1_IN pr2_pru1_gpi19
F10 vout1_d2 0 0 CFG_VOUT1_D2_IN pr2_pru1_gpi20

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct Input mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-166Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode for a definition of the Manual modes.

Table 7-166 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-166 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode

BALL BALL NAME PR2_PRU1_DIR_IN_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
C14 mcasp1_aclkx 400 0 CFG_MCASP1_ACLKX_IN pr2_pru1_gpi7
G12 mcasp1_axr0 700 200 CFG_MCASP1_AXR0_IN pr2_pru1_gpi8
F12 mcasp1_axr1 600 300 CFG_MCASP1_AXR1_IN pr2_pru1_gpi9
B13 mcasp1_axr10 600 500 CFG_MCASP1_AXR10_IN pr2_pru1_gpi12
A12 mcasp1_axr11 700 500 CFG_MCASP1_AXR11_IN pr2_pru1_gpi13
E14 mcasp1_axr12 500 0 CFG_MCASP1_AXR12_IN pr2_pru1_gpi14
A13 mcasp1_axr13 600 200 CFG_MCASP1_AXR13_IN pr2_pru1_gpi15
G14 mcasp1_axr14 600 0 CFG_MCASP1_AXR14_IN pr2_pru1_gpi16
E11 vout1_vsync 0 0 CFG_VOUT1_VSYNC_IN pr2_pru1_gpi17
F11 vout1_d0 0 0 CFG_VOUT1_D0_IN pr2_pru1_gpi18
G10 vout1_d1 0 0 CFG_VOUT1_D1_IN pr2_pru1_gpi19
F10 vout1_d2 0 0 CFG_VOUT1_D2_IN pr2_pru1_gpi20
B12 mcasp1_axr8 800 0 CFG_MCASP1_AXR8_IN pr2_pru1_gpi10
A11 mcasp1_axr9 600 300 CFG_MCASP1_AXR9_IN pr2_pru1_gpi11
D17 mcasp4_axr1 500 0 CFG_MCASP4_AXR1_IN pr2_pru1_gpi0
AA3 mcasp5_aclkx 2100 1959 CFG_MCASP5_ACLKX_IN pr2_pru1_gpi1
AB3 mcasp5_axr0 2300 2000 CFG_MCASP5_AXR0_IN pr2_pru1_gpi3
AA4 mcasp5_axr1 2300 1800 CFG_MCASP5_AXR1_IN pr2_pru1_gpi4
AB9 mcasp5_fsx 2100 1780 CFG_MCASP5_FSX_IN pr2_pru1_gpi2
D18 xref_clk0 0 0 CFG_XREF_CLK0_IN pr2_pru1_gpi5
E17 xref_clk1 0 0 CFG_XREF_CLK1_IN pr2_pru1_gpi6

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct Output mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-167Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode for a definition of the Manual modes.

Table 7-167 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-167 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode

BALL BALL NAME PR2_PRU1_DIR_OUT_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
U3 RMII_MHZ_50_CLK 2306 100 CFG_RMII_MHZ_50_CLK_OUT pr2_pru1_gpo2
U4 mdio_d 1900 2000 CFG_MDIO_D_OUT pr2_pru1_gpo1
V1 mdio_mclk 2000 1100 CFG_MDIO_MCLK_OUT pr2_pru1_gpo0
U5 rgmii0_rxc 2000 1200 CFG_RGMII0_RXC_OUT pr2_pru1_gpo11
V5 rgmii0_rxctl 2000 1700 CFG_RGMII0_RXCTL_OUT pr2_pru1_gpo12
W2 rgmii0_rxd0 2000 1000 CFG_RGMII0_RXD0_OUT pr2_pru1_gpo16
Y2 rgmii0_rxd1 2200 1000 CFG_RGMII0_RXD1_OUT pr2_pru1_gpo15
V3 rgmii0_rxd2 2200 1300 CFG_RGMII0_RXD2_OUT pr2_pru1_gpo14
V4 rgmii0_rxd3 2250 1100 CFG_RGMII0_RXD3_OUT pr2_pru1_gpo13
W9 rgmii0_txc 2350 1000 CFG_RGMII0_TXC_OUT pr2_pru1_gpo5
V9 rgmii0_txctl 2000 1200 CFG_RGMII0_TXCTL_OUT pr2_pru1_gpo6
U6 rgmii0_txd0 2000 1500 CFG_RGMII0_TXD0_OUT pr2_pru1_gpo10
V6 rgmii0_txd1 1850 1000 CFG_RGMII0_TXD1_OUT pr2_pru1_gpo9
U7 rgmii0_txd2 2100 1100 CFG_RGMII0_TXD2_OUT pr2_pru1_gpo8
V7 rgmii0_txd3 2200 1000 CFG_RGMII0_TXD3_OUT pr2_pru1_gpo7
V2 uart3_rxd 2000 1600 CFG_UART3_RXD_OUT pr2_pru1_gpo3
Y1 uart3_txd 2000 1000 CFG_UART3_TXD_OUT pr2_pru1_gpo4
F11 vout1_d0 400 0 CFG_VOUT1_D0_OUT pr2_pru1_gpo18
G10 vout1_d1 0 0 CFG_VOUT1_D1_OUT pr2_pru1_gpo19
F10 vout1_d2 200 0 CFG_VOUT1_D2_OUT pr2_pru1_gpo20
E11 vout1_vsync 500 0 CFG_VOUT1_VSYNC_OUT pr2_pru1_gpo17

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct Output mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-168Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode for a definition of the Manual modes.

Table 7-168 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-168 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode

BALL BALL NAME PR2_PRU1_DIR_OUT_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
C14 mcasp1_aclkx 200 800 CFG_MCASP1_ACLKX_OUT pr2_pru1_gpo7
G12 mcasp1_axr0 200 1000 CFG_MCASP1_AXR0_OUT pr2_pru1_gpo8
F12 mcasp1_axr1 0 1110 CFG_MCASP1_AXR1_OUT pr2_pru1_gpo9
B13 mcasp1_axr10 0 2500 CFG_MCASP1_AXR10_OUT pr2_pru1_gpo12
A12 mcasp1_axr11 0 1900 CFG_MCASP1_AXR11_OUT pr2_pru1_gpo13
E14 mcasp1_axr12 0 2300 CFG_MCASP1_AXR12_OUT pr2_pru1_gpo14
A13 mcasp1_axr13 200 1200 CFG_MCASP1_AXR13_OUT pr2_pru1_gpo15
G14 mcasp1_axr14 200 1100 CFG_MCASP1_AXR14_OUT pr2_pru1_gpo16
E11 vout1_vsync 0 0 CFG_VOUT1_VSYNC_OUT pr2_pru1_gpo17
F11 vout1_d0 0 0 CFG_VOUT1_D0_OUT pr2_pru1_gpo18
G10 vout1_d1 0 0 CFG_VOUT1_D1_OUT pr2_pru1_gpo19
F10 vout1_d2 0 0 CFG_VOUT1_D2_OUT pr2_pru1_gpo20
B12 mcasp1_axr8 200 1600 CFG_MCASP1_AXR8_OUT pr2_pru1_gpo10
A11 mcasp1_axr9 0 1900 CFG_MCASP1_AXR9_OUT pr2_pru1_gpo11
D17 mcasp4_axr1 0 700 CFG_MCASP4_AXR1_OUT pr2_pru1_gpo0
AA3 mcasp5_aclkx 1400 4000 CFG_MCASP5_ACLKX_OUT pr2_pru1_gpo1
AB3 mcasp5_axr0 1500 3000 CFG_MCASP5_AXR0_OUT pr2_pru1_gpo3
AA4 mcasp5_axr1 1500 1900 CFG_MCASP5_AXR1_OUT pr2_pru1_gpo4
AB9 mcasp5_fsx 1300 2700 CFG_MCASP5_FSX_OUT pr2_pru1_gpo2
D18 xref_clk0 0 160 CFG_XREF_CLK0_OUT pr2_pru1_gpo5
E17 xref_clk1 0 0 CFG_XREF_CLK1_OUT pr2_pru1_gpo6

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET1 Parallel Capture Mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-169Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Parallel Capture Mode for a definition of the Manual modes.

Table 7-169 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-169 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Parallel Capture Mode

BALL BALL NAME PR2_PRU0_PAR_CAP_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
D7 vout1_d10 1994 0 CFG_VOUT1_D10_IN pr2_pru0_gpi7
D8 vout1_d11 1888 0 CFG_VOUT1_D11_IN pr2_pru0_gpi8
A5 vout1_d12 2024 0 CFG_VOUT1_D12_IN pr2_pru0_gpi9
C6 vout1_d13 1819 0 CFG_VOUT1_D13_IN pr2_pru0_gpi10
C8 vout1_d14 1971 0 CFG_VOUT1_D14_IN pr2_pru0_gpi11
C7 vout1_d15 2147 0 CFG_VOUT1_D15_IN pr2_pru0_gpi12
B7 vout1_d16 2016 0 CFG_VOUT1_D16_IN pr2_pru0_gpi13
B8 vout1_d17 1546 0 CFG_VOUT1_D17_IN pr2_pru0_gpi14
A7 vout1_d18 1557 0 CFG_VOUT1_D18_IN pr2_pru0_gpi15
A8 vout1_d19 0 0 CFG_VOUT1_D19_IN pr2_pru0_gpi16
G11 vout1_d3 1734 0 CFG_VOUT1_D3_IN pr2_pru0_gpi0
E9 vout1_d4 1861 0 CFG_VOUT1_D4_IN pr2_pru0_gpi1
F9 vout1_d5 1684 0 CFG_VOUT1_D5_IN pr2_pru0_gpi2
F8 vout1_d6 1547 0 CFG_VOUT1_D6_IN pr2_pru0_gpi3
E7 vout1_d7 1504 0 CFG_VOUT1_D7_IN pr2_pru0_gpi4
E8 vout1_d8 2238 0 CFG_VOUT1_D8_IN pr2_pru0_gpi5
D9 vout1_d9 2133 0 CFG_VOUT1_D9_IN pr2_pru0_gpi6

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-170Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode for a definition of the Manual modes.

Table 7-170 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-170 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode

BALL BALL NAME PR2_PRU0_PAR_CAP_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
AC5 gpio6_10 4125 481 CFG_GPIO6_10_IN pr2_pru0_gpi0
AB4 gpio6_11 3935 997 CFG_GPIO6_11_IN pr2_pru0_gpi1
C15 mcasp2_axr2 0 0 CFG_MCASP2_AXR2_IN pr2_pru0_gpi16
B18 mcasp3_aclkx 571 0 CFG_MCASP3_ACLKX_IN pr2_pru0_gpi12
B19 mcasp3_axr0 1570 0 CFG_MCASP3_AXR0_IN pr2_pru0_gpi14
C17 mcasp3_axr1 1405 0 CFG_MCASP3_AXR1_IN pr2_pru0_gpi15
F15 mcasp3_fsx 1946 0 CFG_MCASP3_FSX_IN pr2_pru0_gpi13
AD4 mmc3_clk 4093 1066 CFG_MMC3_CLK_IN pr2_pru0_gpi2
AC4 mmc3_cmd 4043 921 CFG_MMC3_CMD_IN pr2_pru0_gpi3
AC7 mmc3_dat0 4010 864 CFG_MMC3_DAT0_IN pr2_pru0_gpi4
AC6 mmc3_dat1 3817 1643 CFG_MMC3_DAT1_IN pr2_pru0_gpi5
AC9 mmc3_dat2 4040 673 CFG_MMC3_DAT2_IN pr2_pru0_gpi6
AC3 mmc3_dat3 3923 1478 CFG_MMC3_DAT3_IN pr2_pru0_gpi7
AC8 mmc3_dat4 4096 729 CFG_MMC3_DAT4_IN pr2_pru0_gpi8
AD6 mmc3_dat5 3926 1271 CFG_MMC3_DAT5_IN pr2_pru0_gpi9
AB8 mmc3_dat6 4004 929 CFG_MMC3_DAT6_IN pr2_pru0_gpi10
AB5 mmc3_dat7 3963 666 CFG_MMC3_DAT7_IN pr2_pru0_gpi11

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-171Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode for a definition of the Manual modes.

Table 7-171 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-171 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode

BALL BALL NAME PR2_PRU1_PAR_CAP_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
U3 RMII_MHZ_50_CLK 1717 0 CFG_RMII_MHZ_50_CLK_IN pr2_pru1_gpi2
U4 mdio_d 2088 0 CFG_MDIO_D_IN pr2_pru1_gpi1
V1 mdio_mclk 1321 0 CFG_MDIO_MCLK_IN pr2_pru1_gpi0
U5 rgmii0_rxc 1287 0 CFG_RGMII0_RXC_IN pr2_pru1_gpi11
V5 rgmii0_rxctl 2456 0 CFG_RGMII0_RXCTL_IN pr2_pru1_gpi12
W2 rgmii0_rxd0 0 0 CFG_RGMII0_RXD0_IN pr2_pru1_gpi16
Y2 rgmii0_rxd1 2157 0 CFG_RGMII0_RXD1_IN pr2_pru1_gpi15
V3 rgmii0_rxd2 2008 0 CFG_RGMII0_RXD2_IN pr2_pru1_gpi14
V4 rgmii0_rxd3 2271 0 CFG_RGMII0_RXD3_IN pr2_pru1_gpi13
W9 rgmii0_txc 1851 0 CFG_RGMII0_TXC_IN pr2_pru1_gpi5
V9 rgmii0_txctl 1875 0 CFG_RGMII0_TXCTL_IN pr2_pru1_gpi6
U6 rgmii0_txd0 1685 0 CFG_RGMII0_TXD0_IN pr2_pru1_gpi10
V6 rgmii0_txd1 2131 0 CFG_RGMII0_TXD1_IN pr2_pru1_gpi9
U7 rgmii0_txd2 1734 0 CFG_RGMII0_TXD2_IN pr2_pru1_gpi8
V7 rgmii0_txd3 1764 0 CFG_RGMII0_TXD3_IN pr2_pru1_gpi7
V2 uart3_rxd 1654 0 CFG_UART3_RXD_IN pr2_pru1_gpi3
Y1 uart3_txd 1242 0 CFG_UART3_TXD_IN pr2_pru1_gpi4

Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-172Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode for a definition of the Manual modes.

Table 7-172 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-172 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode

BALL BALL NAME PR2_PRU1_PAR_CAP_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
C14 mcasp1_aclkx 1928 0 CFG_MCASP1_ACLKX_IN pr2_pru1_gpi7
G12 mcasp1_axr0 2413 0 CFG_MCASP1_AXR0_IN pr2_pru1_gpi8
F12 mcasp1_axr1 2523 25 CFG_MCASP1_AXR1_IN pr2_pru1_gpi9
B13 mcasp1_axr10 2607 0 CFG_MCASP1_AXR10_IN pr2_pru1_gpi12
A12 mcasp1_axr11 2669 92 CFG_MCASP1_AXR11_IN pr2_pru1_gpi13
E14 mcasp1_axr12 2225 0 CFG_MCASP1_AXR12_IN pr2_pru1_gpi14
A13 mcasp1_axr13 2315 0 CFG_MCASP1_AXR13_IN pr2_pru1_gpi15
G14 mcasp1_axr14 0 0 CFG_MCASP1_AXR14_IN pr2_pru1_gpi16
B12 mcasp1_axr8 2201 0 CFG_MCASP1_AXR8_IN pr2_pru1_gpi10
A11 mcasp1_axr9 2293 278 CFG_MCASP1_AXR9_IN pr2_pru1_gpi11
D17 mcasp4_axr1 1759 0 CFG_MCASP4_AXR1_IN pr2_pru1_gpi0
AA3 mcasp5_aclkx 3732 1810 CFG_MCASP5_ACLKX_IN pr2_pru1_gpi1
AB3 mcasp5_axr0 3776 2255 CFG_MCASP5_AXR0_IN pr2_pru1_gpi3
AA4 mcasp5_axr1 3886 1923 CFG_MCASP5_AXR1_IN pr2_pru1_gpi4
AB9 mcasp5_fsx 3800 1449 CFG_MCASP5_FSX_IN pr2_pru1_gpi2
D18 xref_clk0 1375 21 CFG_XREF_CLK0_IN pr2_pru1_gpi5
E17 xref_clk1 1320 0 CFG_XREF_CLK1_IN pr2_pru1_gpi6