JAJSGC7F December 2015 – May 2019 AM5726 , AM5728 , AM5729
PRODUCTION DATA.
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Table 7-90 and Table 7-91 present Timing requirements and Switching characteristics for MMC1 - Default Speed in receiver and transmitter mode (see Figure 7-60 and Figure 7-61)
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
DSSD5 | tsu(cmdV-clkH) | Setup time, mmc1_cmd valid before mmc1_clk rising clock edge | 5.11 | ns | |
DSSD6 | th(clkH-cmdV) | Hold time, mmc1_cmd valid after mmc1_clk rising clock edge | 20.46 | ns | |
DSSD7 | tsu(dV-clkH) | Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge | 5.11 | ns | |
DSSD8 | th(clkH-dV) | Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge | 20.46 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
DSSD0 | fop(clk) | Operating frequency, mmc1_clk | 24 | MHz | |
DSSD1 | tw(clkH) | Pulse duration, mmc1_clk high | 0.5*P-0.185 | (1) | ns |
DSSD2 | tw(clkL) | Pulse duration, mmc1_clk low | 0.5*P-0.185 | (1) | ns |
DSSD3 | td(clkL-cmdV) | Delay time, mmc1_clk falling clock edge to mmc1_cmd transition | -14.93 | 14.93 | ns |
DSSD4 | td(clkL-dV) | Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition | -14.93 | 14.93 | ns |