JAJSGC7F December 2015 – May 2019 AM5726 , AM5728 , AM5729
PRODUCTION DATA.
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Table 7-98 and Table 7-99 present Timing requirements and Switching characteristics for MMC1 - SDR50 in receiver and transmitter mode (see Figure 7-68 and Figure 7-69).
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
SDR503 | tsu(cmdV-clkH) | Setup time, mmc1_cmd valid before mmc1_clk rising clock edge | 1.72 | ns | ||
SDR504 | th(clkH-cmdV) | Hold time, mmc1_cmd valid after mmc1_clk rising clock edge | 1.6 | ns | ||
SDR507 | tsu(dV-clkH) | Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge | 1.72 | ns | ||
SDR508 | th(clkH-dV) | Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge | Pad Loopback Clock | 1.6 | ns | |
Internal Loopback Clock | 1.6 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
SDR501 | fop(clk) | Operating frequency, mmc1_clk | 96 | MHz | |
SDR502H | tw(clkH) | Pulse duration, mmc1_clk high | 0.5*P-0.185 | (1) | ns |
SDR502L | tw(clkL) | Pulse duration, mmc1_clk low | 0.5*P-0.185 | (1) | ns |
SDR505 | td(clkL-cmdV) | Delay time, mmc1_clk falling clock edge to mmc1_cmd transition | -3.66 | 1.46 | ns |
SDR506 | td(clkL-dV) | Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition | -3.66 | 1.46 | ns |