JAJSGC7F December 2015 – May 2019 AM5726 , AM5728 , AM5729
PRODUCTION DATA.
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Figure 7-89, Figure 7-90, Table 7-131, and Table 7-132 present Timing requirements and Switching characteristics for MMC3 - SDIO High speed SDR50 in receiver and transmitter mode.
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
SDR503 | tsu(cmdV-clkH) | Setup time, mmc3_cmd valid before mmc3_clk rising clock edge | 1.48 | ns | |
SDR504 | th(clkH-cmdV) | Hold time, mmc3_cmd valid after mmc3_clk rising clock edge | 1.6 | ns | |
SDR507 | tsu(dV-clkH) | Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge | 1.48 | ns | |
SDR508 | th(clkH-dV) | Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge | 1.6 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
SDR501 | fop(clk) | Operating frequency, mmc3_clk | 64 | MHz | |
SDR502H | tw(clkH) | Pulse duration, mmc3_clk high | 0.5*P-0.270 | (1) | ns |
SDR502L | tw(clkL) | Pulse duration, mmc3_clk low | 0.5*P-0.270 | (1) | ns |
SDR505 | td(clkL-cmdV) | Delay time, mmc3_clk falling clock edge to mmc3_cmd transition | -3.66 | 1.46 | ns |
SDR506 | td(clkL-dV) | Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition | -3.66 | 1.46 | ns |
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to ensure some IO timings for MMC3. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-133Manual Functions Mapping for MMC3 for a definition of the Manual modes.
Table 7-133 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | MMC3_MANUAL1 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 0 | |||
AD4 | mmc3_clk | 0 | 386 | CFG_MMC3_CLK_IN | mmc3_clk |
AD4 | mmc3_clk | 605 | 0 | CFG_MMC3_CLK_OUT | mmc3_clk |
AC4 | mmc3_cmd | 0 | 0 | CFG_MMC3_CMD_IN | mmc3_cmd |
AC4 | mmc3_cmd | 0 | 0 | CFG_MMC3_CMD_OEN | mmc3_cmd |
AC4 | mmc3_cmd | 0 | 0 | CFG_MMC3_CMD_OUT | mmc3_cmd |
AC7 | mmc3_dat0 | 171 | 0 | CFG_MMC3_DAT0_IN | mmc3_dat0 |
AC7 | mmc3_dat0 | 0 | 0 | CFG_MMC3_DAT0_OEN | mmc3_dat0 |
AC7 | mmc3_dat0 | 0 | 0 | CFG_MMC3_DAT0_OUT | mmc3_dat0 |
AC6 | mmc3_dat1 | 221 | 0 | CFG_MMC3_DAT1_IN | mmc3_dat1 |
AC6 | mmc3_dat1 | 0 | 0 | CFG_MMC3_DAT1_OEN | mmc3_dat1 |
AC6 | mmc3_dat1 | 0 | 0 | CFG_MMC3_DAT1_OUT | mmc3_dat1 |
AC9 | mmc3_dat2 | 0 | 0 | CFG_MMC3_DAT2_IN | mmc3_dat2 |
AC9 | mmc3_dat2 | 0 | 0 | CFG_MMC3_DAT2_OEN | mmc3_dat2 |
AC9 | mmc3_dat2 | 0 | 0 | CFG_MMC3_DAT2_OUT | mmc3_dat2 |
AC3 | mmc3_dat3 | 474 | 0 | CFG_MMC3_DAT3_IN | mmc3_dat3 |
AC3 | mmc3_dat3 | 0 | 0 | CFG_MMC3_DAT3_OEN | mmc3_dat3 |
AC3 | mmc3_dat3 | 0 | 0 | CFG_MMC3_DAT3_OUT | mmc3_dat3 |
AC8 | mmc3_dat4 | 792 | 0 | CFG_MMC3_DAT4_IN | mmc3_dat4 |
AC8 | mmc3_dat4 | 0 | 0 | CFG_MMC3_DAT4_OEN | mmc3_dat4 |
AC8 | mmc3_dat4 | 0 | 0 | CFG_MMC3_DAT4_OUT | mmc3_dat4 |
AD6 | mmc3_dat5 | 782 | 0 | CFG_MMC3_DAT5_IN | mmc3_dat5 |
AD6 | mmc3_dat5 | 0 | 0 | CFG_MMC3_DAT5_OEN | mmc3_dat5 |
AD6 | mmc3_dat5 | 0 | 0 | CFG_MMC3_DAT5_OUT | mmc3_dat5 |
AB8 | mmc3_dat6 | 942 | 0 | CFG_MMC3_DAT6_IN | mmc3_dat6 |
AB8 | mmc3_dat6 | 0 | 0 | CFG_MMC3_DAT6_OEN | mmc3_dat6 |
AB8 | mmc3_dat6 | 0 | 0 | CFG_MMC3_DAT6_OUT | mmc3_dat6 |
AB5 | mmc3_dat7 | 636 | 0 | CFG_MMC3_DAT7_IN | mmc3_dat7 |
AB5 | mmc3_dat7 | 0 | 0 | CFG_MMC3_DAT7_OEN | mmc3_dat7 |
AB5 | mmc3_dat7 | 0 | 0 | CFG_MMC3_DAT7_OUT | mmc3_dat7 |
Manual IO Timings Modes must be used to ensure some IO timings for MMC4. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-134Manual Functions Mapping for MMC4 for a definition of the Manual modes.
Table 7-134 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | MMC4_MANUAL1 | MMC4_DS_MANUAL1 | CFG REGISTER | MUXMODE | ||
---|---|---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | A_DELAY (ps) | G_DELAY (ps) | 3 | |||
E25 | uart1_ctsn | 0 | 0 | 0 | 0 | CFG_UART1_CTSN_IN | mmc4_clk |
E25 | uart1_ctsn | 1147 | 0 | 0 | 0 | CFG_UART1_CTSN_OUT | mmc4_clk |
C27 | uart1_rtsn | 1834 | 0 | 307 | 0 | CFG_UART1_RTSN_IN | mmc4_cmd |
C27 | uart1_rtsn | 0 | 0 | 0 | 0 | CFG_UART1_RTSN_OEN | mmc4_cmd |
C27 | uart1_rtsn | 0 | 0 | 0 | 0 | CFG_UART1_RTSN_OUT | mmc4_cmd |
D27 | uart2_ctsn | 2165 | 0 | 785 | 0 | CFG_UART2_CTSN_IN | mmc4_dat2 |
D27 | uart2_ctsn | 0 | 0 | 0 | 0 | CFG_UART2_CTSN_OEN | mmc4_dat2 |
D27 | uart2_ctsn | 0 | 0 | 0 | 0 | CFG_UART2_CTSN_OUT | mmc4_dat2 |
C28 | uart2_rtsn | 1929 | 64 | 613 | 0 | CFG_UART2_RTSN_IN | mmc4_dat3 |
C28 | uart2_rtsn | 0 | 0 | 0 | 0 | CFG_UART2_RTSN_OEN | mmc4_dat3 |
C28 | uart2_rtsn | 0 | 0 | 0 | 0 | CFG_UART2_RTSN_OUT | mmc4_dat3 |
D28 | uart2_rxd | 1935 | 128 | 683 | 0 | CFG_UART2_RXD_IN | mmc4_dat0 |
D28 | uart2_rxd | 0 | 0 | 0 | 0 | CFG_UART2_RXD_OEN | mmc4_dat0 |
D28 | uart2_rxd | 0 | 0 | 0 | 0 | CFG_UART2_RXD_OUT | mmc4_dat0 |
D26 | uart2_txd | 2172 | 44 | 835 | 0 | CFG_UART2_TXD_IN | mmc4_dat1 |
D26 | uart2_txd | 0 | 0 | 0 | 0 | CFG_UART2_TXD_OEN | mmc4_dat1 |
D26 | uart2_txd | 0 | 0 | 0 | 0 | CFG_UART2_TXD_OUT | mmc4_dat1 |