JAJSGC7 データシート

JAJSGC7F December 2015 – May 2019 AM5726 , AM5728 , AM5729

PRODUCTION DATA.

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

ABC|760

サーマルパッド・メカニカル・データ

発注情報

8.2.2.17.2 DQS and DQ Routing Specification

Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL, a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.

NOTE

It is not required, nor is it recommended, to match the lengths across all bytes. Length matching is only required within each byte.

Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 8-28 shows this distance for four loads. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-13.

There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3

Figure 8-28 DQLM for Any Number of Allowed DDR3 Devices

Table 8-13 Data Routing Specification^⁽²⁾

NO.	PARAMETER	MIN	MAX	UNIT
DRS31	DB0 length		340	ps
DRS32	DB1 length		340	ps
DRS33	DB2 length		340	ps
DRS34	DB3 length		340	ps
DRS35	DBn skew^⁽³⁾		5	ps
DRS36	DQSn+ to DQSn- skew		1	ps
DRS37	DQSn to DBn skew^{⁽³⁾⁽⁴⁾}		5^⁽¹⁰⁾	ps
DRS38	Vias per trace		2^⁽¹⁾	vias
DRS39	Via count difference		0^⁽¹⁰⁾	vias
DRS310	Center-to-center DBn to other DDR3 trace spacing^⁽⁶⁾	4		w^⁽⁵⁾
DRS311	Center-to-center DBn to other DBn trace spacing^⁽⁷⁾	3		w^⁽⁵⁾
DRS312	DQSn center-to-center spacing ^⁽⁸⁾^⁽⁹⁾
DRS313	DQSn center-to-center spacing to other net	4		w^⁽⁵⁾

Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
External termination disallowed. Data termination should use built-in ODT functionality.
Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
Each DQS pair is length matched to its associated byte.
Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
Other DDR3 trace spacing means other DDR3 net classes not within the byte.
This applies to spacing within the net classes of a byte.
DQS pair spacing is set to ensure proper differential impedance.
The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, Zo.
Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.