SPRS982H December 2016 – December 2019 AM5746 , AM5748 , AM5749
PRODUCTION DATA.
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TI only supports board designs using DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 7-2 and Figure 7-1.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
RAM1 | tc(DDR_CLK) | Cycle time, DDR_CLK | 1.5 | 2.5(1) | ns |