SPRS982H December   2016  – December 2019 AM5746 , AM5748 , AM5749

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  EMIF
      5. 4.3.5  GPMC
      6. 4.3.6  Timer
      7. 4.3.7  I2C
      8. 4.3.8  HDQ1W
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 SATA
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 Test Interfaces
      25. 4.3.25 System and Miscellaneous
        1. 4.3.25.1 Sysboot
        2. 4.3.25.2 PRCM
        3. 4.3.25.3 RTCSS
        4. 4.3.25.4 SDMA
        5. 4.3.25.5 INTC
        6. 4.3.25.6 Observability
        7. 4.3.25.7 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH) Limits
      1. Table 5-1 Power-On Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-7  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-8  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-9  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-11 LVCMOS OSC Buffers DC Electrical Characteristics
      6. Table 5-12 BC1833IHHV Buffers DC Electrical Characteristics
      7. Table 5-13 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-14 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      HDMIPHY DC Electrical Characteristics
      10. 5.7.2      USBPHY DC Electrical Characteristics
      11. 5.7.3      SATAPHY DC Electrical Characteristics
      12. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-15 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RTC Oscillator Input Clock
            1. 5.10.4.1.4.1 RTC Oscillator External Crystal
            2. 5.10.4.1.4.2 RTC Oscillator Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  I2C
          1. Table 5-65 Timing Requirements for I2C Input Timings
          2. Table 5-66 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-67 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        9. 5.10.6.9  HDQ1W
          1. 5.10.6.9.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.9.2 HDQ/1-Wire—1-Wire Mode
        10. 5.10.6.10 UART
          1. Table 5-72 Timing Requirements for UART
          2. Table 5-73 Switching Characteristics Over Recommended Operating Conditions for UART
        11. 5.10.6.11 McSPI
        12. 5.10.6.12 QSPI
        13. 5.10.6.13 McASP
          1. Table 5-80 Timing Requirements for McASP1
          2. Table 5-81 Timing Requirements for McASP2
          3. Table 5-82 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-83 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-84 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-85 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        14. 5.10.6.14 USB
          1. 5.10.6.14.1 USB1 DRD PHY
          2. 5.10.6.14.2 USB2 PHY
        15. 5.10.6.15 SATA
        16. 5.10.6.16 PCIe
        17. 5.10.6.17 CAN
          1. 5.10.6.17.1 DCAN
          2. 5.10.6.17.2 MCAN-FD
          3. Table 5-97  Timing Requirements for CANx Receive
          4. Table 5-98  Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        18. 5.10.6.18 GMAC_SW
          1. 5.10.6.18.1 GMAC MII Timings
            1. Table 5-99  Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-100 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-101 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-102 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.18.2 GMAC MDIO Interface Timings
          3. 5.10.6.18.3 GMAC RMII Timings
            1. Table 5-107 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-108 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-109 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.18.4 GMAC RGMII Timings
            1. Table 5-114 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-115 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-116 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-117 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        19. 5.10.6.19 eMMC/SD/SDIO
          1. 5.10.6.19.1 MMC1—SD Card Interface
            1. 5.10.6.19.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.19.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.19.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.19.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.19.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.19.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.19.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.19.2 MMC2 — eMMC
            1. 5.10.6.19.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.19.2.2 High Speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.19.2.3 High Speed HS200 JC64 SDR, 8-bit data, half cycle
            4. 5.10.6.19.2.4 High Speed JC64 DDR, 8-bit data
          3. 5.10.6.19.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.19.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.19.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.19.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.19.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.19.3.5 MMC3 SDIO High Speed UHS-I SDR50 Mode, Half Cycle
        20. 5.10.6.20 PRU-ICSS
          1. 5.10.6.20.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.20.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-167 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.20.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-168 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.20.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-169 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-170 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.20.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-171 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-172 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-173 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.20.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.20.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-175 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-176 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-177 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-178 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.20.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.20.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-179 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-180 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-181 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.20.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-182 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-183 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-184 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-185 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.20.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-186 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-187 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.20.5 PRU-ICSS IOSETs
          6. 5.10.6.20.6 PRU-ICSS Manual Functional Mapping
        21. 5.10.6.21 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-210 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-211 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-212 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-213 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 TPIU
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor Subsystems
      1. 6.2.1 MPU
      2. 6.2.2 DSP Subsystem
      3. 6.2.3 IPU
      4. 6.2.4 Interrupt Controller
      5. 6.2.5 VPE
    3. 6.3 Accelerators and Coprocessors
      1. 6.3.1 IVA
      2. 6.3.2 GPU
      3. 6.3.3 PRU-ICSS
      4. 6.3.4 EVE
    4. 6.4 Other Subsystems
      1. 6.4.1 Memory Subsystem
        1. 6.4.1.1 EMIF
        2. 6.4.1.2 GPMC
        3. 6.4.1.3 ELM
        4. 6.4.1.4 OCMC
        5. 6.4.1.5 Interprocessor Communication
          1. 6.4.1.5.1 Mailbox
          2. 6.4.1.5.2 Spinlock
      2. 6.4.2 EDMA
      3. 6.4.3 Peripherals
        1. 6.4.3.1  VIP
        2. 6.4.3.2  DSS
        3. 6.4.3.3  Timers
        4. 6.4.3.4  I2C
        5. 6.4.3.5  HDQ1W
        6. 6.4.3.6  UART
          1. 6.4.3.6.1 UART Features
          2. 6.4.3.6.2 IrDA Features
          3. 6.4.3.6.3 CIR Features
        7. 6.4.3.7  McSPI
        8. 6.4.3.8  QSPI
        9. 6.4.3.9  McASP
        10. 6.4.3.10 USB
        11. 6.4.3.11 SATA
        12. 6.4.3.12 PCIe
        13. 6.4.3.13 CAN
          1. 6.4.3.13.1 DCAN
          2. 6.4.3.13.2 MCAN-FD
        14. 6.4.3.14 GMAC_SW
        15. 6.4.3.15 eMMC/SD/SDIO
        16. 6.4.3.16 GPIO
        17. 6.4.3.17 ePWM
        18. 6.4.3.18 eCAP
        19. 6.4.3.19 eQEP
      4. 6.4.4 On-Chip Debug
    5. 6.5 Identification
      1. 6.5.1 Revision Identification
      2. 6.5.2 Die Identification
      3. 6.5.3 JTAG Identification
      4. 6.5.4 ROM Code Identification
    6. 6.6 Boot Modes
      1. 6.6.1 Boot Mode List
      2. 6.6.2 Boot Mode Pin Usage
        1. 6.6.2.1 GPMC Configuration for XIP/NAND
        2. 6.6.2.2 System Clock Speed Selection
        3. 6.6.2.3 QSPI Redundant SBL Images Offset
      3. 6.6.3 Boot Mode Selection
        1. 6.6.3.1 Booting Device Order Selection
  7. 7Applications, Implementation, and Layout
    1. 7.1 Power Supply Mapping
    2. 7.2 DDR3 Board Design and Layout Guidelines
      1. 7.2.1 DDR3 General Board Layout Guidelines
      2. 7.2.2 DDR3 Board Design and Layout Guidelines
        1. 7.2.2.1  Board Designs
        2. 7.2.2.2  DDR3 EMIFs
        3. 7.2.2.3  DDR3 Device Combinations
        4. 7.2.2.4  DDR3 Interface Schematic
          1. 7.2.2.4.1 32-Bit DDR3 Interface
          2. 7.2.2.4.2 16-Bit DDR3 Interface
        5. 7.2.2.5  Compatible JEDEC DDR3 Devices
        6. 7.2.2.6  PCB Stackup
        7. 7.2.2.7  Placement
        8. 7.2.2.8  DDR3 Keepout Region
        9. 7.2.2.9  Bulk Bypass Capacitors
        10. 7.2.2.10 High Speed Bypass Capacitors
          1. 7.2.2.10.1 Return Current Bypass Capacitors
        11. 7.2.2.11 Net Classes
        12. 7.2.2.12 DDR3 Signal Termination
        13. 7.2.2.13 VREF_DDR Routing
        14. 7.2.2.14 VTT
        15. 7.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.2.2.15.1 Four DDR3 Devices
            1. 7.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.2.2.15.2 Two DDR3 Devices
            1. 7.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.2.2.15.3 One DDR3 Device
            1. 7.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.2.2.16 Data Topologies and Routing Definition
          1. 7.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.2.2.17 Routing Specification
          1. 7.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.2.2.17.2 DQS and DQ Routing Specification
    3. 7.3 High Speed Differential Signal Routing Guidance
    4. 7.4 Power Distribution Network Implementation Guidance
    5. 7.5 Thermal Solution Guidance
    6. 7.6 Single-Ended Interfaces
      1. 7.6.1 General Routing Guidelines
      2. 7.6.2 QSPI Board Design and Layout Guidelines
    7. 7.7 LJCB_REFN/P Connections
    8. 7.8 Clock Routing Guidelines
      1. 7.8.1 32-kHz Oscillator Routing
      2. 7.8.2 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • ABZ|760
サーマルパッド・メカニカル・データ
発注情報

Power Supply Sequences

This section describes the power-up and power-down sequence required to ensure proper device operation. The power supply names described in this section comprise a superset of a family of compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to the Section 4.2, Pin Attributes of the Section 4, Terminal Configuration and Functions to determine which power supplies are applicable.

NOTE

RTC-only mode is not a supported feature.

Figure 5-5 and Figure 5-6 describe the device power sequencing when RTC-mode is NOT used.

AM5749 AM5748 AM5746 SPRS982_ELCH_04_ABZ.gifFigure 5-5 Power-Up Sequencing(2)

  1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
  2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
  3. If RTC-only mode is not used then the following combinations are approved:
    - vdda_rtc can be combined with vdds18v
    - vdd_rtc can be combined with vdd
    - vddshv5 can be combined with other 1.8 V or 3.3 V vddshvn rails.
    If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements. When using RTC mode timing:
    - vdda_rtc rises coincident with, or before, the 1.8 V interface supplies (such as vdds18v).
    - vdd_rtc rises coincident with vdd, or it may rise earlier. If rising earlier, it must rise after the 1.8 V interface supplies.
    - vddshv5 rises coincident with the other vddshvn rails (of the same voltage) or it can rise about the same time as the 1.8 V PHY supplies (such as vdd_usb1).
  4. vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
  5. vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
  6. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8 V only, then these rails can be combined with vdds18v.
  7. vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp after vdd.
  8. vdds and vdda rails must not be combined together, with the one exception of vdda_rtc when RTC-mode is not supported.
  9. Pulse duration: rtc_porz must remain low 1 ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
  10. The FUNC_32K_CLK source must be stable and at a valid frequency 1ms prior to deasserting rtc_porz high.
  11. porz must remain asserted low until all of the following conditions are met:
    • All device supply rails reach stable operational levels.
    • xi_osc0 is stable and at a valid frequency.
    • Minimum of 12P after both of the above conditions are met, where P = 1 / (SYS_CLK1/610), units in ns.
    resetn must be high prior to, or rise simultaneous with, porz but not before its power supply, vddshv3, rising.
  12. Setup time: sysboot[15:0] pins must be valid 2P(15) before porz is de-asserted high.
  13. Hold time: sysboot[15:0] pins must be valid 15P(15) after porz is de-asserted high.
  14. rstoutn will be asserted low when porz is low, and de-asserted following an internal 2ms delay. rstoutn is only valid after vddshv3 reaches an operational level. If used as a peripheral component reset, it should be AND gated with porz to avoid possible reset glitches during power up.
  15. P = 1 / (SYS_CLK1 / 610) µs, where SYS_CLK1 is in MHz.
  16. ddr1_vref0 / ddr2_vref0 may rise coincident with vdds_ddr1 / vdds_ddr2, respectively or at a later time. However, it must be valid before porz rising.
AM5749 AM5748 AM5746 SPRS982_ELCH_05_ABZ.gifFigure 5-6 Power-Down Sequencing(12)(14)
  1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
  2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
  3. xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
  4. If RTC-mode is not used then the following combinations are approved:
    - vdda_rtc can be combined with vdds18v
    - vdd_rtc can be combined with vdd
    - vddshv5 can be combined with other 1.8 V or 3.3 V vddshv* rails
    If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements. When using RTC mode timing:
    - vdda_rtc falls coincident with, or later than, the 1.8 V interface supplies (such as vdds18v).
    - vdd_rtc falls coincident with vdd, or it may fall later. If falling later, it must fall before, or coincident with, the 1.8 V interface supplies.
    - vddshv5 falls coincident with the other vddshvn rails (of the same voltage) or it can fall about the same time as the 1.8 V PHY supplies (such as vdd_usb1).
  5. vddshv* domains supplied by 3.3 V:
    • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after porz is asserted low.
    • must be in first group of supplies ramping down after porz has been asserted low for 100 µs min.
    • must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-7 “vdds18v versus vddshv* Discharge Relationship”.
  6. vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
  7. vddshv8 domain:
    • if SDIO operation is needed,
      • must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.
      • must be sourced from independent power resource that can provide dual voltage (3.3 V / 1.8 V) operation as required to be compliant to SDIO specification
    • if SDIO operation is not needed,
      • must be grouped and ramped down with other vddshv* domains as noted above.
  8. vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
  9. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8 V only, then these rails can be combined with vdds18v. vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8 V mode or in 3.3 V mode. If vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must ensure that the vddshv[1-7,9-11] rail is never higher than 2.0 V above the vdds18v rail.
  10. vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
  11. The 1.8 V vdda_* supplies can either ramp down at the earlier time period shown or can be delayed to ramp down after the core supplies coincident with the vdds18v supply as long as porz is asserted (low) during the power down sequence.
  12. The power down sequence shown is the most general case and is always valid. An accelerated power down sequence is also available but is only valid when porz is asserted (low). This accelerated power down sequence has been implemented in the companion PMIC that is recommended for use with this SoC. The accelerated sequence has porz go low first, then all 3.3 V supplies simultaneously second, core supplies, DDR supplies and DDR references simultaneously third and all 1.8 V supplies simultaneously last.
  13. ddr1_vref0 / ddr2_vref0 may fall coincident with vdds_ddr1 / vdds_ddr2, respectively or at a prior time but after porz is asserted low.
  14. Ramped Down is defined as reaching a voltage level of no more than 0.6 V.

Figure 5-7 describes the discharge relationship between vdds18v and vddshv* power supplies during power-down.

AM5749 AM5748 AM5746 SPRS85v_ELCH_06.gifFigure 5-7 vdds18v versus vddshv* Discharge Relationship
  1. Vdelta MAX = 2 V
  2. If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.