SPRS982H December   2016  – December 2019 AM5746 , AM5748 , AM5749

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  EMIF
      5. 4.3.5  GPMC
      6. 4.3.6  Timer
      7. 4.3.7  I2C
      8. 4.3.8  HDQ1W
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 SATA
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 Test Interfaces
      25. 4.3.25 System and Miscellaneous
        1. 4.3.25.1 Sysboot
        2. 4.3.25.2 PRCM
        3. 4.3.25.3 RTCSS
        4. 4.3.25.4 SDMA
        5. 4.3.25.5 INTC
        6. 4.3.25.6 Observability
        7. 4.3.25.7 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH) Limits
      1. Table 5-1 Power-On Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-7  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-8  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-9  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-11 LVCMOS OSC Buffers DC Electrical Characteristics
      6. Table 5-12 BC1833IHHV Buffers DC Electrical Characteristics
      7. Table 5-13 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-14 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      HDMIPHY DC Electrical Characteristics
      10. 5.7.2      USBPHY DC Electrical Characteristics
      11. 5.7.3      SATAPHY DC Electrical Characteristics
      12. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-15 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RTC Oscillator Input Clock
            1. 5.10.4.1.4.1 RTC Oscillator External Crystal
            2. 5.10.4.1.4.2 RTC Oscillator Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  I2C
          1. Table 5-65 Timing Requirements for I2C Input Timings
          2. Table 5-66 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-67 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        9. 5.10.6.9  HDQ1W
          1. 5.10.6.9.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.9.2 HDQ/1-Wire—1-Wire Mode
        10. 5.10.6.10 UART
          1. Table 5-72 Timing Requirements for UART
          2. Table 5-73 Switching Characteristics Over Recommended Operating Conditions for UART
        11. 5.10.6.11 McSPI
        12. 5.10.6.12 QSPI
        13. 5.10.6.13 McASP
          1. Table 5-80 Timing Requirements for McASP1
          2. Table 5-81 Timing Requirements for McASP2
          3. Table 5-82 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-83 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-84 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-85 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        14. 5.10.6.14 USB
          1. 5.10.6.14.1 USB1 DRD PHY
          2. 5.10.6.14.2 USB2 PHY
        15. 5.10.6.15 SATA
        16. 5.10.6.16 PCIe
        17. 5.10.6.17 CAN
          1. 5.10.6.17.1 DCAN
          2. 5.10.6.17.2 MCAN-FD
          3. Table 5-97  Timing Requirements for CANx Receive
          4. Table 5-98  Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        18. 5.10.6.18 GMAC_SW
          1. 5.10.6.18.1 GMAC MII Timings
            1. Table 5-99  Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-100 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-101 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-102 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.18.2 GMAC MDIO Interface Timings
          3. 5.10.6.18.3 GMAC RMII Timings
            1. Table 5-107 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-108 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-109 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.18.4 GMAC RGMII Timings
            1. Table 5-114 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-115 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-116 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-117 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        19. 5.10.6.19 eMMC/SD/SDIO
          1. 5.10.6.19.1 MMC1—SD Card Interface
            1. 5.10.6.19.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.19.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.19.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.19.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.19.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.19.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.19.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.19.2 MMC2 — eMMC
            1. 5.10.6.19.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.19.2.2 High Speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.19.2.3 High Speed HS200 JC64 SDR, 8-bit data, half cycle
            4. 5.10.6.19.2.4 High Speed JC64 DDR, 8-bit data
          3. 5.10.6.19.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.19.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.19.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.19.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.19.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.19.3.5 MMC3 SDIO High Speed UHS-I SDR50 Mode, Half Cycle
        20. 5.10.6.20 PRU-ICSS
          1. 5.10.6.20.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.20.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-167 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.20.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-168 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.20.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-169 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-170 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.20.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-171 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-172 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-173 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.20.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.20.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-175 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-176 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-177 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-178 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.20.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.20.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-179 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-180 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-181 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.20.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-182 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-183 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-184 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-185 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.20.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-186 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-187 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.20.5 PRU-ICSS IOSETs
          6. 5.10.6.20.6 PRU-ICSS Manual Functional Mapping
        21. 5.10.6.21 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-210 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-211 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-212 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-213 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 TPIU
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor Subsystems
      1. 6.2.1 MPU
      2. 6.2.2 DSP Subsystem
      3. 6.2.3 IPU
      4. 6.2.4 Interrupt Controller
      5. 6.2.5 VPE
    3. 6.3 Accelerators and Coprocessors
      1. 6.3.1 IVA
      2. 6.3.2 GPU
      3. 6.3.3 PRU-ICSS
      4. 6.3.4 EVE
    4. 6.4 Other Subsystems
      1. 6.4.1 Memory Subsystem
        1. 6.4.1.1 EMIF
        2. 6.4.1.2 GPMC
        3. 6.4.1.3 ELM
        4. 6.4.1.4 OCMC
        5. 6.4.1.5 Interprocessor Communication
          1. 6.4.1.5.1 Mailbox
          2. 6.4.1.5.2 Spinlock
      2. 6.4.2 EDMA
      3. 6.4.3 Peripherals
        1. 6.4.3.1  VIP
        2. 6.4.3.2  DSS
        3. 6.4.3.3  Timers
        4. 6.4.3.4  I2C
        5. 6.4.3.5  HDQ1W
        6. 6.4.3.6  UART
          1. 6.4.3.6.1 UART Features
          2. 6.4.3.6.2 IrDA Features
          3. 6.4.3.6.3 CIR Features
        7. 6.4.3.7  McSPI
        8. 6.4.3.8  QSPI
        9. 6.4.3.9  McASP
        10. 6.4.3.10 USB
        11. 6.4.3.11 SATA
        12. 6.4.3.12 PCIe
        13. 6.4.3.13 CAN
          1. 6.4.3.13.1 DCAN
          2. 6.4.3.13.2 MCAN-FD
        14. 6.4.3.14 GMAC_SW
        15. 6.4.3.15 eMMC/SD/SDIO
        16. 6.4.3.16 GPIO
        17. 6.4.3.17 ePWM
        18. 6.4.3.18 eCAP
        19. 6.4.3.19 eQEP
      4. 6.4.4 On-Chip Debug
    5. 6.5 Identification
      1. 6.5.1 Revision Identification
      2. 6.5.2 Die Identification
      3. 6.5.3 JTAG Identification
      4. 6.5.4 ROM Code Identification
    6. 6.6 Boot Modes
      1. 6.6.1 Boot Mode List
      2. 6.6.2 Boot Mode Pin Usage
        1. 6.6.2.1 GPMC Configuration for XIP/NAND
        2. 6.6.2.2 System Clock Speed Selection
        3. 6.6.2.3 QSPI Redundant SBL Images Offset
      3. 6.6.3 Boot Mode Selection
        1. 6.6.3.1 Booting Device Order Selection
  7. 7Applications, Implementation, and Layout
    1. 7.1 Power Supply Mapping
    2. 7.2 DDR3 Board Design and Layout Guidelines
      1. 7.2.1 DDR3 General Board Layout Guidelines
      2. 7.2.2 DDR3 Board Design and Layout Guidelines
        1. 7.2.2.1  Board Designs
        2. 7.2.2.2  DDR3 EMIFs
        3. 7.2.2.3  DDR3 Device Combinations
        4. 7.2.2.4  DDR3 Interface Schematic
          1. 7.2.2.4.1 32-Bit DDR3 Interface
          2. 7.2.2.4.2 16-Bit DDR3 Interface
        5. 7.2.2.5  Compatible JEDEC DDR3 Devices
        6. 7.2.2.6  PCB Stackup
        7. 7.2.2.7  Placement
        8. 7.2.2.8  DDR3 Keepout Region
        9. 7.2.2.9  Bulk Bypass Capacitors
        10. 7.2.2.10 High Speed Bypass Capacitors
          1. 7.2.2.10.1 Return Current Bypass Capacitors
        11. 7.2.2.11 Net Classes
        12. 7.2.2.12 DDR3 Signal Termination
        13. 7.2.2.13 VREF_DDR Routing
        14. 7.2.2.14 VTT
        15. 7.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.2.2.15.1 Four DDR3 Devices
            1. 7.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.2.2.15.2 Two DDR3 Devices
            1. 7.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.2.2.15.3 One DDR3 Device
            1. 7.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.2.2.16 Data Topologies and Routing Definition
          1. 7.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.2.2.17 Routing Specification
          1. 7.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.2.2.17.2 DQS and DQ Routing Specification
    3. 7.3 High Speed Differential Signal Routing Guidance
    4. 7.4 Power Distribution Network Implementation Guidance
    5. 7.5 Thermal Solution Guidance
    6. 7.6 Single-Ended Interfaces
      1. 7.6.1 General Routing Guidelines
      2. 7.6.2 QSPI Board Design and Layout Guidelines
    7. 7.7 LJCB_REFN/P Connections
    8. 7.8 Clock Routing Guidelines
      1. 7.8.1 32-kHz Oscillator Routing
      2. 7.8.2 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

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発注情報

5.10.6.20.5 PRU-ICSS IOSETs

In Table 5-188 and Table 5-189 are presented the specific groupings of signals (IOSET) for use with PRU-ICSS1 and PRU-ICSS2.

Table 5-188 PRU-ICSS1 IOSETs

SIGNALS IOSET1 IOSET2 IOSET3(1)(2) IOSET4(1)(2)
BALL MUX BALL MUX BALL MUX BALL MUX
PRU-ICSS1
pr1_pru1_gpi20 A4 12
pr1_pru1_gpi19 B5 12
pr1_pru1_gpi18 B4 12
pr1_pru1_gpi17 B3 12
pr1_pru1_gpi16 A3 12
pr1_pru1_gpi15 C5 12
pr1_pru1_gpi14 D6 12
pr1_pru1_gpi13 B2 12
pr1_pru1_gpi12 C4 12
pr1_pru1_gpi11 C3 12
pr1_pru1_gpi10 C2 12
pr1_pru1_gpo20 A4 13
pr1_pru1_gpo19 B5 13
pr1_pru1_gpo18 B4 13
pr1_pru1_gpo17 B3 13
pr1_pru1_gpo16 A3 13
pr1_pru1_gpo15 C5 13
pr1_pru1_gpo14 D6 13
pr1_pru1_gpo13 B2 13
pr1_pru1_gpo12 C4 13
pr1_pru1_gpo11 C3 13
pr1_pru1_gpo10 C2 13
pr1_pru1_gpi9 D5 12
pr1_pru1_gpi8 F6 12
pr1_pru1_gpi7 D3 12
pr1_pru1_gpi6 E6 12
pr1_pru1_gpi5 F5 12
pr1_pru1_gpi4 E4 12
pr1_pru1_gpi3 C1 12
pr1_pru1_gpi2 F4 12
pr1_pru1_gpi1 D2 12
pr1_pru1_gpi0 E2 12
pr1_pru1_gpo9 D5 13
pr1_pru1_gpo8 F6 13
pr1_pru1_gpo7 D3 13
pr1_pru1_gpo6 E6 13
pr1_pru1_gpo5 F5 13
pr1_pru1_gpo4 E4 13
pr1_pru1_gpo3 C1 13
pr1_pru1_gpo2 F4 13
pr1_pru1_gpo1 D2 13
pr1_pru1_gpo0 E2 13
pr1_pru0_gpi20 AD3 12
pr1_pru0_gpi19 AD2 12
pr1_pru0_gpi18 AE6 12
pr1_pru0_gpi17 AE2 12
pr1_pru0_gpi16 AE1 12
pr1_pru0_gpi15 AE5 12
pr1_pru0_gpi14 AE3 12
pr1_pru0_gpi13 AF1 12
pr1_pru0_gpi12 AF4 12
pr1_pru0_gpi11 AF3 12
pr1_pru0_gpi10 AF6 12
pr1_pru0_gpo20 AD3 13
pr1_pru0_gpo19 AD2 13
pr1_pru0_gpo18 AE6 13
pr1_pru0_gpo17 AE2 13
pr1_pru0_gpo16 AE1 13
pr1_pru0_gpo15 AE5 13
pr1_pru0_gpo14 AE3 13
pr1_pru0_gpo13 AF1 13
pr1_pru0_gpo12 AF4 13
pr1_pru0_gpo11 AF3 13
pr1_pru0_gpo10 AF6 13
pr1_pru0_gpi9 AF2 12
pr1_pru0_gpi8 AG5 12
pr1_pru0_gpi7 AG3 12
pr1_pru0_gpi6 AG2 12
pr1_pru0_gpi5 AG4 12
pr1_pru0_gpi4 AH4 12
pr1_pru0_gpi3 AG6 12
pr1_pru0_gpi2 AH5 12
pr1_pru0_gpi1 AH3 12
pr1_pru0_gpi0 AH6 12
pr1_pru0_gpo9 AF2 13
pr1_pru0_gpo8 AG5 13
pr1_pru0_gpo7 AG3 13
pr1_pru0_gpo6 AG2 13
pr1_pru0_gpo5 AG4 13
pr1_pru0_gpo4 AH4 13
pr1_pru0_gpo3 AG6 13
pr1_pru0_gpo2 AH5 13
pr1_pru0_gpo1 AH3 13
pr1_pru0_gpo0 AH6 13
pr1_edio_data_out7 AD3 11 D1 13
pr1_edio_data_out6 AD2 11 F3 13
pr1_edio_data_out5 AE6 11 F2 13
pr1_edio_data_out4 AE2 11 G6 13
pr1_edio_data_out3 AE1 11 G1 13
pr1_edio_data_out2 AE5 11 H7 13
pr1_edio_data_out1 AE3 11 G2 13
pr1_edio_data_out0 AF1 11 E1 13
pr1_edio_data_in7 AD3 10 D1 12
pr1_edio_data_in6 AD2 10 F3 12
pr1_edio_data_in5 AE6 10 F2 12
pr1_edio_data_in4 AE2 10 G6 12
pr1_edio_data_in3 AE1 10 G1 12
pr1_edio_data_in2 AE5 10 H7 12
pr1_edio_data_in1 AE3 10 G2 12
pr1_edio_data_in0 AF1 10 E1 12
pr1_edio_sof AF4 10 F4 11
pr1_edc_latch0_in AG3 10 E2 11 D18 12
pr1_edc_latch1_in AG5 10
pr1_edc_sync1_out AF6 10
pr1_edc_sync0_out AF2 10 D2 11 B18 13
pr1_edio_latch_in AF3 10
pr1_uart0_cts_n G1 11 F11 10
pr1_uart0_rts_n G6 11 G10 10
pr1_uart0_txd F3 11 G11 10
pr1_uart0_rxd F2 11 F10 10
pr1_ecap0_ecap_capin_apwm_o D1 11 E9 10
PRU-ICSS1 MII
pr1_mii1_txd3 F5 11 F5 11
pr1_mii1_txd2 E6 11 E6 11
pr1_mii1_txd1 D5 11 D2 13
pr1_mii1_txd0 C2 11 F4 13
pr1_mii1_rxd3 B2 11 E9 12
pr1_mii1_rxd2 D6 11 F9 12
pr1_mii1_rxd1 C5 11 F8 12
pr1_mii1_rxd0 A3 11 E7 12
pr1_mii1_rxdv C4 11 G11 12
pr1_mii1_txen E4 11 E4 11
pr1_mii1_rxer B3 11 E11 12
pr1_mii_mr1_clk C3 11 F10 12
pr1_mii_mt1_clk C1 11 C1 11
pr1_mii0_txd3 V5 11 D9 13
pr1_mii0_txd2 V4 11 D7 13
pr1_mii0_txd1 Y2 11 A5 13
pr1_mii0_txd0 W2 11 C6 13
pr1_mii0_rxd3 W9 11 B7 12
pr1_mii0_rxd2 V9 11 B8 12
pr1_mii0_rxd1 V6 11 A7 12
pr1_mii0_rxd0 U6 11 A8 12
pr1_mii0_rxdv V2 11 C7 12
pr1_mii0_txen V3 11 D8 13
pr1_mii0_rxer U7 11 C9 12
pr1_mii_mt0_clk U5 11 E8 12
pr1_mii_mr0_clk Y1 11 C8 12
pr1_mdio_mdclk D3 11
pr1_mdio_data F6 11
pr1_mii1_crs A4 11 G10 12
pr1_mii1_rxlink B4 11 F11 12
pr1_mii1_col B5 11 E2 12
pr1_mii0_col V1 11 B9 12
pr1_mii0_rxlink U4 11 A9 12
pr1_mii0_crs V7 11 A10 12
  1. These signals are internally muxed with the PRU GPI/GPO signals. When PRUSS1_MII pins are selected from IOSЕТ3, the PRUSS internal wrapper multiplexing must be configured for PRUSS_MII functionality (or MII2 mode). In this configuration, the PRU pins listed below are not available for any other I/O functionality and cannot be selected. Refer to the PRU chapter in the device TRM for more details about the PRU-ICSS internal wrapper multiplexing.
    • PRUSS1_MII0 pins selected from IOSЕТ3:
      • pr2_pru1_* cannot be used.
    • PRUSS1_MII1 pins selected from IOSЕТ4:
      • pr1_pru1_*, pr2_pru0_*, pr2_pru1_* cannot be used.
  2. These IOSETS (PRU-ICSS1 IOSET3 and IOSET4) are combined in the TI PinMux Tool and renamed PRUSS1_MII_IOSЕТ_3.

Table 5-189 PRU-ICSS2 IOSETs

SIGNALS IOSET1 IOSET2
BALL MUX BALL MUX
PRU-ICSS2
pr2_pru1_gpi20 F10 12 F10 12
pr2_pru1_gpi19 G10 12 G10 12
pr2_pru1_gpi18 F11 12 F11 12
pr2_pru1_gpi17 E11 12 E11 12
pr2_pru1_gpi16 W2 12 G14 12
pr2_pru1_gpi15 Y2 12 A13 12
pr2_pru1_gpi14 V3 12 E14 12
pr2_pru1_gpi13 V4 12 A12 12
pr2_pru1_gpi12 V5 12 B13 12
pr2_pru1_gpi11 U5 12 A11 12
pr2_pru1_gpi10 U6 12 B12 12
pr2_pru1_gpi9 V6 12 F12 12
pr2_pru1_gpi8 U7 12 G12 12
pr2_pru1_gpi7 V7 12 C14 12
pr2_pru1_gpi6 V9 12 E17 12
pr2_pru1_gpi5 W9 12 D18 12
pr2_pru1_gpi4 Y1 12 AA4 12
pr2_pru1_gpi3 V2 12 AB3 12
pr2_pru1_gpi2 U3 12 AB9 12
pr2_pru1_gpi1 U4 12 AA3 12
pr2_pru1_gpi0 V1 12 D17 12
pr2_pru1_gpo20 F10 13 F10 13
pr2_pru1_gpo19 G10 13 G10 13
pr2_pru1_gpo18 F11 13 F11 13
pr2_pru1_gpo17 E11 13 E11 13
pr2_pru1_gpo16 W2 13 G14 13
pr2_pru1_gpo15 Y2 13 A13 13
pr2_pru1_gpo14 V3 13 E14 13
pr2_pru1_gpo13 V4 13 A12 13
pr2_pru1_gpo12 V5 13 B13 13
pr2_pru1_gpo11 U5 13 A11 13
pr2_pru1_gpo10 U6 13 B12 13
pr2_pru1_gpo9 V6 13 F12 13
pr2_pru1_gpo8 U7 13 G12 13
pr2_pru1_gpo7 V7 13 C14 13
pr2_pru1_gpo6 V9 13 E17 13
pr2_pru1_gpo5 W9 13 D18 13
pr2_pru1_gpo4 Y1 13 AA4 13
pr2_pru1_gpo3 V2 13 AB3 13
pr2_pru1_gpo2 U3 13 AB9 13
pr2_pru1_gpo1 U4 13 AA3 13
pr2_pru1_gpo0 V1 13 D17 13
pr2_pru0_gpi20 A10 12 F14 12
pr2_pru0_gpi19 B9 12 A18 12
pr2_pru0_gpi18 A9 12 A19 12
pr2_pru0_gpi17 C9 12 A16 12
pr2_pru0_gpi16 A8 12 C15 12
pr2_pru0_gpi15 A7 12 C17 12
pr2_pru0_gpi14 B8 12 B19 12
pr2_pru0_gpi13 B7 12 F15 12
pr2_pru0_gpi12 C7 12 B18 12
pr2_pru0_gpi11 C8 12 AB5 12
pr2_pru0_gpi10 C6 12 AB8 12
pr2_pru0_gpi9 A5 12 AD6 12
pr2_pru0_gpi8 D8 12 AC8 12
pr2_pru0_gpi7 D7 12 AC3 12
pr2_pru0_gpi6 D9 12 AC9 12
pr2_pru0_gpi5 E8 12 AC6 12
pr2_pru0_gpi4 E7 12 AC7 12
pr2_pru0_gpi3 F8 12 AC4 12
pr2_pru0_gpi2 F9 12 AD4 12
pr2_pru0_gpi1 E9 12 AB4 12
pr2_pru0_gpi0 G11 12 AC5 12
pr2_pru0_gpo20 A10 13 F14 13
pr2_pru0_gpo19 B9 13 A18 13
pr2_pru0_gpo18 A9 13 A19 13
pr2_pru0_gpo17 C9 13 A16 13
pr2_pru0_gpo16 A8 13 C15 13
pr2_pru0_gpo15 A7 13 C17 13
pr2_pru0_gpo14 B8 13 B19 13
pr2_pru0_gpo13 B7 13 F15 13
pr2_pru0_gpo12 C7 13 B18 13
pr2_pru0_gpo11 C8 13 AB5 13
pr2_pru0_gpo10 C6 13 AB8 13
pr2_pru0_gpo9 A5 13 AD6 13
pr2_pru0_gpo8 D8 13 AC8 13
pr2_pru0_gpo7 D7 13 AC3 13
pr2_pru0_gpo6 D9 13 AC9 13
pr2_pru0_gpo5 E8 13 AC6 13
pr2_pru0_gpo4 E7 13 AC7 13
pr2_pru0_gpo3 F8 13 AC4 13
pr2_pru0_gpo2 F9 13 AD4 13
pr2_pru0_gpo1 E9 13 AB4 13
pr2_pru0_gpo0 G11 13 AC5 13
pr2_edio_data_out7 A10 11
pr2_edio_data_out6 B9 11
pr2_edio_data_out5 A9 11
pr2_edio_data_out4 C9 11
pr2_edio_data_out3 A8 11
pr2_edio_data_out2 A7 11
pr2_edio_data_out1 B8 11
pr2_edio_data_out0 B7 11
pr2_edio_data_in7 A10 10
pr2_edio_data_in6 B9 10
pr2_edio_data_in5 A9 10
pr2_edio_data_in4 C9 10
pr2_edio_data_in3 A8 10
pr2_edio_data_in2 A7 10
pr2_edio_data_in1 B8 10
pr2_edio_data_in0 B7 10
pr2_edio_latch_in D9 10
pr2_edio_sof D7 10
pr2_edc_sync0_out E7 10 F15 13
pr2_edc_sync1_out E8 10
pr2_edc_latch0_in F9 10 E17 12
pr2_edc_latch1_in F8 10
pr2_uart0_rxd C6 10
pr2_uart0_txd C8 10
pr2_uart0_cts_n D8 10
pr2_uart0_rts_n A5 10
pr2_ecap0_ecap_capin_apwm_o C7 10
PRU-ICSS2 MII
pr2_mii1_txd3 AD4 11
pr2_mii1_txd2 AC4 11
pr2_mii1_txd1 AC7 11
pr2_mii1_txd0 AC6 11
pr2_mii1_rxd3 AC8 11
pr2_mii1_rxd2 AD6 11
pr2_mii1_rxd1 AB8 11
pr2_mii1_rxd0 AB5 11
pr2_mii_mr1_clk AC9 11
pr2_mii1_rxer B19 11
pr2_mii_mt1_clk AC5 11
pr2_mii1_rxdv AC3 11
pr2_mii1_txen AB4 11
pr2_mii0_txd3 A11 11
pr2_mii0_txd2 B13 11
pr2_mii0_txd1 A12 11
pr2_mii0_txd0 E14 11
pr2_mii0_rxd3 F14 11
pr2_mii0_rxd2 A19 11
pr2_mii0_rxd1 A18 11
pr2_mii0_rxd0 C15 11
pr2_mii_mr0_clk A13 11
pr2_mii0_rxer G12 11
pr2_mii_mt0_clk F12 11
pr2_mii0_rxdv G14 11
pr2_mii0_txen B12 11
pr2_mdio_mdclk C14 11 AB3 11
pr2_mdio_data D14 11 AA4 11
pr2_mii1_crs E17 11
pr2_mii1_rxlink C17 11
pr2_mii0_crs B18 11
pr2_mii0_rxlink A16 11
pr2_mii0_col F15 11
pr2_mii1_col D18 11

Table 5-190 PRU-ICSS2 IOSETs (EnDAT)

SIGNALS IOSET1 IOSET3
BALL MUX BALL MUX
pr2_pru1_endat0_clk V1 13 D17 13
pr2_pru1_endat0_out U4 13 AA3 13
pr2_pru1_endat0_out_en U3 13 AB9 13
pr2_pru1_endat1_clk V2 13 AB3 13
pr2_pru1_endat1_out Y1 13 AA4 13
pr2_pru1_endat1_out_en W9 13 D18 13
pr2_pru1_endat2_clk V9 13 E17 13
pr2_pru1_endat2_out V7 13 C14 13
pr2_pru1_endat2_out_en U7 13 G12 13
pr2_pru1_endat0_in V6 12 F12 12
pr2_pru1_endat1_in U6 12 B12 12
pr2_pru1_endat2_in U5 12 A11 12
pr2_pru0_endat0_clk AC5 13 G11 13
pr2_pru0_endat0_out AB4 13 E9 13
pr2_pru0_endat0_out_en AD4 13 F9 13
pr2_pru0_endat1_clk AC4 13 F8 13
pr2_pru0_endat1_out AC7 13 E7 13
pr2_pru0_endat1_out_en AC6 13 E8 13
pr2_pru0_endat2_clk AC9 13 D9 13
pr2_pru0_endat2_out AC3 13 D7 13
pr2_pru0_endat2_out_en AC8 13 D8 13
pr2_pru0_endat0_in AD6 12 A5 12
pr2_pru0_endat1_in AB8 12 C6 12
pr2_pru0_endat2_in AB5 12 C8 12

Table 5-191 PRU-ICSS2 IOSETs (Sigma Delta)

SIGNALS IOSET1 IOSET3
BALL MUX BALL MUX
pr2_pru1_sd0_clk V1 12 D17 12
pr2_pru1_sd0_d U4 12 AA3 12
pr2_pru1_sd1_clk U3 12 AB9 12
pr2_pru1_sd1_d V2 12 AB3 12
pr2_pru1_sd2_clk Y1 12 AA4 12
pr2_pru1_sd2_d W9 12 D18 12
pr2_pru1_sd3_clk V9 12 E17 12
pr2_pru1_sd3_d V7 12 C14 12
pr2_pru1_sd4_clk U7 12 G12 12
pr2_pru1_sd4_d V6 12 F12 12
pr2_pru1_sd5_clk U6 12 B12 12
pr2_pru1_sd5_d U5 12 A11 12
pr2_pru1_sd6_clk V5 12 B13 12
pr2_pru1_sd6_d V4 12 A12 12
pr2_pru1_sd7_clk V3 12 E14 12
pr2_pru1_sd7_d Y2 12 A13 12
pr2_pru1_sd8_clk W2 12 G14 12
pr2_pru1_sd8_d E11 12 E11 12
pr2_pru0_sd0_clk G11 12 AC5 12
pr2_pru0_sd0_d E9 12 AB4 12
pr2_pru0_sd1_clk F9 12 AD4 12
pr2_pru0_sd1_d F8 12 AC4 12
pr2_pru0_sd2_clk E7 12 AC7 12
pr2_pru0_sd2_d E8 12 AC6 12
pr2_pru0_sd3_clk D9 12 AC9 12
pr2_pru0_sd3_d D7 12 AC3 12
pr2_pru0_sd4_clk D8 12 AC8 12
pr2_pru0_sd4_d A5 12 AD6 12
pr2_pru0_sd5_clk C6 12 AB8 12
pr2_pru0_sd5_d C8 12 AB5 12
pr2_pru0_sd6_clk C7 12 B18 12
pr2_pru0_sd6_d B7 12 F15 12
pr2_pru0_sd7_clk B8 12 B19 12
pr2_pru0_sd7_d A7 12 C17 12
pr2_pru0_sd8_clk A8 12 C15 12
pr2_pru0_sd8_d C9 12 A16 12