SPRS982H December 2016 – December 2019 AM5746 , AM5748 , AM5749
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
ASP1 | tc(AHCLKX) | Cycle time, AHCLKX | 20 | ns | ||
ASP2 | tw(AHCLKX) | Pulse duration, AHCLKX high or low | 0.35P (2) | ns | ||
ASP3 | tc(ACLKRX) | Cycle time, ACLKR/X | Any Other Conditions | 20 | ns | |
ACLKX/AFSX (In Sync Mode), ACLKR/AFSR (In Async Mode), and AXR are all inputs "80M" Virtual IO Timing Mode | 12.5 | ns | ||||
ASP4 | tw(ACLKRX) | Pulse duration, ACLKR/X high or low | Any Other Conditions | 0.5R(3) - 3 | ns | |
ACLKX/AFSX (In Sync Mode), ACLKR/AFSR (In Async Mode), and AXR are all inputs "80M" Virtual IO Timing Modes | 0.38R (3) | ns | ||||
ASP5 | tsu(AFSRX-ACLK) | Setup time, AFSR/X input valid before ACLKR/X | ACLKR/X int | 20.7 | ns | |
ACLKR/X ext in
ACLKR/X ext out |
3.9 | ns | ||||
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes |
3 | ns | ||||
ASP6 | th(ACLK-AFSRX) | Hold time, AFSR/X input valid after ACLKR/X | ACLKR/X int | -1 | ns | |
ACLKR/X ext in
ACLKR/X ext out |
3.2 | ns | ||||
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes |
3 | ns | ||||
ASP7 | tsu(AXR-ACLK) | Setup time, AXR input valid before ACLKR/X | ACLKR/X int | 21.4 | ns | |
ACLKR/X ext in
ACLKR/X ext out |
3.9 | ns | ||||
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes |
3 | ns | ||||
ASP8 | th(ACLK-AXR) | Hold time, AXR input valid after ACLKR/X | ACLKR/X int | -1 | ns | |
ACLKR/X ext in
ACLKR/X ext out |
3.2 | ns | ||||
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual IO Timing Modes |
3 | ns |