JAJSS68A November   2023  – June 2024 AM625SIP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes and Signal Descriptions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Operating Performance Points
    5. 6.5 Thermal Resistance Characteristics
      1. 6.5.1 Thermal Resistance Characteristics for AMK Package
    6. 6.6 Timing and Switching Characteristics
      1. 6.6.1 Power Supply Requirements
        1. 6.6.1.1 Power Supply Sequencing
  8. 7 アプリケーション、実装、およびレイアウト
    1. 7.1 Peripheral- and Interface-Specific Design Information
      1. 7.1.1 Integrated LPDDR4 SDRAM Information
  9. 8 Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • AMK|425
サーマルパッド・メカニカル・データ
発注情報

5.1 Pin Diagrams

Note: The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package.

Figure 5-1 shows a top view of the ball locations for the 425-ball grid array (FCCSP BGA) package to quickly locate signal names and ball grid numbering. The pin diagram in this document is intended to be used with Pin Attributes and Signal Descriptions section of this document along with the Pin Attributes through Pin Connectivity Requirements tables found in the AM62x Sitara Processors Datasheet.

Figure 5-1 AMK FCCSP BGA Package (Top View)