JAJSS68A November 2023 – June 2024 AM625SIP
PRODUCTION DATA
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This section describes the AM625SIP device pins which have different power or signal functions relative to the ALW packaged AM6254 device. The AM6254 DDRSS0 signals in the ALW package that would normally connect to an external SDRAM were connected directly to an integrated LPDDR4 SDRAM in the AM625SIP device, and the pins associated with these signals were reassigned to different power or signal functions. Table 5-1 contains a list of ball numbers that were reassigned to new power or signal functions along with their new ball name and signal description.
| BALL NUMBER |
BALL NAME | Signal Description |
|---|---|---|
| M9 | VDDS_DDR | DDR PHY IO supply |
| F2 | VDDS_MEM_1P1 | SDRAM IO supply (Sources the SDRAM VDD2 and VDDQ power rails) |
| G2 | ||
| H1 | ||
| H2 | ||
| N1 | ||
| N2 | ||
| P2 | ||
| R2 | ||
| U1 | ||
| U2 | ||
| V2 | ||
| W2 | ||
| M4 | VDDS_MEM_1P8 | SDRAM Core supply (Sources the SDRAM VDD1 power rail) |
| N3 | ||
| R3 | DDR_ZQ | SDRAM
Calibration Reference(1) (Connects to the SDRAM ZQ Calibration Reference) |
| E1 | VSS | Ground (Connects to the SDRAM VSS and VSSQ grounds) |
| E2 | ||
| E3 | ||
| F1 | ||
| F3 | ||
| F4 | ||
| G5 | ||
| H5 | ||
| H6 | ||
| J1 | ||
| J2 | ||
| J3 | ||
| J4 | ||
| K1 | ||
| K2 | ||
| K3 | ||
| K4 | ||
| L1 | ||
| L2 | ||
| L5 | ||
| L6 | ||
| M1 | ||
| M5 | ||
| N6 | ||
| P1 | ||
| P4 | ||
| P5 | ||
| R1 | ||
| R5 | ||
| R6 | ||
| T1 | ||
| T4 | ||
| U3 | ||
| V1 | ||
| V5 | ||
| V6 | ||
| W1 | ||
| W5 | ||
| Y1 |