JAJSQZ4B March   2023  – September 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      11
      2.      12
    3. 5.3 Signal Descriptions
      1.      14
      2. 5.3.1  CPSW3G
        1. 5.3.1.1 MAIN Domain
          1.        17
          2.        18
          3.        19
          4.        20
      3. 5.3.2  CPTS
        1. 5.3.2.1 MAIN Domain
          1.        23
      4. 5.3.3  CSI-2
        1. 5.3.3.1 MAIN Domain
          1.        26
      5. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
          1.        29
      6. 5.3.5  DSS
        1. 5.3.5.1 MAIN Domain
          1.        32
      7. 5.3.6  ECAP
        1. 5.3.6.1 MAIN Domain
          1.        35
          2.        36
          3.        37
      8. 5.3.7  Emulation and Debug
        1. 5.3.7.1 MAIN Domain
          1.        40
        2. 5.3.7.2 MCU Domain
          1.        42
      9. 5.3.8  EPWM
        1. 5.3.8.1 MAIN Domain
          1.        45
          2.        46
          3.        47
          4.        48
      10. 5.3.9  EQEP
        1. 5.3.9.1 MAIN Domain
          1.        51
          2.        52
          3.        53
      11. 5.3.10 GPIO
        1. 5.3.10.1 MAIN Domain
          1.        56
          2.        57
        2. 5.3.10.2 MCU Domain
          1.        59
      12. 5.3.11 GPMC
        1. 5.3.11.1 MAIN Domain
          1.        62
      13. 5.3.12 I2C
        1. 5.3.12.1 MAIN Domain
          1.        65
          2.        66
          3.        67
          4.        68
        2. 5.3.12.2 MCU Domain
          1.        70
        3. 5.3.12.3 WKUP Domain
          1.        72
      14. 5.3.13 MCAN
        1. 5.3.13.1 MAIN Domain
          1.        75
        2. 5.3.13.2 MCU Domain
          1.        77
          2.        78
      15. 5.3.14 MCASP
        1. 5.3.14.1 MAIN Domain
          1.        81
          2.        82
          3.        83
      16. 5.3.15 MCSPI
        1. 5.3.15.1 MAIN Domain
          1.        86
          2.        87
          3.        88
        2. 5.3.15.2 MCU Domain
          1.        90
          2.        91
      17. 5.3.16 MDIO
        1. 5.3.16.1 MAIN Domain
          1.        94
      18. 5.3.17 MMC
        1. 5.3.17.1 MAIN Domain
          1.        97
          2.        98
          3.        99
      19. 5.3.18 OSPI
        1. 5.3.18.1 MAIN Domain
          1.        102
      20. 5.3.19 Power Supply
        1.       104
      21. 5.3.20 Reserved
        1.       106
      22. 5.3.21 System and Miscellaneous
        1. 5.3.21.1 Boot Mode Configuration
          1. 5.3.21.1.1 MAIN Domain
            1.         110
        2. 5.3.21.2 Clock
          1. 5.3.21.2.1 MCU Domain
            1.         113
          2. 5.3.21.2.2 WKUP Domain
            1.         115
        3. 5.3.21.3 System
          1. 5.3.21.3.1 MAIN Domain
            1.         118
          2. 5.3.21.3.2 MCU Domain
            1.         120
          3. 5.3.21.3.3 WKUP Domain
            1.         122
        4. 5.3.21.4 VMON
          1.        124
      23. 5.3.22 TIMER
        1. 5.3.22.1 MAIN Domain
          1.        127
        2. 5.3.22.2 MCU Domain
          1.        129
        3. 5.3.22.3 WKUP Domain
          1.        131
      24. 5.3.23 UART
        1. 5.3.23.1 MAIN Domain
          1.        134
          2.        135
          3.        136
          4.        137
          5.        138
          6.        139
          7.        140
        2. 5.3.23.2 MCU Domain
          1.        142
        3. 5.3.23.3 WKUP Domain
          1.        144
      25. 5.3.24 USB
        1. 5.3.24.1 MAIN Domain
          1.        147
          2.        148
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings for Devices which are not AEC - Q100 Qualified
    3. 6.3  ESD Ratings for AEC - Q100 Qualified Devices
    4. 6.4  Power-On Hours (POH)
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
    7. 6.7  Power Consumption Summary
    8. 6.8  Electrical Characteristics
      1. 6.8.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.8.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.8.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.8.4 Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
      5. 6.8.5 SDIO Electrical Characteristics
      6. 6.8.6 LVCMOS Electrical Characteristics
      7. 6.8.7 CSI-2 (D-PHY) Electrical Characteristics
      8. 6.8.8 USB2PHY Electrical Characteristics
      9. 6.8.9 DDR Electrical Characteristics
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 Thermal Resistance Characteristics for AMB Package
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Requirements
        1. 6.11.2.1 Power Supply Slew Rate Requirement
        2. 6.11.2.2 Power Supply Sequencing
          1. 6.11.2.2.1 Power-Up Sequencing
          2. 6.11.2.2.2 Power-Down Sequencing
          3. 6.11.2.2.3 Partial IO Power Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 Reset Timing
        2. 6.11.3.2 Error Signal Timing
        3. 6.11.3.3 Clock Timing
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.11.4.1.1.1 Load Capacitance
            2. 6.11.4.1.1.2 Shunt Capacitance
          2. 6.11.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
          3. 6.11.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
          4. 6.11.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 6.11.4.1.5 WKUP_LFOSC0 Not Used
        2. 6.11.4.2 Output Clocks
        3. 6.11.4.3 PLLs
        4. 6.11.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.11.5 Peripherals
        1. 6.11.5.1  CPSW3G
          1. 6.11.5.1.1 CPSW3G MDIO Timing
          2. 6.11.5.1.2 CPSW3G RMII Timing
          3. 6.11.5.1.3 CPSW3G RGMII Timing
        2. 6.11.5.2  CPTS
        3. 6.11.5.3  CSI-2
        4. 6.11.5.4  DDRSS
        5. 6.11.5.5  DSS
        6. 6.11.5.6  ECAP
        7. 6.11.5.7  Emulation and Debug
          1. 6.11.5.7.1 Trace
          2. 6.11.5.7.2 JTAG
        8. 6.11.5.8  EPWM
        9. 6.11.5.9  EQEP
        10. 6.11.5.10 GPIO
        11. 6.11.5.11 GPMC
          1. 6.11.5.11.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.11.5.11.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.11.5.11.3 GPMC and NAND Flash — Asynchronous Mode
        12. 6.11.5.12 I2C
        13. 6.11.5.13 MCAN
        14. 6.11.5.14 MCASP
        15. 6.11.5.15 MCSPI
          1. 6.11.5.15.1 MCSPI — Controller Mode
          2. 6.11.5.15.2 MCSPI — Peripheral Mode
        16. 6.11.5.16 MMCSD
          1. 6.11.5.16.1 MMC0 - eMMC/SD/SDIO Interface
            1. 6.11.5.16.1.1  Legacy SDR Mode
            2. 6.11.5.16.1.2  High Speed SDR Mode
            3. 6.11.5.16.1.3  HS200 Mode
            4. 6.11.5.16.1.4  Default Speed Mode
            5. 6.11.5.16.1.5  High Speed Mode
            6. 6.11.5.16.1.6  UHS–I SDR12 Mode
            7. 6.11.5.16.1.7  UHS–I SDR25 Mode
            8. 6.11.5.16.1.8  UHS–I SDR50 Mode
            9. 6.11.5.16.1.9  UHS–I DDR50 Mode
            10. 6.11.5.16.1.10 UHS–I SDR104 Mode
          2. 6.11.5.16.2 MMC1/MMC2 - SD/SDIO Interface
            1. 6.11.5.16.2.1 Default Speed Mode
            2. 6.11.5.16.2.2 High Speed Mode
            3. 6.11.5.16.2.3 UHS–I SDR12 Mode
            4. 6.11.5.16.2.4 UHS–I SDR25 Mode
            5. 6.11.5.16.2.5 UHS–I SDR50 Mode
            6. 6.11.5.16.2.6 UHS–I DDR50 Mode
            7. 6.11.5.16.2.7 UHS–I SDR104 Mode
        17. 6.11.5.17 OSPI
          1. 6.11.5.17.1 OSPI0 PHY Mode
            1. 6.11.5.17.1.1 OSPI0 With PHY Data Training
            2. 6.11.5.17.1.2 OSPI0 Without Data Training
              1. 6.11.5.17.1.2.1 OSPI0 PHY SDR Timing
              2. 6.11.5.17.1.2.2 OSPI0 PHY DDR Timing
          2. 6.11.5.17.2 OSPI0 Tap Mode
            1. 6.11.5.17.2.1 OSPI0 Tap SDR Timing
            2. 6.11.5.17.2.2 OSPI0 Tap DDR Timing
        18. 6.11.5.18 Timers
        19. 6.11.5.19 UART
        20. 6.11.5.20 USB
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53 Subsystem
      2. 7.2.2 Device/Power Manager
      3. 7.2.3 MCU Arm Cortex-R5F Subsystem
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 C7xV-256 Deep Learning Accelerator
      2. 7.3.2 Vision Pre-processing Accelerator
      3. 7.3.3 JPEG Encoder
      4. 7.3.4 Video Accelerator
    4. 7.4 Other Subsystems
      1. 7.4.1 Dual Clock Comparator (DCC)
      2. 7.4.2 Data Movement Subsystem (DMSS)
      3. 7.4.3 Memory Cyclic Redundancy Check (MCRC)
      4. 7.4.4 Peripheral DMA Controller (PDMA)
      5. 7.4.5 Real-Time Clock (RTC)
    5. 7.5 Peripherals
      1. 7.5.1  Gigabit Ethernet Switch (CPSW3G)
      2. 7.5.2  Camera Serial Interface Receiver (CSI_RX_IF)
      3. 7.5.3  Display Subsystem (DSS)
      4. 7.5.4  Enhanced Capture (ECAP)
      5. 7.5.5  Error Location Module (ELM)
      6. 7.5.6  Enhanced Pulse Width Modulation (EPWM)
      7. 7.5.7  Error Signaling Module (ESM)
      8. 7.5.8  Enhanced Quadrature Encoder Pulse (EQEP)
      9. 7.5.9  General-Purpose Interface (GPIO)
      10. 7.5.10 General-Purpose Memory Controller (GPMC)
      11. 7.5.11 Global Timebase Counter (GTC)
      12. 7.5.12 Inter-Integrated Circuit (I2C)
      13. 7.5.13 Modular Controller Area Network (MCAN)
      14. 7.5.14 Multichannel Audio Serial Port (MCASP)
      15. 7.5.15 Multichannel Serial Peripheral Interface (MCSPI)
      16. 7.5.16 Multi-Media Card Secure Digital (MMCSD)
      17. 7.5.17 Octal Serial Peripheral Interface (OSPI)
      18. 7.5.18 Timers
      19. 7.5.19 Universal Asynchronous Receiver/Transmitter (UART)
      20. 7.5.20 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal SPI devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines
      5. 8.2.5 High Speed Differential Signal Routing Guidance
      6. 8.2.6 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • AMB|484
サーマルパッド・メカニカル・データ
発注情報
6.11.2.2.1 Power-Up Sequencing

Table 6-4 and Figure 6-5 describes the device power-up sequencing.

Note: The power supply sequencing requirements defined in this section does not include entry or exit from low power modes. See Section 6.11.2.2.3, Partial IO Power Sequencing for more information on power supply sequence requirements when entering or exiting low power modes.
Table 6-4 Power-Up Sequencing – Supply / Signal Assignments See: Figure 6-5
WAVEFORM SUPPLY / SIGNAL NAME
A VSYS(1), VMON_VSYS(2)
B VDDSHV_CANUART(3), VDDSHV_MCU(3), VDDSHV0(3), VDDSHV1(3), VDDSHV2(3), VDDSHV3(3), VDDA_3P3_USB, VMON_3P3_SOC(4)
C VDDSHV_CANUART(5), VDDSHV_MCU(5), VDDSHV0(5), VDDSHV1(5), VDDSHV2(5), VDDSHV3(5), VDDA_MCU, VDDS_OSC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_PLL3, VDDA_PLL4, VDDA_PLL5, VDDA_1P8_CSIRX0, VDDA_1P8_USB, VDDA_TEMP0, VDDA_TEMP1, VDDA_TEMP2, VMON_1P8_SOC(6)
D VDDSHV4(7), VDDSHV5(7), VDDSHV6(7)
E VDDS_DDR(8), VDDS_DDR_C(8)
F VDD_CANUART(9)
G VDD_CANUART(10), VDD_CORE(10)(12), VDDA_CORE_CSIRX0(10), VDDA_CORE_USB0(10), VDDA_DDR_PLL0(10)
H VDD_CANUART(11), VDD_CORE(11)(12), VDDA_CORE_CSIRX0(11), VDDA_CORE_USB0(11), VDDA_DDR_PLL0(11), VDDR_CORE(12)
I VPP(13)
J MCU_PORz
K MCU_OSC0_XI, MCU_OSC0_XI
(1) VSYS represents the name of a supply which sources power to the entire system. This supply is expected to be a pre-regulated supply that sources power management devices which source all other supplies.
(2) VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information, see the System Power Supply Monitor Design Guidelines.
(3) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or 3.3V depending on the application requirements.VDDSHV_CANUART shall be connected to an always-on power source when using Partial IO low power mode, or connected to any valid IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to an always-on power source and is operating at 3.3V, it shall be ramped up with other 3.3V supplies during the 3.3V ramp period defined by this waveform.When any of the VDDSHV_MCU and VDDSHVx [x=0-3] IO supplies are operating at 3.3V, they shall be ramped up with other 3.3V supplies during the 3.3V ramp period defined by this waveform.
(4) The VMON_3P3_SOC input is used to monitor supply voltage and shall be connected to the respective 3.3V supply source.
(5) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or 3.3V depending on the application requirements.VDDSHV_CANUART shall be connected to an always-on power source when using Partial IO low power mode, or connected to any valid IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to an always-on power source and is operating at 1.8V, it shall be ramped up with other 1.8V supplies during the 1.8V ramp period defined by this waveform.When any of the VDDSHV_MCU and VDDSHVx [x=0-3] IO supplies are operating at 1.8V, they shall be ramped up with other 1.8V supplies during the 1.8V ramp period defined by this waveform.
(6) The VMON_1P8_SOC input is used to monitor supply voltage and shall be connected to the respective 1.8V supply source.
(7) VDDSHV4, VDDSHV5, and VDDSHV6 were designed to support power-up, power-down, or dynamic voltage change without any dependency on other power rails. This capability is required to support UHS-I SD Cards.
(8) VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp together.
(9) VDD_CANUART shall be connected to an always-on power source when using Partial IO low power mode.When VDD_CANUART is connected to an always-on power source, the potential applied to VDD_CORE must never be greater than the potential applied to VDD_CANUART + 0.18V during power-up or power-down. This requires VDD_CANUART to ramp up before and ramp down after VDD_CORE. VDD_CANUART does not have any ramp requirements beyond the one defined for VDD_CORE.
(10) VDD_CANUART shall be connected to the same power source as VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 when not using Partial IO low power mode.VDD_CANUART, VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 can be operated at 0.75V or 0.85V. When these supplies are operating at 0.75V, they shall be ramped up prior to VDDR_CORE as defined by this waveform.
(11) VDD_CANUART shall be connected to the same power source as VDD_CORE, VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 when not using Partial IO low power mode.VDD_CANUART, VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 can be operated at 0.75V or 0.85V. When these supplies are operating at 0.85V, they shall be powered from the same source as VDDR_CORE and ramped during the 0.85V ramp period defined by this waveform.
(12) The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE + 0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements beyond the one defined for VDDR_CORE.VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is operating at 0.85V.
(13) VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/down sequences and during normal device operation. This supply shall only be sourced while programming eFuse.
GUID-20220617-SS0I-JL4D-LMKS-XG0CBFR0MPK0-low.gif Figure 6-5 Power-Up Sequencing