JAJSQZ4 データシート

JAJSQZ4B March 2023 – September 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

PRODUCTION DATA

1
1 特長
2 アプリケーション
3 概要
1. 3.1 機能ブロック図
4 Device Comparison
1. 4.1 Related Products
5 Terminal Configuration and Functions
1. 5.1 Pin Diagrams
2. 5.2 Pin Attributes
  1. 11
  2. 12
3. 5.3 Signal Descriptions
  1. 14
  2. 5.3.1 CPSW3G
    1. 5.3.1.1 MAIN Domain
      1. 17
      2. 18
      3. 19
      4. 20
  3. 5.3.2 CPTS
    1. 5.3.2.1 MAIN Domain
      1. 23
  4. 5.3.3 CSI-2
    1. 5.3.3.1 MAIN Domain
      1. 26
  5. 5.3.4 DDRSS
    1. 5.3.4.1 MAIN Domain
      1. 29
  6. 5.3.5 DSS
    1. 5.3.5.1 MAIN Domain
      1. 32
  7. 5.3.6 ECAP
    1. 5.3.6.1 MAIN Domain
      1. 35
      2. 36
      3. 37
  8. 5.3.7 Emulation and Debug
    1. 5.3.7.1 MAIN Domain
      1. 40
    2. 5.3.7.2 MCU Domain
      1. 42
  9. 5.3.8 EPWM
    1. 5.3.8.1 MAIN Domain
      1. 45
      2. 46
      3. 47
      4. 48
  10. 5.3.9 EQEP
    1. 5.3.9.1 MAIN Domain
      1. 51
      2. 52
      3. 53
  11. 5.3.10 GPIO
    1. 5.3.10.1 MAIN Domain
      1. 56
      2. 57
    2. 5.3.10.2 MCU Domain
      1. 59
  12. 5.3.11 GPMC
    1. 5.3.11.1 MAIN Domain
      1. 62
  13. 5.3.12 I2C
    1. 5.3.12.1 MAIN Domain
      1. 65
      2. 66
      3. 67
      4. 68
    2. 5.3.12.2 MCU Domain
      1. 70
    3. 5.3.12.3 WKUP Domain
      1. 72
  14. 5.3.13 MCAN
    1. 5.3.13.1 MAIN Domain
      1. 75
    2. 5.3.13.2 MCU Domain
      1. 77
      2. 78
  15. 5.3.14 MCASP
    1. 5.3.14.1 MAIN Domain
      1. 81
      2. 82
      3. 83
  16. 5.3.15 MCSPI
    1. 5.3.15.1 MAIN Domain
      1. 86
      2. 87
      3. 88
    2. 5.3.15.2 MCU Domain
      1. 90
      2. 91
  17. 5.3.16 MDIO
    1. 5.3.16.1 MAIN Domain
      1. 94
  18. 5.3.17 MMC
    1. 5.3.17.1 MAIN Domain
      1. 97
      2. 98
      3. 99
  19. 5.3.18 OSPI
    1. 5.3.18.1 MAIN Domain
      1. 102
  20. 5.3.19 Power Supply
    1. 104
  21. 5.3.20 Reserved
    1. 106
  22. 5.3.21 System and Miscellaneous
    1. 5.3.21.1 Boot Mode Configuration
      1. 5.3.21.1.1 MAIN Domain
        
        110
    2. 5.3.21.2 Clock
      1. 5.3.21.2.1 MCU Domain
        
        113
      2. 5.3.21.2.2 WKUP Domain
        
        115
    3. 5.3.21.3 System
      1. 5.3.21.3.1 MAIN Domain
        
        118
      2. 5.3.21.3.2 MCU Domain
        
        120
      3. 5.3.21.3.3 WKUP Domain
        
        122
    4. 5.3.21.4 VMON
      1. 124
  23. 5.3.22 TIMER
    1. 5.3.22.1 MAIN Domain
      1. 127
    2. 5.3.22.2 MCU Domain
      1. 129
    3. 5.3.22.3 WKUP Domain
      1. 131
  24. 5.3.23 UART
    1. 5.3.23.1 MAIN Domain
      1. 134
      2. 135
      3. 136
      4. 137
      5. 138
      6. 139
      7. 140
    2. 5.3.23.2 MCU Domain
      1. 142
    3. 5.3.23.3 WKUP Domain
      1. 144
  25. 5.3.24 USB
    1. 5.3.24.1 MAIN Domain
      1. 147
      2. 148
4. 5.4 Pin Connectivity Requirements
6 Specifications
7 Detailed Description
8 Applications, Implementation, and Layout
9 Device and Documentation Support
10Revision History
11Mechanical, Packaging, and Orderable Information
1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

AMB|484

サーマルパッド・メカニカル・データ

発注情報

jajsqz4b_oa

6.11.3.3 Clock Timing

Tables and figures provided in this section define timing conditions, timing requirements, and switching characteristics for clock signals.

Table 6-18 Clock Timing Conditions

PARAMETER			MIN	MAX	UNIT
INPUT CONDITIONS
SR_I	Input slew rate		0.5		V/ns
OUTPUT CONDITIONS
C_L	Output load capacitance	5 ns ≤ t_c < 8 ns		5	pF
		8 ns ≤ t_c < 20 ns		10	pF
		20 ns ≤ t_c		30	pF

Table 6-19 Clock Timing Requirements see Figure 6-14

NO.			MIN	MAX	UNIT
CLK1	t_{c(EXT_REFCLK1)}	Cycle time minimum, EXT_REFCLK1	10		ns
CLK2	t_{w(EXT_REFCLK1H)}	Pulse Duration, EXT_REFCLK1 high	E*0.45⁽¹⁾	E*0.55⁽¹⁾	ns
CLK3	t_{w(EXT_REFCLK1L)}	Pulse Duration, EXT_REFCLK1 low	E*0.45⁽¹⁾	E*0.55⁽¹⁾	ns
CLK1	t_{c(MCU_EXT_REFCLK0)}	Cycle time minimum, MCU_EXT_REFCLK0	10		ns
CLK2	t_{w(MCU_EXT_REFCLK0H)}	Pulse Duration, MCU_EXT_REFCLK0 high	F*0.45⁽²⁾	F*0.55⁽²⁾	ns
CLK3	t_{w(MCU_EXT_REFCLK0L)}	Pulse Duration, MCU_EXT_REFCLK0 low	F*0.45⁽²⁾	F*0.55⁽²⁾	ns
CLK1	t_{c(AUDIO_EXT_REFCLK0)}	Cycle time minimum, AUDIO_EXT_REFCLK0	20		ns
CLK2	t_{w(AUDIO_EXT_REFCLK0H)}	Pulse Duration, AUDIO_EXT_REFCLK0 high	G*0.45⁽³⁾	G*0.55⁽³⁾	ns
CLK3	t_{w(AUDIO_EXT_REFCLK0L)}	Pulse Duration, AUDIO_EXT_REFCLK0 low	G*0.45⁽³⁾	G*0.55⁽³⁾	ns
CLK1	t_{c(AUDIO_EXT_REFCLK1)}	Cycle time minimum, AUDIO_EXT_REFCLK1	20		ns
CLK2	t_{w(AUDIO_EXT_REFCLK1H)}	Pulse Duration, AUDIO_EXT_REFCLK1 high	H*0.45⁽⁴⁾	H*0.55⁽⁴⁾	ns
CLK3	t_{w(AUDIO_EXT_REFCLK1L)}	Pulse Duration, AUDIO_EXT_REFCLK1 low	H*0.45⁽⁴⁾	H*0.55⁽⁴⁾	ns

(1) E = EXT_REFCLK1 cycle time in ns.

(2) F = MCU_EXT_REFCLK0 cycle time in ns.

(3) G = AUDIO_EXT_REFCLK0 cycle time in ns.

(4) H = AUDIO_EXT_REFCLK1 cycle time in ns.

Figure 6-14 Clock Timing Requirements

Table 6-20 Clock Switching Characteristics see Figure 6-15

NO.	PARAMETER		MIN	MAX	UNIT
CLK4	t_{c(SYSCLKOUT0)}	Cycle time minimum,SYSCLKOUT0	8		ns
CLK5	t_{w(SYSCLKOUT0H)}	Pulse Duration, SYSCLKOUT0 high	A*0.4⁽¹⁾	A*0.6⁽¹⁾	ns
CLK6	t_{w(SYSCLKOUT0L)}	Pulse Duration, SYSCLKOUT0 low	A*0.4⁽¹⁾	A*0.6⁽¹⁾	ns
CLK4	t_c(OBSCLK0)	Cycle time minimum, OBSCLK0	5		ns
CLK5	t_w(OBSCLK0H)	Pulse Duration, OBSCLK0 high	B*0.45⁽²⁾	B*0.55⁽²⁾	ns
CLK6	t_w(OBSCLK0L)	Pulse Duration, OBSCLK0 low	B*0.45⁽²⁾	B*0.55⁽²⁾	ns
CLK4	t_c(OBSCLK1)	Cycle time minimum, OBSCLK1	5		ns
CLK5	t_w(OBSCLK1H)	Pulse Duration, OBSCLK1 high	F*0.45⁽³⁾	F*0.55⁽³⁾	ns
CLK6	t_w(OBSCLK1L)	Pulse Duration, OBSCLK1 low	F*0.45⁽³⁾	F*0.55⁽³⁾	ns
CLK4	t_c(CLKOUT0)	Cycle time minimum, CLKOUT0	20		ns
CLK5	t_w(CLKOUT0H)	Pulse Duration, CLKOUT0 high	C*0.4⁽⁴⁾	C*0.6⁽⁴⁾	ns
CLK6	t_w(CLKOUT0L)	Pulse Duration, CLKOUT0 low	C*0.4⁽⁴⁾	C*0.6⁽⁴⁾	ns
CLK4	t_{c(MCU_SYSCLKOUT0)}	Cycle time minimum, MCU_SYSCLKOUT0	10		ns
CLK5	t_{w(MCU_SYSCLKOUT0H)}	Pulse Duration, MCU_SYSCLKOUT0 high	E*0.4⁽⁵⁾	E*0.6⁽⁵⁾	ns
CLK6	t_{w(MCU_SYSCLKOUT0L)}	Pulse Duration, MCU_SYSCLKOUT0 low	E*0.4⁽⁵⁾	E*0.6⁽⁵⁾	ns
CLK4	t_{c(MCU_OBSCLK0)}	Cycle time minimum, MCU_OBSCLK0	5		ns
CLK5	t_{w(MCU_OBSCLK0H)}	Pulse Duration, MCU_OBSCLK0 high	D*0.45⁽⁶⁾	D*0.55⁽⁶⁾	ns
CLK6	t_{w(MCU_OBSCLK0L)}	Pulse Duration, MCU_OBSCLK0 low	D*0.45⁽⁶⁾	D*0.55⁽⁶⁾	ns
CLK4	t_{c(WKUP_CLKOUT0)}	Cycle time minimum, WKUP_CLKOUT0	5		ns
CLK5	t_{w(WKUP_CLKOUT0H)}	Pulse Duration, WKUP_CLKOUT0 high	W*0.4⁽⁷⁾	W*0.6⁽⁷⁾	ns
CLK6	t_{w(WKUP_CLKOUT0L)}	Pulse Duration, WKUP_CLKOUT0 low	W*0.4⁽⁷⁾	W*0.6⁽⁷⁾	ns
CLK4	t_{c(AUDIO_EXT_REFCLK0 )}	Cycle time minimum, AUDIO_EXT_REFCLK0 (McASP Clock Source)	20		ns
CLK4	t_{c(AUDIO_EXT_REFCLK0 )}	Cycle time minimum, AUDIO_EXT_REFCLK0 (PLL Clock Source)	10		ns
CLK5	t_{w(AUDIO_EXT_REFCLK0 H)}	Pulse Duration, AUDIO_EXT_REFCLK0 high	G*0.4⁽⁸⁾	G*0.6⁽⁸⁾	ns
CLK6	t_{w(AUDIO_EXT_REFCLK0 L)}	Pulse Duration, AUDIO_EXT_REFCLK0 low	G*0.4⁽⁸⁾	G*0.6⁽⁸⁾	ns
CLK4	t_{c(AUDIO_EXT_REFCLK1 )}	Cycle time minimum, AUDIO_EXT_REFCLK1 (McASP Clock Source)	20		ns
CLK4	t_{c(AUDIO_EXT_REFCLK1 )}	Cycle time minimum, AUDIO_EXT_REFCLK1 (PLL Clock Source)	10		ns
CLK5	t_{w(AUDIO_EXT_REFCLK1 H)}	Pulse Duration, AUDIO_EXT_REFCLK1 high	J*0.4⁽⁹⁾	J*0.6⁽⁹⁾	ns
CLK6	t_{w(AUDIO_EXT_REFCLK1 L)}	Pulse Duration, AUDIO_EXT_REFCLK1 low	J*0.4⁽⁹⁾	J*0.6⁽⁹⁾	ns

(1) A = SYSCLKOUT0 cycle time in ns.

(2) B = OBSCLK0 cycle time in ns.

(3) F = OBSCLK1 cycle time in ns.

(4) C = CLKOUT0 cycle time in ns.

(5) E = MCU_SYSCLKOUT0 cycle time in ns.

(6) D = MCU_OBSCLK0 cycle time in ns.

(7) W = WKUP_CLKOUT0 cycle time in ns.

(8) G = AUDIO_EXT_REFCLK0 cycle time in ns.

(9) J = AUDIO_EXT_REFCLK1 cycle time in ns.

Figure 6-15 Clock Switching Characteristics