JAJSQZ4 データシート

JAJSQZ4B March 2023 – September 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

PRODUCTION DATA

1
1 特長
2 アプリケーション
3 概要
1. 3.1 機能ブロック図
4 Device Comparison
1. 4.1 Related Products
5 Terminal Configuration and Functions
1. 5.1 Pin Diagrams
2. 5.2 Pin Attributes
  1. 11
  2. 12
3. 5.3 Signal Descriptions
  1. 14
  2. 5.3.1 CPSW3G
    1. 5.3.1.1 MAIN Domain
      1. 17
      2. 18
      3. 19
      4. 20
  3. 5.3.2 CPTS
    1. 5.3.2.1 MAIN Domain
      1. 23
  4. 5.3.3 CSI-2
    1. 5.3.3.1 MAIN Domain
      1. 26
  5. 5.3.4 DDRSS
    1. 5.3.4.1 MAIN Domain
      1. 29
  6. 5.3.5 DSS
    1. 5.3.5.1 MAIN Domain
      1. 32
  7. 5.3.6 ECAP
    1. 5.3.6.1 MAIN Domain
      1. 35
      2. 36
      3. 37
  8. 5.3.7 Emulation and Debug
    1. 5.3.7.1 MAIN Domain
      1. 40
    2. 5.3.7.2 MCU Domain
      1. 42
  9. 5.3.8 EPWM
    1. 5.3.8.1 MAIN Domain
      1. 45
      2. 46
      3. 47
      4. 48
  10. 5.3.9 EQEP
    1. 5.3.9.1 MAIN Domain
      1. 51
      2. 52
      3. 53
  11. 5.3.10 GPIO
    1. 5.3.10.1 MAIN Domain
      1. 56
      2. 57
    2. 5.3.10.2 MCU Domain
      1. 59
  12. 5.3.11 GPMC
    1. 5.3.11.1 MAIN Domain
      1. 62
  13. 5.3.12 I2C
    1. 5.3.12.1 MAIN Domain
      1. 65
      2. 66
      3. 67
      4. 68
    2. 5.3.12.2 MCU Domain
      1. 70
    3. 5.3.12.3 WKUP Domain
      1. 72
  14. 5.3.13 MCAN
    1. 5.3.13.1 MAIN Domain
      1. 75
    2. 5.3.13.2 MCU Domain
      1. 77
      2. 78
  15. 5.3.14 MCASP
    1. 5.3.14.1 MAIN Domain
      1. 81
      2. 82
      3. 83
  16. 5.3.15 MCSPI
    1. 5.3.15.1 MAIN Domain
      1. 86
      2. 87
      3. 88
    2. 5.3.15.2 MCU Domain
      1. 90
      2. 91
  17. 5.3.16 MDIO
    1. 5.3.16.1 MAIN Domain
      1. 94
  18. 5.3.17 MMC
    1. 5.3.17.1 MAIN Domain
      1. 97
      2. 98
      3. 99
  19. 5.3.18 OSPI
    1. 5.3.18.1 MAIN Domain
      1. 102
  20. 5.3.19 Power Supply
    1. 104
  21. 5.3.20 Reserved
    1. 106
  22. 5.3.21 System and Miscellaneous
    1. 5.3.21.1 Boot Mode Configuration
      1. 5.3.21.1.1 MAIN Domain
        
        110
    2. 5.3.21.2 Clock
      1. 5.3.21.2.1 MCU Domain
        
        113
      2. 5.3.21.2.2 WKUP Domain
        
        115
    3. 5.3.21.3 System
      1. 5.3.21.3.1 MAIN Domain
        
        118
      2. 5.3.21.3.2 MCU Domain
        
        120
      3. 5.3.21.3.3 WKUP Domain
        
        122
    4. 5.3.21.4 VMON
      1. 124
  23. 5.3.22 TIMER
    1. 5.3.22.1 MAIN Domain
      1. 127
    2. 5.3.22.2 MCU Domain
      1. 129
    3. 5.3.22.3 WKUP Domain
      1. 131
  24. 5.3.23 UART
    1. 5.3.23.1 MAIN Domain
      1. 134
      2. 135
      3. 136
      4. 137
      5. 138
      6. 139
      7. 140
    2. 5.3.23.2 MCU Domain
      1. 142
    3. 5.3.23.3 WKUP Domain
      1. 144
  25. 5.3.24 USB
    1. 5.3.24.1 MAIN Domain
      1. 147
      2. 148
4. 5.4 Pin Connectivity Requirements
6 Specifications
7 Detailed Description
8 Applications, Implementation, and Layout
9 Device and Documentation Support
10Revision History
11Mechanical, Packaging, and Orderable Information
1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

AMB|484

サーマルパッド・メカニカル・データ

発注情報

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6.11.5.11.2 GPMC and NOR Flash — Asynchronous Mode

Table 6-65 and Table 6-66 present timing requirements and switching characteristics for GPMC and NOR Flash — Asynchronous Mode.

Table 6-65 GPMC and NOR Flash Timing Requirements – Asynchronous Mode see Figure 6-51, Figure 6-52, Figure 6-53, and Figure 6-55

NO.	PARAMETER	DESCRIPTION	MODE	MAX	UNIT
FA5^⁽¹⁾	t_acc(d)	Data access time	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	H^⁽⁴⁾	ns
FA20^⁽²⁾	t_{acc1-pgmode(d)}	Page mode successive data access time	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	P^⁽³⁾	ns
FA21^⁽¹⁾	t_{acc2-pgmode(d)}	Page mode first data access time	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	H^⁽⁴⁾	ns

(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field.

(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(3) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁵⁾

(4) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁵⁾

(5) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

Table 6-66 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode see Figure 6-51, Figure 6-52, Figure 6-53, Figure 6-54, Figure 6-55, and Figure 6-56

NO.	PARAMETER	DESCRIPTION	MODE^⁽¹⁵⁾	MIN	MAX	UNIT
NO.	PARAMETER	DESCRIPTION	MODE^⁽¹⁵⁾	133 MHz		UNIT
FA0	t_w(be[x]nV)	Pulse duration, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid time	Read		N ⁽¹²⁾	ns
FA0	t_w(be[x]nV)		Write		N ⁽¹²⁾	ns
FA1	t_w(csnV)	Pulse duration, output chip select GPMC_CSn[i]⁽¹³⁾ low	Read		A ⁽¹⁾	ns
FA1	t_w(csnV)	Pulse duration, output chip select GPMC_CSn[i]⁽¹³⁾ low	Write		A ⁽¹⁾	ns
FA3	t_{d(csnV-advnIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output address valid and address latch enable GPMC_ADVn_ALE invalid	Read	B - 2 ⁽²⁾	B + 2⁽²⁾	ns
FA3	t_{d(csnV-advnIV)}		Write	B - 2⁽²⁾	B + 2⁽²⁾	ns
FA4	t_{d(csnV-oenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn invalid (Single read)	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	C - 2⁽³⁾	C + 2⁽³⁾	ns
FA9	t_d(aV-csnV)	Delay time, output address GPMC_A[27:1] valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	J - 2⁽⁹⁾	J + 2⁽⁹⁾	ns
FA10	t_{d(be[x]nV-csnV)}	Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	J - 2⁽⁹⁾	J + 2⁽⁹⁾	ns
FA12	t_{d(csnV-advnV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output address valid and address latch enable GPMC_ADVn_ALE valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	K - 2⁽¹⁰⁾	K + 2⁽¹⁰⁾	ns
FA13	t_d(csnV-oenV)	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	L - 2⁽¹¹⁾	L + 2⁽¹¹⁾	ns
FA16	t_w(aIV)	Pulse duration output address GPMC_A[26:1] invalid between 2 successive read and write accesses	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	G ⁽⁷⁾		ns
FA18	t_{d(csnV-oenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn invalid (Burst read)	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	I - 2⁽⁸⁾	I + 2⁽⁸⁾	ns
FA20	t_w(aV)	Pulse duration, output address GPMC_A[27:1] valid - 2nd, 3rd, and 4th accesses	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	D ⁽⁴⁾		ns
FA25	t_d(csnV-wenV)	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output write enable GPMC_WEn valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	E - 2⁽⁵⁾	E + 2⁽⁵⁾	ns
FA27	t_{d(csnV-wenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output write enable GPMC_WEn invalid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	F - 2⁽⁶⁾	F + 2⁽⁶⁾	ns
FA28	t_d(wenV-dV)	Delay time, output write enable GPMC_WEn valid to output data GPMC_AD[15:0] valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1		2	ns
FA29	t_d(dV-csnV)	Delay time, output data GPMC_AD[15:0] valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	J - 2⁽⁹⁾	J + 2⁽⁹⁾	ns
FA37	t_d(oenV-aIV)	Delay time, output enable GPMC_OEn_REn valid to output address GPMC_AD[15:0] phase end	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1		2	ns

(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
with n being the page burst access number

(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(7) G = Cycle2CycleDelay × GPMC_FCLK⁽¹⁴⁾

(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁴⁾

(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(15) For div_by_1_mode:

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
- GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz

For TIMEPARAGRANULARITY_X1:

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 6-51 GPMC and NOR Flash — Asynchronous Read — Single Word