JAJSJ32 データシート

JAJSJ32C December 2019 – September 2023 AM6526 , AM6528 , AM6546 , AM6548

PRODUCTION DATA

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

Various external clock inputs are needed to drive the device. Summary of these input clock signals are:

OSC1_XO/OSC1_XI — Еxternal main crystal interface pins connected to internal oscillator which sources reference clock and provides reference clock to PLLs within MAIN domain. Also, for audio applications, high-frequency oscillator 0 is used to provide audio clock frequencies to MCASPs.
WKUP_OSC0_XO/WKUP_OSC0_XI — Еxternal main crystal interface pins connected to internal oscillator which sources reference clock and provides reference clock to PLLs within MCU domain and MAIN domain.
WKUP_LFOSC_XO/WKUP_LFOSC_XI — External main crystal interface pins connected to internal oscillator which sources reference clock provides a clock for low power operation in deeper sleep modes.
MCU_EXT_REFCLK0 — Optional external system clock input (MCU domain).
EXT_REFCLK1— Optional external System clock input (MAIN domain). Optionally PLL2 (PER1) and MCASP can be sourced by EXT_REFCLK1 (sourced externally).
SERDES0_REFCLK P/N and SERDES1_REFCLK P/N — SerDes reference clock for PCIe or Optional USB3.0 PHY.
MCU_CPTS0_RFT_CLK — CPTS reference clock inputs for MCU_CPTS0_RFT_CLK.
CPTS_RFT0_CLK — CPTS reference clock inputs for CPTS0_RFT_CLK.
VOUT1_EXTPCLKIN — Optional for the DPI1 Port of DSS.
REFCLK0 P/N and REFCLK1 P/N — There are 2 differential clock output pins to support 2 PCIe devices.

Figure 6-14 shows the external input clock sources to peripherals.

Figure 6-14 Input Clocks Interface

For more information about Input clock interfaces, see the Clocking section in the device TRM.