JAJSJ32C December   2019  – September 2023 AM6526 , AM6528 , AM6546 , AM6548

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  CAL
        1. 5.3.2.1 MAIN Domain
      3. 5.3.3  CPSW2G
        1. 5.3.3.1 MCU Domain
      4. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 DDRSS Mapping
      5. 5.3.5  DMTIMER
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  DSS
        1. 5.3.6.1 MAIN Domain
      7. 5.3.7  ECAP
        1. 5.3.7.1 MAIN Domain
      8. 5.3.8  EHRPWM
        1. 5.3.8.1 MAIN Domain
      9. 5.3.9  EQEP
        1. 5.3.9.1 MAIN Domain
      10. 5.3.10 GPIO
        1. 5.3.10.1 MAIN Domain
        2. 5.3.10.2 WKUP Domain
      11. 5.3.11 GPMC
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 HyperBus
        1. 5.3.12.1 MCU Domain
      13. 5.3.13 I2C
        1. 5.3.13.1 MAIN Domain
        2. 5.3.13.2 MCU Domain
        3. 5.3.13.3 WKUP Domain
      14. 5.3.14 MCAN
        1. 5.3.14.1 MCU Domain
      15. 5.3.15 MCASP
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 MCSPI
        1. 5.3.16.1 MAIN Domain
        2. 5.3.16.2 MCU Domain
      17. 5.3.17 MMCSD
        1. 5.3.17.1 MAIN Domain
      18. 5.3.18 CPTS
        1. 5.3.18.1 MCU Domain
        2. 5.3.18.2 MAIN Domain
      19. 5.3.19 OLDI
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 OSPI
        1. 5.3.20.1 MCU Domain
      21. 5.3.21 PRU_ICSSG
        1. 5.3.21.1 MAIN Domain
      22. 5.3.22 SERDES
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 UART
        1. 5.3.23.1 MAIN Domain
        2. 5.3.23.2 MCU Domain
        3. 5.3.23.3 WKUP Domain
      24. 5.3.24 USB
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 Emulation and Debug
        1. 5.3.25.1 MAIN Domain
      26. 5.3.26 System and Miscellaneous
        1. 5.3.26.1 Boot Mode Configuration
          1. 5.3.26.1.1 MAIN Domain
          2. 5.3.26.1.2 MCU Domain
        2. 5.3.26.2 Clock
          1. 5.3.26.2.1 MAIN Domain
          2. 5.3.26.2.2 WKUP Domain
        3. 5.3.26.3 System
          1. 5.3.26.3.1 MAIN Domain
          2. 5.3.26.3.2 WKUP Domain
        4. 5.3.26.4 Miscellaneous
          1. 5.3.26.4.1 WKUP Domain
        5. 5.3.26.5 EFUSE
          1. 5.3.26.5.1 MAIN Domain
          2. 5.3.26.5.2 MCU Domain
      27. 5.3.27 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Power-On Hours (POH)
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Operating Performance Points
      1. 6.5.1 Voltage and Core Clock Specifications
    6. 6.6 Electrical Characteristics
      1. 6.6.1 I2C OPEN DRAIN DC Electrical Characteristics
      2. 6.6.2 Analog OSC Buffers DC Electrical Characteristics
      3. 6.6.3 Analog ADC DC Electrical Characteristics
      4. 6.6.4 DPHY CSI2 Buffers DC Electrical Characteristics
      5. 6.6.5 OLDI LVDS Buffers DC Electrical Characteristics
        1. 6.6.5.1 LVCMOS Buffers DC Electrical Characteristics
      6. 6.6.6 USBHS Buffers DC Electrical Characteristics
      7. 6.6.7 SERDES Buffers DC Electrical Characteristics
    7. 6.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8 Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics
    9. 6.9 Timing and Switching Characteristics
      1. 6.9.1 Timing Parameters and Information
      2. 6.9.2 Power Supply Sequencing
        1. 6.9.2.1 Power Supply Slew Rate Requirement
        2. 6.9.2.2 VDDA_1P8_SERDES0 Supply Slew Rate Requirement
        3. 6.9.2.3 Power-Up Sequencing
        4. 6.9.2.4 Power-Down Sequencing
      3. 6.9.3 System Timing
        1. 6.9.3.1 Reset Electrical Data/Timing
        2. 6.9.3.2 Safety Signal Timing
        3. 6.9.3.3 Clock Timing
      4. 6.9.4 Clock Specifications
        1. 6.9.4.1 Input Clocks / Oscillators
          1. 6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
          2. 6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
          4. 6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.9.4.1.5 Auxiliary OSC1 Not Used
          6. 6.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 6.9.4.1.7 WKUP_LFOSC0 LVCMOS Digital Clock Source
          8. 6.9.4.1.8 WKUP_LFOSC0 Not Used
        2. 6.9.4.2 Output Clocks
        3. 6.9.4.3 PLLs
        4. 6.9.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 6.9.4.5 Module and Peripheral Clock Frequencies
      5. 6.9.5 Peripherals
        1. 6.9.5.1  VIN
        2. 6.9.5.2  CPSW2G
          1. 6.9.5.2.1 CPSW2G MDIO Interface Timings
          2. 6.9.5.2.2 CPSW2G RMII Timings
            1. 6.9.5.2.2.1 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. 6.9.5.2.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. 6.9.5.2.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          3. 6.9.5.2.3 CPSW2G RGMII Timings
            1. 6.9.5.2.3.1 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. 6.9.5.2.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. 6.9.5.2.3.3 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. 6.9.5.2.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL - RGMII Mode
        3. 6.9.5.3  CSI2
        4. 6.9.5.4  DDRSS
        5. 6.9.5.5  DSS
        6. 6.9.5.6  eCAP
          1. 6.9.5.6.1 eCAP Timing Requirements
          2. 6.9.5.6.2 eCAP Switching Characteristics
        7. 6.9.5.7  ePWM
          1. 6.9.5.7.1 ePWM Timing Requirements
          2. 6.9.5.7.2 ePWM Switching Characteristics
        8. 6.9.5.8  eQEP
          1. 6.9.5.8.1 eQEP Timing Requirements
          2. 6.9.5.8.2 eQEP Switching Characteristics
        9. 6.9.5.9  GPIO
          1. 6.9.5.9.1 GPIO Timing Requirements
          2. 6.9.5.9.2 GPIO Switching Characteristics
        10. 6.9.5.10 GPMC
          1. 6.9.5.10.1 GPMC and NOR Flash—Synchronous Mode
            1. 6.9.5.10.1.1 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            2. 6.9.5.10.1.2 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 6.9.5.10.2 GPMC and NOR Flash—Asynchronous Mode
            1. 6.9.5.10.2.1 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            2. 6.9.5.10.2.2 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 6.9.5.10.3 GPMC and NAND Flash—Asynchronous Mode
            1. 6.9.5.10.3.1 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            2. 6.9.5.10.3.2 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        11. 6.9.5.11 HyperBus
          1. 6.9.5.11.1 Timing Requirements for HyperBus Initialization
          2. 6.9.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 6.9.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 6.9.5.12 I2C
        13. 6.9.5.13 MCAN
        14. 6.9.5.14 MCASP
          1. 6.9.5.14.1 MCASP Timing Requirements and Switching Characteristics
        15. 6.9.5.15 MCSPI
          1. 6.9.5.15.1 SPI—Master Mode
          2. 6.9.5.15.2 SPI—Slave Mode
        16. 6.9.5.16 MMCSD
          1. 6.9.5.16.1 MMCSDi — eMMC/SD/SDIO Card Interface
            1. 6.9.5.16.1.1 Default Speed, 3.3V Legacy SDR Mode
            2. 6.9.5.16.1.2 High Speed, 3.3V High Speed SDR Mode
            3. 6.9.5.16.1.3 UHS-I SDR12, 1.8-V Legacy SDR Mode
            4. 6.9.5.16.1.4 UHS-I SDR25 Mode
            5. 6.9.5.16.1.5 UHS-I DDR50 Mode
            6. 6.9.5.16.1.6 UHS-I SDR50 Mode
            7. 6.9.5.16.1.7 UHS-I SDR104 / HS200 Mode
        17. 6.9.5.17 CPTS
          1. 6.9.5.17.1 CPTS Timing Requirements
          2. 6.9.5.17.2 CPTS Switching Characteristics
        18. 6.9.5.18 OSPI
          1. 6.9.5.18.1 OSPI with Data Training
            1. 6.9.5.18.1.1 OSPI Switching Characteristics - Data Training
          2. 6.9.5.18.2 OSPI without Data Training
            1. 6.9.5.18.2.1 OSPI Timing Requirements - SDR Mode
            2. 6.9.5.18.2.2 OSPI Switching Characteristics - SDR Mode
            3. 6.9.5.18.2.3 OSPI Timing Requirements - DDR Mode
            4. 6.9.5.18.2.4 OSPI Switching Characteristics - DDR Mode
        19. 6.9.5.19 OLDI
          1. 6.9.5.19.1 OLDI Switching Characteristics
        20. 6.9.5.20 PCIE
        21. 6.9.5.21 PRU_ICSSG
          1. 6.9.5.21.1 Programmable Real-Time Unit (PRU_ICSSG PRU)
            1. 6.9.5.21.1.1 PRU_ICSSG PRU Direct Input/Output Mode Electrical Data and Timing
              1. 6.9.5.21.1.1.1 PRU_ICSSG PRU Switching Characteristics - Direct Output Mode
            2. 6.9.5.21.1.2 PRU_ICSSG PRU Parallel Capture Mode Electrical Data and Timing
              1. 6.9.5.21.1.2.1 PRU_ICSSG PRU Timing Requirements - Parallel Capture Mode
            3. 6.9.5.21.1.3 PRU_ICSSG PRU Shift Mode Electrical Data and Timing
              1. 6.9.5.21.1.3.1 PRU_ICSSG PRU Timing Requirements - Shift In Mode
              2. 6.9.5.21.1.3.2 PRU_ICSSG PRU Switching Characteristics - Shift Out Mode
            4. 6.9.5.21.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Modes Electrical Data and Timing
              1. 6.9.5.21.1.4.1 PRU_ICSSG PRU Timing Requirements - Sigma Delta Mode
              2. 6.9.5.21.1.4.2 PRU_ICSSG PRU Timing Requirements - Peripheral Interface Mode
              3. 6.9.5.21.1.4.3 PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode
          2. 6.9.5.21.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 6.9.5.21.2.1 PRU_ICSSG PWM Electrical Data and Timing
              1. 6.9.5.21.2.1.1 PRU_ICSSG PWM Switching Characteristics
          3. 6.9.5.21.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)
            1. 6.9.5.21.3.1 PRU_ICSSG IEP Electrical Data and Timing
              1. 6.9.5.21.3.1.1 PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx
              2. 6.9.5.21.3.1.2 PRU_ICSSG IEP Timing Requirements - Digital IOs
              3. 6.9.5.21.3.1.3 PRU_ICSSG IEP Timing Requirements - LATCHx_IN
          4. 6.9.5.21.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. 6.9.5.21.4.1 PRU_ICSSG UART Electrical Data and Timing
              1. 6.9.5.21.4.1.1 PRU_ICSSG UART Timing Requirements
              2. 6.9.5.21.4.1.2 PRU_ICSSG UART Switching Characteristics
          5. 6.9.5.21.5 PRU_ICSSG Enhanced Capture Peripheral (PRU-ICSS ECAP)
            1. 6.9.5.21.5.1 PRU_ICSSG ECAP Electrical Data and Timing
              1. 6.9.5.21.5.1.1 PRU_ICSSG ECAP Timing Requirements
              2. 6.9.5.21.5.1.2 PRU_ICSSG ECAP Switching Characteristics
          6. 6.9.5.21.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 6.9.5.21.6.1 PRU_ICSSG MDIO Electrical Data and Timing
              1. 6.9.5.21.6.1.1 PRU_ICSSG MDIO Timing Requirements
              2. 6.9.5.21.6.1.2 PRU_ICSSG MDIO Switching Characteristics - MDIO_CLK
              3. 6.9.5.21.6.1.3 PRU_ICSSG MDIO Switching Characteristics – MDIO_DATA
            2. 6.9.5.21.6.2 PRU_ICSSG RGMII Electrical Data and Timing
              1. 6.9.5.21.6.2.1 PRU_ICSSG RGMII Timing Requirements - RGMII_RXC
              2. 6.9.5.21.6.2.2 PRU_ICSSG RGMII Timing Requirements - RGMII_RD[3:0] and RGMII_RX_CTL
              3. 6.9.5.21.6.2.3 PRU_ICSSG RGMII Switching Characteristics - RGMII_TXC
              4. 6.9.5.21.6.2.4 PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TX_CTL
            3. 6.9.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing
              1. 6.9.5.21.6.3.1 PRU_ICSSG MII_RT Timing Requirements – MII_RX_CLK
              2. 6.9.5.21.6.3.2 PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RX_DV, and MII_RX_ER
              3. 6.9.5.21.6.3.3 PRU_ICSSG MII_RT Switching Characteristics – MII_TX_CLK
              4. 6.9.5.21.6.3.4 PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
        22. 6.9.5.22 Timers
          1. 6.9.5.22.1 Timing Requirements for Timers
          2. 6.9.5.22.2 Switching Characteristics for Timers
        23. 6.9.5.23 UART
          1. 6.9.5.23.1 Timing Requirements for UART
          2. 6.9.5.23.2 Switching Characteristics Over Recommended Operating Conditions for UART
        24. 6.9.5.24 USB
        25. 6.9.5.25 Emulation and Debug
          1. 6.9.5.25.1 Debug Trace
          2. 6.9.5.25.2 JTAG
            1. 6.9.5.25.2.1 JTAG Electrical Data and Timing
              1. 6.9.5.25.2.1.1 JTAG Timing Requirements
              2. 6.9.5.25.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53
      2. 7.2.2 Arm Cortex-R5F
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 PRU_ICSSG
        1. 7.3.1.1 PRU_ICSSG PRU and RTU_PRU Cores
        2. 7.3.1.2 PRU_ICSSG Broadside Accelerators Overview
        3. 7.3.1.3 PRU_ICSSG UART Module
        4. 7.3.1.4 PRU_ICSSG ECAP Module
        5. 7.3.1.5 PRU_ICSSG PWM Module
        6. 7.3.1.6 PRU_ICSSG MII_G_RT Module
        7. 7.3.1.7 PRU_ICSSG MII MDIO Module
        8. 7.3.1.8 PRU_ICSSG IEP
      2. 7.3.2 GPU
    4. 7.4 Other Subsystems
      1. 7.4.1 DMSC
      2. 7.4.2 MSMC
      3. 7.4.3 NAVSS
        1. 7.4.3.1 NAVSS0
        2. 7.4.3.2 MCU_NAVSS0
      4. 7.4.4 PDMA Controller
      5. 7.4.5 Peripherals
        1. 7.4.5.1  ADC
        2. 7.4.5.2  CAL
        3. 7.4.5.3  CPSW2G
        4. 7.4.5.4  DCC
        5. 7.4.5.5  DDRSS
        6. 7.4.5.6  DSS
        7. 7.4.5.7  ЕCAP
        8. 7.4.5.8  EPWM
        9. 7.4.5.9  ELM
        10. 7.4.5.10 ESM
        11. 7.4.5.11 EQEP
        12. 7.4.5.12 GPIO
        13. 7.4.5.13 GPMC
        14. 7.4.5.14 HyperBus
        15. 7.4.5.15 I2C
        16. 7.4.5.16 MCAN
        17. 7.4.5.17 MCASP
        18. 7.4.5.18 MCRC
        19. 7.4.5.19 MCSPI
        20. 7.4.5.20 MMCSD
        21. 7.4.5.21 OSPI
        22. 7.4.5.22 PCIE
        23. 7.4.5.23 SerDes
        24. 7.4.5.24 RTI
        25. 7.4.5.25 Timers
        26. 7.4.5.26 UART
        27. 7.4.5.27 USB
    5. 7.5 Identification
      1. 7.5.1 Revision Identification
      2. 7.5.2 Die Identification
      3. 7.5.3 JTAG Identification
      4. 7.5.4 ROM Code Identification
    6. 7.6 Boot Modes
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.1.1.1 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG and EMU
      4. 8.1.4 Reset
      5. 8.1.5 Unused Pins
      6. 8.1.6 Hardware Design Guide for AM65x/DRA80xM Devices
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (Only Available in Octal Flash Devices)
      3. 8.2.3 USB Design Guidelines
      4. 8.2.4 High Speed Differential Signal Routing Guidance
      5. 8.2.5 System Power Supply Monitor Design Guidelines
      6. 8.2.6 MMC Design Guidelines
      7. 8.2.7 Integrated Power Management Features
      8. 8.2.8 External Capacitors
        1. 8.2.8.1 LVCMOS External Capacitor Connections
      9. 8.2.9 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • ACD|784
サーマルパッド・メカニカル・データ
発注情報

5.3.27 Power Supply

Table 5-75 Power Supply Signal Description
SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4]
CAP_VDDAR_CORE0(1) External capacitor connection for CORE SRAM LDOs CAP P17
CAP_VDDAR_CORE1(1) External capacitor connection for CORE SRAM LDOs CAP V17
CAP_VDDAR_CORE2(1) External capacitor connection for CORE SRAM LDOs CAP W16
CAP_VDDAR_CORE3(1) External capacitor connection for MSMC SRAM LDOs CAP M14
CAP_VDDAR_CORE4(1) External capacitor connection for MSMC SRAM LDOs CAP L15
CAP_VDDAR_MCU(1) External capacitor connection for MCU SRAM LDO CAP U10
CAP_VDDAR_MPU0_0(1) External capacitor connection for MPU SRAM LDOs CAP M12
CAP_VDDAR_MPU0_1(1) External capacitor connection for MPU SRAM LDOs CAP N12
CAP_VDDAR_MPU1_0(1) External capacitor connection for MPU SRAM LDOs CAP N18
CAP_VDDAR_MPU1_1(1) External capacitor connection for MPU SRAM LDOs CAP N15
CAP_VDDAR_WKUP(1) External capacitor connection for WKUP SRAM LDO CAP Y10
CAP_VDDA_1P8_IOLDO_WKUP(1) External capacitor connection for IO Bias LDO in WKUP domain CAP AA8
CAP_VDDA_1P8_SDIO(2) External capacitor connection for SDIO LDO CAP J17
CAP_VDDA_1P8_IOLDO0(1) External capacitor connection for IO Bias LDO CAP G19
CAP_VDDA_1P8_IOLDO1(1) External capacitor connection for IO Bias LDO CAP Y19
CAP_VDDSHV_SDIO(2)(3) External capacitor connection for SDIO LDO CAP H18
CAP_VDD_WKUP(1) External capacitor connection for WKUP LDO CAP V9
VDDA_1P8_MON_WKUP Supply monitor in WKUP domain A AB6
VDDA_1P8_SDIO(2) SDIO LDO analog power supply PWR G17
VDDA_1P8_CSI0 CSI PHY analog power supply PWR L20, M21
VDDA_1P8_MON0 Supply monitor in MAIN domain A AC6
VDDA_1P8_OLDI0 OLDI analog power supply PWR L22
VDDA_1P8_SERDES0 SERDES0/1 (USB, PCIE) analog power supply PWR AA14, AB13, AB15
VDDA_3P3_IOLDO_WKUP WKUP IO Bias LDO analog power supply PWR AB9
VDDA_3P3_MON_WKUP Supply monitor in WKUP domain A U6
VDDA_3P3_SDIO(2) SDIO LDO analog power supply PWR H17
VDDA_3P3_USB USB analog power supply PWR AC12
VDDA_3P3_IOLDO0 IO Bias LDO analog power supply PWR G18
VDDA_3P3_IOLDO1 IO Bias LDO analog power supply PWR AA21
VDDA_3P3_MON0 Supply monitor in MAIN domain A AC10
VDDA_ADC_MCU ADC0, ADC1 analog power supply PWR M7, M9
VDDA_LDO_WKUP WKUP LDO analog power supply PWR AB8
VDDA_MCU MCU SRAM LDO, MCU DPLL, CPSW DPLL analog power supply PWR U12
VDDA_PLL0_DDR DDR DPLL analog power supply PWR H15
VDDA_PLL1_DDR DDR De-skew DPLL analog power supply PWR H11
VDDA_PLL_CORE CORE DPLL, PER1 DPLL analog power supply PWR Y17
VDDA_PLL_DSS DSS DPLL analog power supply PWR L21
VDDA_PLL_MPU0 MPU0 DPLL analog power supply PWR L12
VDDA_PLL_MPU1 MPU1 DPLL analog power supply PWR K15
VDDA_PLL_PER0 PER0 DPLL analog power supply PWR AB7
VDDA_POR_WKUP(5) WKUP POR/POK analog power supply PWR Y9
VDDA_SRAM_CORE0 CORE SRAM LDOs analog power supply PWR M19
VDDA_SRAM_CORE1 CORE SRAM LDOs analog power supply PWR V16
VDDA_SRAM_MPU0 MPU SRAM LDOs analog power supply PWR K7
VDDA_SRAM_MPU1 MPU SRAM LDOs analog power supply PWR L18
VDDA_VSYS_MON(6) Supply monitor for system A AC11
VDDA_WKUP WKUP High/Low Frequency Oscillator (WKUP_LFOSC0 / WKUP_OSC0), SRAM LDO analog power supply PWR AA9
VDDS0 IO bias supply for VDDSHV0 PWR G12
VDDS0_WKUP IO bias supply for VDDSHV0_WKUP PWR V8
VDDS1 IO bias supply for VDDSHV1 PWR AA16
VDDS1_WKUP IO bias supply for VDDSHV1_WKUP PWR T9
VDDS2 IO bias supply for VDDSHV2 PWR P20
VDDS2_WKUP IO bias supply for VDDSHV2_WKUP PWR N8
VDDS3 IO bias supply for VDDSHV3 PWR T20
VDDS4 IO bias supply for VDDSHV4 PWR Y20
VDDS5 IO bias supply for VDDSHV5 PWR AC18
VDDS6 IO bias supply for VDDSHV6 PWR F20
VDDS7 IO bias supply for VDDSHV7 PWR K20
VDDS8 IO bias supply for VDDSHV8 PWR AA10
VDDSHV0 Dual-voltage IO domain power supply PWR G15, H16
VDDSHV0_WKUP Dual-voltage IO domain power supply PWR U8, V7, W8, Y7
VDDSHV1 Dual-voltage IO domain power supply PWR AA18, AB17
VDDSHV1_WKUP Dual-voltage IO domain power supply PWR R6, R8, T7
VDDSHV2 Dual-voltage IO domain power supply PWR N20, N22, P21, R20, R22
VDDSHV2_WKUP Dual-voltage IO domain power supply PWR N6, P7, P9
VDDSHV3 Dual-voltage IO domain power supply PWR T21, U20, U22, V21, V23
VDDSHV4 Dual-voltage IO domain power supply PWR AA22, W20, W22, Y21, Y23
VDDSHV5 Dual-voltage IO domain power supply PWR AA20, AB19, AB21, AB23
VDDSHV6 Dual-voltage IO domain power supply PWR G20, H19, H21
VDDSHV7 Dual-voltage IO domain power supply PWR J20, J22, K21
VDDSHV8 Dual-voltage IO domain power supply PWR AB11
VDDS_DDR DDR IO domain power supply PWR G10, G14, G8, H13, H7, H9
VDDS_OSC1 MAIN High Frequency Oscillator (OSC1) analog power supply PWR J16
VDD_CORE CORE voltage domain supply PWR AA12, J10, J12, J14, J19, J8, K13, L14, L19, M13, N14, P13, P15, P19, R14, R16, R18, T13, T15, T17, T19, U14, U16, U18, V13, V15, V19, W14, W18, Y11, Y13, Y15
VDD_DLL_MMC0 MMC0 PHY DLL voltage supply PWR G22
VDD_DLL_MMC1 MMC1 PHY DLL voltage supply PWR H23
VDD_MCU MCU voltage domain supply PWR N10, P11, R10, R12, T11
VDD_MPU0 MPU0 voltage domain supply PWR K11, K9, L10, L8, M11
VDD_MPU1 MPU1 voltage domain supply PWR K16, K18, L17, M16, M18, N17
VDD_WKUP0(4) WKUP voltage domain supply PWR V11, W10, W12
VDD_WKUP1(4) WKUP voltage domain supply PWR M22
VSS Ground GND A1, A2, A28, AA11, AA13, AA15, AA17, AA19, AA23, AA26, AA7, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AD4, AE10, AE25, AE5, AF15, AF2, AF20, AF8, AG1, AG10, AG28, AG4, AG7, AH1, AH11, AH2, AH27, AH28, AH5, AH8, B12, B15, B20, B6, B9, D22, E26, E28, E4, F14, F19, F22, F25, F27, F3, G11, G13, G16, G2, G21, G23, G7, G9, H1, H10, H12, H14, H20, H22, H24, H26, H28, H6, H8, J11, J13, J15, J18, J21, J23, J25, J27, J7, J9, K1, K10, K12, K14, K17, K19, K22, K23, K6, K8, L11, L13, L16, L23, L24, L26, L28, L3, L7, L9, M10, M15, M17, M20, M8, N11, N13, N16, N19, N21, N7, N9, P10, P12, P14, P16, P18, P22, P6, P8, R11, R13, R15, R17, R19, R21, R7, R9, T10, T12, T14, T16, T18, T22, T26, T8, U11, U13, U15, U17, U19, U21, U3, U7, U9, V10, V12, V14, V18, V20, V22, V6, W11, W13, W15, W17, W19, W21, W23, W7, W9, Y12, Y14, Y16, Y18, Y22, Y6, Y8
(1) This pin must always be connected via a 1-µF capacitor to VSS.
(2) The net connecting CAP_VDDA_1P8_SDIO and VDDA_1P8_SDIO to VDDS6 or VDDS7 must be connected to a 3.3-uF decoupling capacitor. VDDA_1P8_SDIO, CAP_VDDA_1P8_SDIO, CAP_VDDSHV_SDIO, and VDDA_3P3_SDIO must be connected to VSS, when SDIO_LDO is not used with either MMC0 or MMC1.
(3) When CAP_VDDSHV_SDIO is connected to VDDSHV6 or VDDSHV7, the entire net which connects these pins should not exceed 6-uF of decoupling capacitance. VDDA_1P8_SDIO, CAP_VDDA_1P8_SDIO, CAP_VDDSHV_SDIO, and VDDA_3P3_SDIO must be connected to VSS, when SDIO_LDO is not used with either MMC0 or MMC1.
(4) These power rails should be connected together on the board level.
(5) VDDA_POR_WKUP is preferred to be connected to CAP_VDDA_1P8_IOLDO_WKUP when using internal POR feature.
(6) The VDDA_VSYS_MON pin provides a way to monitor the system power supply and is not fail-safe, unless implemented with the appropriate resistor voltage divider source. For more information, see Section 8.2.5, System Power Supply Monitor Design Guidelines.