JAJSJ32 データシート

JAJSJ32C December 2019 – September 2023 AM6526 , AM6528 , AM6546 , AM6548

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メカニカル・データ（パッケージ｜ピン）

ACD|784

サーマルパッド・メカニカル・データ

発注情報

6.9.5.10.2.1 GPMC and NOR Flash Timing Requirements—Asynchronous Mode

NO.	PARAMETER	DESCRIPTION	MODE	MAX	UNIT
FA5⁽¹⁾	t_acc(d)	Data access time	div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1	H ⁽⁴⁾	ns
FA20⁽²⁾	t_{acc1-pgmode(d)}	Page mode successive data access time	div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1	P ⁽³⁾	ns
FA21⁽¹⁾	t_{acc2-pgmode(d)}	Page mode first data access time	div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1	H ⁽⁴⁾	ns

(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field.

(2) The FA20 prameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(3) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁵⁾

(4) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁵⁾

(5) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.