SBASAY6 December 2024 AMC0236
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If a fullscale input signal is applied to the AMC0x36, the device generates a single one or zero every 128 bits at DOUT. Figure 7-5 shows a timing diagram of this process. A single 1 or 0 is generated depending on the actual polarity of the signal being sensed. A fullscale signal is defined as |VINP – VSNSN| ≥ |VClipping|. In this way, differentiating between a missing AVDD and a fullscale input signal is possible on the system level. See the Diagnosing Delta-Sigma Modulator Bitstream Using C2000™ Configurable Logic Block (CLB) application note for code examples of diagnosing the digital bitstream.