SBASAT2 December   2024 AMC0386

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Modulator
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Digital Output
        1. 7.3.4.1 Output Behavior in Case of a Fullscale Input
        2. 7.3.4.2 Output Behavior in Case of a Missing High-Side Supply
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Filter Design
        2. 8.2.2.2 Bitstream Filtering
        3. 8.2.2.3 Application Curve
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DFX|15
サーマルパッド・メカニカル・データ
発注情報

7.4 Device Functional Modes

The AMC0386 operates in one of the following states:

  • OFF-state: The low-side of the device (DVDD) is below the DVDDUV threshold. The device is not responsive. OUT is Hi-Z state. Internally, OUT and CLKIN are clamped to DVDD and DGND by ESD protection diodes.
  • Missing high-side supply: The low-side of the device (DVDD) is supplied and within Recommended Operating Conditions. The high-side supply (AVDD) is below the AVDDUV threshold. The device outputs a constant bitstream of logic 0s, as described in the section.
  • Analog input overrange (positive fullscale input): AVDD and DVDD are within recommended operating conditions but the analog input voltage VIN = (VSNSP– VSNSN) is above the maximum clipping voltage (VClipping, MAX). The device outputs a logic 0 every 128 clock cycles, as described in the Output Behavior in Case of a Fullscale Input section.
  • Analog input underrange (negative fullscale input): AVDD and DVDD are within recommended operating conditions but the analog input voltage VIN = (VSNSP– VSNSN) is below the minimum clipping voltage (VClipping, MIN). The device outputs a logic 1 every 128 clock cycles, as described in the Output Behavior in Case of a Fullscale Input section.
  • Normal operation: AVDD, DVDD, and VIN are within the recommended operating conditions. The device outputs a digital bitstream, as explained in the Digital Output section.

Table 7-1 lists the operational modes.

Table 7-1 Device Operational Modes
OPERATINAL
MODE		 AVDD DVDD VIN DEVICE
RESPONSE
OFF Don't care VDVDD < DVDDUV Don't care OUT is Hi-Z state. Internally, OUT and CLKIN are clamped to DVDD and DGND by ESD protection diodes.
Missing high-side supply VAVDD < AVDDUV Valid(1) Don't care The device outputs a constant bitstream of logic 0s, as described in the section.
Input overrange Valid(1) Valid(1) VIN > VClipping, MAX The device outputs a logic 0 every 128 clock cycles, as described in the Output Behavior in Case of a Fullscale Input section.
Input underrange Valid(1) Valid(1) VIN < VClipping, MIN The device outputs a logic 1 every 128 clock cycles, as described in the Output Behavior in Case of a Fullscale Input section.
Normal operation Valid(1) Valid(1) Valid(1) Normal operation
(1) "Valid" denotes within the recommended operating conditions.