JAJSS45 August 2024 AMC3306M05-Q1
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The device generates a single one or zero every 128 bits at DOUT if an input signal is applied that exceeds the clipping voltage. This voltage is defined as (|VIN| ≥ VClipping). Figure 6-5 shows the full-scale output timing, which is dependent on the actual polarity of the signal being sensed. In this way, differentiating between a missing high-side supply and a full-scale input signal is possible on the system level.