JAJSCI6C August 2016 – December 2018 AMIC110
PRODUCTION DATA.
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TI only supports board designs that follow the guidelines outlined in this document. Table 7-45 and Figure 7-38 show the switching characteristics and timing diagram for the DDR2 memory interface.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | tc(DDR_CK)
tc(DDR_CKn) |
Cycle time, DDR_CK and DDR_CKn | 3.75 | 8(1) | ns |