JAJSEW2D May   2017  – December 2021 AWR1243

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1 Power Supply Sequencing and Reset Timing
      2. 8.9.2 Synchronized Frame Triggering
      3. 8.9.3 Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
          1. 8.9.4.1.1 SPI Timing Conditions
          2. 8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5 LVDS Interface Configuration
        1. 8.9.5.1 LVDS Interface Timings
      6. 8.9.6 General-Purpose Input/Output
        1. 8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 8.9.7 Camera Serial Interface (CSI)
        1. 8.9.7.1 CSI Switching Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Host Interface
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Data Format Over CSI2 Interface
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Short-, Medium-, and Long-Range Radar
    3. 11.3 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ABL|161
サーマルパッド・メカニカル・データ
発注情報

7.2.1 Signal Descriptions

FUNCTIONSIGNAL NAMEPIN NUMBERPIN TYPEDEFAULT PULL STATUS(1)DESCRIPTION
TransmittersTX1B4O—Single-ended transmitter1 o/p
TX2B6O—Single-ended transmitter2 o/p
TX3B8O—Single-ended transmitter3 o/p
ReceiversRX1M2I—Single-ended receiver1 i/p
RX2K2I—Single-ended receiver2 i/p
RX3H2I—Single-ended receiver3 i/p
RX4F2I—Single-ended receiver4 i/p
CSI2 TXCSI2_TXP[0]G15O—Differential data Out – Lane 0 (for CSI and LVDS debug interface)
CSI2_TXM[0]G14O—
CSI2_CLKPJ15O—Differential clock Out (for CSI and LVDS debug interface)
CSI2_CLKMJ14O—
CSI2_TXP[1]H15O—Differential data Out – Lane 1 (for CSI and LVDS debug interface)
CSI2_TXM[1]H14O—
CSI2_TXP[2]K15O—Differential data Out – Lane 2 (for CSI and LVDS debug interface)
CSI2_TXM[2]K14O—
CSI2_TXP[3]L15O—Differential data Out – Lane 3 (for CSI and LVDS debug interface)
CSI2_TXM[3]L14O—
HS_DEBUG1_PM15O—Differential debug port 1 (for LVDS debug interface)
HS_DEBUG1_MM14O—
HS_DEBUG2_PN15O—Differential debug port 2 (for LVDS debug interface)
HS_DEBUG2_MN14O—
Reserved SpaceFM_CW_CLKOUTB15O—Reserved Signal. Not applicable in AWR1243.
FM_CW_SYNCOUTD1
FM_CW_SYNCIN1B1I—Reserved Signal. Not applicable in AWR1243.
FM_CW_SYNCIN2D15
Reference clockOSC_CLKOUTA14O—Reference clock output from clocking subsystem after cleanup PLL. Can be used by peripheral chip in multichip cascading
System synchronizationSYNC_OUTP11OPull DownLow-frequency frame synchronization signal output. Can be used by peripheral chip in multichip cascading
SYNC_INN10IPull DownLow-frequency frame synchronization signal input.
This signal could also be used as a hardware trigger for frame start
SPI control interface from external MCU (default peripheral mode)SPI_CS_1R7IPull UpSPI chip select
SPI_CLK_1R9IPull DownSPI clock
MOSI_1R8IPull UpSPI data input
MISO_1P5OPull UpSPI data output
SPI_HOST_INTR_1P6OPull DownSPI interrupt to host
RESERVEDR3, R4, R5, P4—
ResetNRESETP12I—Power on reset for chip. Active low
WARM_RESET(2)N12IOOpen DrainOpen-drain fail-safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.
SOP2P13IThe SOP pins are driven externally (weak drive) and the AWR device senses the state of these pins during bootup to decide the bootup mode. After boot the same pins have other functionality.
[SOP2 SOP1 SOP0] = [0 0 1] → Functional SPI mode
[SOP2 SOP1 SOP0] = [1 0 1] → Flashing mode
[SOP2 SOP1 SOP0] = [0 1 1] → debug mode
Sense on PowerSOP1P11I—
SOP0J13I
SafetyNERROR_OUTN8OOpen DrainOpen-drain fail-safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.
NERROR_INP7IOpen DrainFail-safe input to the device. Error output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by firmware
JTAGTMSL13IPull UpJTAG port for TI internal development
TCKM13IPull Down
TDIH13IPull Up
TDOJ13O—
Reference oscillatorCLKPE14I—In XTAL mode: Input for the reference crystal
In External clock mode: Single ended input reference clock port
CLKMF14O— In XTAL mode: Feedback drive for the reference crystal
In External clock mode: Connect this port to ground
Band-gap voltageVBGAPB10O—
Power supplyVDDINF13,N11,P15,R6POW—1.2-V digital power supply
VIN_SRAMR14POW—1.2-V power rail for internal SRAM
VNWAP14POW—1.2-V power rail for SRAM array back bias
VIOINR13POW—I/O supply (3.3-V or 1.8-V): All CMOS I/Os would operate on this supply.
VIOIN_18K13POW—1.8-V supply for CMOS IO
VIN_18CLKB11POW—1.8-V supply for clock module
VIOIN_18DIFFD13POW—1.8-V supply for CSI2 port
ReservedG13POW—No connect
VIN_13RF1G5,J5,H5POW—1.3-V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the board
VIN_13RF2C2,D2POW—
VIN_18BBK5,F5POW—1.8-V Analog baseband power supply
VIN_18VCOB12POW—1.8-V RF VCO supply
VSSE5,E6,E8,E10,E11,F9,F11,G6,G7,G8,G10,H7,H9,H11,J6,J7,J8,J10,K7,K8,K9,K10,K11,L5,L6,L8,L10,R15GND—Digital ground
VSSAA1,A3,A5,A7,A9,A15,B3,B5,B7,B9,B13,B14,C1,C3,C4,C5,C6,C7,C8,C9,C15,E1,E2,E3,E13,E15,F3,G1,G2,G3,H3,J1,J2,J3,K3,L1,L2,L3, M3,N1,N2,N3,R1GND—Analog ground
Internal LDO output/inputsVOUT_14APLLA10O—
VOUT_14SYNTHA13O—
VOUT_PAA2,B2IO—When internal PA LDO is used this pin provides the output voltage of the LDO. When the internal PA LDO is bypassed and disabled 1V supply should be fed on this pin. This is mandatory in 3TX simultaneous use case.
External clock outPMIC_CLK_OUTP13O—Dithered clock input to PMIC
MCU_CLK_OUTN9O—Programmable clock given out to external MCU or the processor
General-purpose I/OsGPIO[0]N4IOPull DownGeneral-purpose IO
GPIO[1]N7IOPull DownGeneral-purpose IO
GPIO[2]N13IOPull DownGeneral-purpose IO
QSPI for Serial FlashQSPI_CSP8OPull UpChip-select output from the device. Device is a controller connected to serial flash peripheral.
QSPI_CLKR10OPull DownClock output from the device. Device is a controller connected to serial flash peripheral.
QSPI[0]R11IOPull DownData IN/OUT
QSPI[1]P9IOPull DownData IN/OUT
QSPI[2]R12IOPull UpData IN/OUT
QSPI[3]P10IOPull UpData IN/OUT
Flash programming and RS232 UARTRS232_TXN6OPull DownUART pins for programming external flash
RS232_RXN5IPull Up
Test and Debug output for preproduction phase. Can be pinned out on production hardware for field debugAnalog Test1 P1IO—Internal test signal
Analog Test2 P2IO—Internal test signal
Analog Test3 P3IO—Internal test signal
Analog Test4 R2IO—Internal test signal
ANAMUX C13IO—Internal test signal
VSENSE C14IO—Internal test signal
(1) Status of PULL structures associated with the IO after device POWER UP.
(2) For the AWR1243 WARM_RESET can be used as an output only pin for status indication.