JAJSEW3C may   2017  – january 2022 AWR1443

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 機能ブロック図
  6. 5 Revision History
  7. 6 Device Comparison
    1. 6.1 Related Products
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
    3. 7.3 Pin Multiplexing
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1  Power Supply Sequencing and Reset Timing
      2. 8.9.2  Synchronized Frame Triggering
      3. 8.9.3  Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
        2. 8.9.4.2 MibSPI Transmit and Receive RAM Organization
          1. 8.9.4.2.1 SPI Timing Conditions
          2. 8.9.4.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
          3. 8.9.4.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
        3. 8.9.4.3 SPI Peripheral Mode I/O Timings
          1. 8.9.4.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-70 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-71 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-73
        4. 8.9.4.4 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5  LVDS Interface Configuration
        1. 8.9.5.1 LVDS Interface Timings
      6. 8.9.6  General-Purpose Input/Output
        1. 8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 8.9.7  Controller Area Network Interface (DCAN)
        1. 8.9.7.1 Dynamic Characteristics for the DCANx TX and RX Pins
      8. 8.9.8  Serial Communication Interface (SCI)
        1. 8.9.8.1 SCI Timing Requirements
      9. 8.9.9  Inter-Integrated Circuit Interface (I2C)
        1. 8.9.9.1 I2C Timing Requirements #GUID-36963FBF-DA1A-4FF8-B71D-4A185830E708/T4362547-185
      10. 8.9.10 Quad Serial Peripheral Interface (QSPI)
        1. 8.9.10.1 QSPI Timing Conditions
        2. 8.9.10.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-210 #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-209
        3. 8.9.10.3 QSPI Switching Characteristics
      11. 8.9.11 JTAG Interface
        1. 8.9.11.1 JTAG Timing Conditions
        2. 8.9.11.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.9.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 External Interfaces
    4. 9.4 Subsystems
      1. 9.4.1 RF and Analog Subsystem
        1. 9.4.1.1 Clock Subsystem
        2. 9.4.1.2 Transmit Subsystem
        3. 9.4.1.3 Receive Subsystem
        4. 9.4.1.4 Radio Processor Subsystem
      2. 9.4.2 Main (Control) System
      3. 9.4.3 Host Interface
    5. 9.5 Accelerators and Coprocessors
    6. 9.6 Other Subsystems
      1. 9.6.1 ADC Channels (Service) for User Application
        1. 9.6.1.1 GP-ADC Parameter
    7. 9.7 Boot Modes
      1. 9.7.1 Flashing Mode
      2. 9.7.2 Functional Mode
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short-Range Radar
    3. 10.3 Blind Spot Detector and Ultrasonic Upgrades
    4. 10.4 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ABL|161
サーマルパッド・メカニカル・データ
発注情報

8.5 Power Supply Specifications

Table 8-1 describes the four rails from an external power supply block of the AWR1443 device.

Table 8-1 Power Supply Rails Characteristics
SUPPLY DEVICE BLOCKS POWERED FROM THE SUPPLY RELEVANT IOS IN THE DEVICE
1.8 V Synthesizer and APLL VCOs, crystal oscillator, IF Amplifier stages, ADC, LVDS Input: VIN_18VCO, VIN18CLK, VIN_18BB, VIOIN_18DIFF, VIOIN_18
LDO Output: VOUT_14SYNTH, VOUT_14APLL
1.3 V (or 1 V in internal LDO bypass mode)(1) Power Amplifier, Low Noise Amplifier, Mixers and LO Distribution Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V I/O mode) Digital I/Os Input VIOIN
1.2 V Core Digital and SRAMs Input: VDDIN, VIN_SRAM
(1) Three simultaneous transmitter operation is supported only in 1-V LDO bypass and PA LDO disable mode. In this mode 1V supply needs to be fed on the VOUT PA pin.

The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in are defined to meet a target spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB relationship, for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted are rms levels for a sinusoidal input applied at the specified frequency.

Table 8-2 Ripple Specifications
FREQUENCY (kHz) RF RAIL VCO/IF RAIL
1.0 V (INTERNAL LDO BYPASS) (µVRMS) 1.3 V (µVRMS) 1.8 V (µVRMS)
137.5 7 648 83
275 5 76 21
550 3 22 11
1100 2 4 6
2200 11 82 13
4400 13 93 19
6600 22 117 29